Notebook computer battery charging and discharging control circuit and battery management system

Abstract

The utility model provides a charge and discharge control circuit of a notebook computer battery. The charge and discharge control circuit of the notebook computer battery comprises a main control module, a battery management chip, a first electronic switch tube, a second electronic switch tube, a first pull-down resistor, a linear voltage regulator and a negative voltage chip. The linear voltage regulator is connected with the first electronic switching tube and detects virtual voltage. And the negative voltage chip is connected with the linear voltage regulator and the second electronic switching tube, and the working state of the negative voltage chip is controlled by the main control module. When the circuit enters a shutdown sleep mode and virtual voltage exists, the virtual voltage is detected and obtained through the linear voltage regulator, the negative voltage chip is driven to output negative voltage to the control end of the second electronic switch tube, a conductive channel cannot be formed in the second electronic switch tube, the second electronic switch tube cannot be switched on due to the virtual voltage, and therefore the circuit can be switched on. Therefore, the problem of electric leakage of the charging and discharging control circuit of the notebook computer battery in the shutdown sleep mode is avoided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of notebook battery management, and particularly relates to a notebook battery charging and discharging control circuit and a battery management system. BACKGROUND

[0002] In the prior art, a notebook battery power management scheme generally adopts a combination scheme of a power meter, a low-resistance MOS tube and a three-terminal fuse protector. The scheme integrates multiple protection functions such as overvoltage, undervoltage and overcurrent, and controls the switching state of the charging and discharging MOS tube through the cooperative work of the secondary protection IC and the power meter, so as to realize effective management of the battery.

[0003] However, there are still some technical defects in actual application. The conventional low-voltage low-resistance MOS device adopts SGT manufacturing process, which can reduce the specific on-resistance and gate charge of the device and improve the high-temperature and large-current capability of the device. However, when the battery is packaged and enters the low-power sleep mode, due to the specific structure of the MOS device, voltage difference is easy to accumulate between the sources, causing electrons to form a small path through the MOS, resulting in the existence of voltage between the positive and negative electrodes of the notebook battery, and causing the notebook battery to be unable to effectively enter the low-power sleep mode, thereby affecting the yield and test efficiency of the production line. In addition, the battery of the notebook after completion of the installation may be consumed too fast in a long time of non-use, and even the power meter may be damaged due to the low voltage, thereby causing the notebook battery to be unable to work normally. CONTENT OF THE UTILITY MODEL

[0004] The purpose of the present disclosure is to overcome the deficiencies in the prior art, and to provide a notebook battery charging and discharging control circuit and a battery management system which can completely turn off the MOS tube in the shutdown sleep mode.

[0005] The purpose of the present disclosure is achieved by the following technical solutions:

[0006] The notebook battery charging and discharging control circuit comprises a master control module, a battery management chip, a first electronic switch tube, a second electronic switch tube, a first pull-down resistor, a linear voltage regulator and a negative voltage chip, a first end of the first electronic switch tube is used for being connected with a cell power supply end, a control end of the first electronic switch tube is connected with a charging signal end of the battery management chip, a second end of the first electronic switch tube is connected with a power signal end of the battery management chip, a first end of the second electronic switch tube is connected with the power signal end of the battery management chip, a control end of the second electronic switch tube is connected with a discharging signal end of the battery management chip, a second end of the second electronic switch tube is used for being connected with the master control module, a first end of the first pull-down resistor is connected with the control end of the second electronic switch tube, a second end of the first pull-down resistor is connected with the second end of the second electronic switch tube, and a power supply end of the battery management chip is used for being connected with the cell power supply end.

[0007] A power supply end of the linear voltage regulator is connected with the first end of the first electronic switch tube, a power supply enable end of the linear voltage regulator is connected with the second end of the second electronic switch tube, an output end of the linear voltage regulator is connected with a power input end of the negative voltage chip, an output end of the negative voltage chip is connected with the control end of the second electronic switch tube, an enable control end of the negative voltage chip is connected with a negative voltage signal end of the master control module, and a sleep signal end of the master control module is connected with a sleep control end of the battery management chip.

[0008] In one of the embodiments, the notebook battery charging and discharging control circuit further comprises a first voltage dividing resistor, a first end of the first voltage dividing resistor is connected with the first end of the first electronic switch tube, and a second end of the first voltage dividing resistor is connected with the power supply end of the linear voltage regulator.

[0009] In one of the embodiments, the notebook battery charging and discharging control circuit further comprises a first filter capacitor, a first end of the first filter capacitor is connected with the power supply end of the linear voltage regulator, and a second end of the first filter capacitor is grounded.

[0010] In one of the embodiments, the notebook battery charging and discharging control circuit further comprises a second voltage dividing resistor, a first end of the second voltage dividing resistor is connected with the charging signal end of the battery management chip, and a second end of the second voltage dividing resistor is connected with the control end of the first electronic switch tube.

[0011] In one of the embodiments, the notebook battery charging and discharging control circuit further comprises a current limiting resistor, a first end of the current limiting resistor is connected with the power signal end of the battery management chip, and a second end of the current limiting resistor is connected with the second end of the first electronic switch tube and the first end of the second electronic switch tube respectively.

[0012] In one of the embodiments, the notebook battery charge and discharge control circuit further comprises a second pull-down resistor, a first end of the second pull-down resistor is connected with the control end of the first electronic switch tube, and a second end of the second pull-down resistor is connected with the second end of the first electronic switch tube.

[0013] In one of the embodiments, the notebook battery charge and discharge control circuit further comprises a voltage stabilizing diode, a positive electrode of the voltage stabilizing diode is connected with the control end of the second electronic switch tube, and a negative electrode of the voltage stabilizing diode is connected with the output end of the negative voltage chip.

[0014] In one of the embodiments, the notebook battery charge and discharge control circuit further comprises a current guide diode, a positive electrode of the current guide diode is connected with the second end of the second electronic switch tube, and a negative electrode of the current guide diode is connected with the power supply enable end of the linear voltage stabilizer.

[0015] In one of the embodiments, the first electronic switch tube and the second electronic switch tube are both SGT-NMOS tubes.

[0016] A battery management system comprising the notebook battery charge and discharge control circuit of any one of the above.

[0017] Compared with the prior art, the present disclosure has at least the following advantages:

[0018] 1. The notebook battery charge and discharge control circuit described above, under the original technical framework, a linear voltage stabilizer and a negative voltage chip are added, when the notebook battery charge and discharge control circuit enters the shutdown sleep mode and there is a virtual voltage, the linear voltage stabilizer detects and obtains the virtual voltage, so as to drive the negative voltage chip to enter the working state and output a negative voltage to the control end of the second electronic switch tube, so that the conduction channel cannot be formed in the second electronic switch tube, thereby avoiding the problem of electric leakage of the notebook battery charge and discharge control circuit in the shutdown sleep mode. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0020] Figure 1 The circuit diagram of the notebook battery charge and discharge control circuit of an embodiment;

[0021] Figure 2 For Figure 1The diagram shows a partial circuit diagram of the laptop battery charging and discharging control circuit. Detailed Implementation

[0022] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure.

[0023] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0025] To better understand the technical solutions and beneficial effects of this disclosure, the following detailed description is provided in conjunction with specific embodiments:

[0026] like Figures 1 to 2 As shown, a notebook battery charging and discharging control circuit 10 according to an embodiment of this disclosure includes a main control module 100, a battery management chip U2, a first electronic switch Q1, a second electronic switch Q2, a first pull-down resistor R4, a linear regulator U4, and a negative voltage chip U3. The first terminal of the first electronic switch Q1 is connected to the power supply terminal of the battery cell, the control terminal of the first electronic switch Q1 is connected to the charging signal terminal CHG of the battery management chip U2, the second terminal of the first electronic switch Q1 is connected to the power signal terminal VCC of the battery management chip U2, the first terminal of the second electronic switch Q2 is connected to the power signal terminal VCC of the battery management chip U2, the control terminal of the second electronic switch Q2 is connected to the discharging signal terminal DSG of the battery management chip U2, the second terminal of the second electronic switch Q2 is connected to the main control module 100, the first terminal of the first pull-down resistor R4 is connected to the control terminal of the second electronic switch Q2, the second terminal of the first pull-down resistor R4 is connected to the second terminal of the second electronic switch Q2, and the power supply terminal of the battery management chip U2 is connected to the power supply terminal of the battery cell.

[0027] The power supply end of the linear voltage regulator U4 is connected with the first end of the first electronic switch tube Q1, the power supply enable end EN1 of the linear voltage regulator U4 is connected with the second end of the second electronic switch tube Q2, the output end of the linear voltage regulator U4 is connected with the power supply input end of the negative voltage chip U3, the output end of the negative voltage chip U3 is connected with the control end of the second electronic switch tube Q2, the enable control end EN2 of the negative voltage chip U3 is connected with the negative voltage signal end EN3 of the main control module 100, and the sleep signal end PRES of the main control module 100 is connected with the sleep control end PRES of the battery management chip U2.

[0028] In the embodiment, in the normal working mode, the sleep signal end PRES of the main control module 100 outputs a high level signal to the sleep control end PRES of the battery management chip U2, so that the battery management chip U2 is in the normal working state, at the same time, the negative voltage signal end EN3 of the main control module 100 outputs a low level signal to the enable control end EN2 of the negative voltage chip U3, so that the negative voltage chip U3 is in the off state, and the charging signal end CHG of the battery management chip U2 outputs a high level signal to the control end of the first electronic switch tube Q1, and the discharging signal end DSG of the battery management chip U2 outputs a high level signal to the control end of the second electronic switch tube Q2, so that the control end voltage of the first electronic switch tube Q1 and the second electronic switch tube Q2 is greater than the conduction threshold voltage, the first electronic switch tube Q1 and the second electronic switch tube Q2 are turned on, so that the notebook battery charging and discharging control circuit 10 can normally complete the charging and discharging work.

[0029] Further, when the notebook battery charging and discharging control circuit 10 needs to enter the sleep mode, the sleep signal end PRES of the main control module 100 outputs a low level signal to the sleep control end PRES of the battery management chip U2, so that the battery management chip U2 starts to enter the sleep mode, and outputs a low level signal to the control end of the first electronic switch tube Q1 through the charging signal end CHG of the battery management chip U2, and outputs a low level signal to the control end of the second electronic switch tube Q2 through the discharging signal end DSG of the battery management chip U2, so that the control end voltage of the first electronic switch tube Q1 and the second electronic switch tube Q2 is lower than the conduction threshold voltage, the first electronic switch tube Q1 and the second electronic switch tube Q2 are in the off state, so that the notebook battery charging and discharging control circuit 10 is in the shutdown sleep mode and stops the charging and discharging work.

[0030] Further, since the SGT process characteristics of the MOS tube are easy to cause the SGT-MOS tube to accumulate charges between the sources and form a voltage difference, thereby causing the MOS tube to be mis-conducted and a false voltage to be generated in the circuit; if the notebook battery charge and discharge control circuit 10 exists a false voltage in the shutdown sleep mode, the false voltage will enable the supply enable end EN1 of the linear voltage regulator U4 to obtain an enabling conduction signal, specifically, the linear voltage regulator U4 is a high voltage signal, so that the linear voltage regulator U4 works normally to output a stable voltage to the power input end of the negative voltage chip U3, at the same time, the negative voltage signal end EN3 of the main control module 100 outputs a high level signal to the enable control end EN2 of the negative voltage chip U3, thereby making the negative voltage chip U3 start to work and output a negative voltage to the control end of the second electronic switch tube Q2. At this time, since the control end of the second electronic switch tube Q2 is affected by the negative voltage field, the electric field distribution in the channel of the second electronic switch tube Q2 is changed, so that the electrons cannot pass through the channel, thereby realizing the complete shutdown of the second electronic switch tube Q2, and thereby avoiding the problem that the notebook battery charge and discharge control circuit 10 continues to discharge in the shutdown sleep mode.

[0031] The notebook battery charge and discharge control circuit 10 described above increases the linear voltage regulator U4 and the negative voltage chip U3 under the original technical framework, when the notebook battery charge and discharge control circuit 10 enters the shutdown sleep mode and exists a false voltage, the linear voltage regulator U4 detects and obtains the false voltage, thereby driving the negative voltage chip U3 to enter the working state and output a negative voltage to the control end of the second electronic switch tube Q2, so that the conduction channel cannot be formed in the second electronic switch tube Q2, thereby avoiding the problem of leakage in the notebook battery charge and discharge control circuit 10 in the shutdown sleep mode.

[0032] As shown in Figures 1 to 2 In one embodiment, the notebook battery charge and discharge control circuit 10 further includes a first voltage dividing resistor R30, the first end of the first voltage dividing resistor R30 is connected with the first end of the first electronic switch tube Q1, and the second end of the first voltage dividing resistor R30 is connected with the power supply end of the linear voltage regulator U4. In this embodiment, after the notebook battery charge and discharge control circuit 10 enters the sleep mode, although the first electronic switch tube Q1 and the second electronic switch tube Q2 should be in the off state, but due to the false voltage problem of the MOS tube caused by the SGT process characteristics of the MOS tube, the battery power supply end may still provide a weak voltage to the linear voltage regulator U4 through the first voltage dividing resistor R30; at this time, the first voltage dividing resistor R30 plays a role of sharing the voltage of the battery power supply end for the internal circuit of the linear voltage regulator U4, thereby ensuring that the voltage received by the linear voltage regulator U4 is within its working range, and thereby protecting the linear voltage regulator U4 from being damaged by excessive voltage.

[0033] AsFigures 1 to 2 As shown in the figure, in one embodiment, the notebook battery charge and discharge control circuit 10 further comprises a first filter capacitor C29, a first end of the first filter capacitor C29 is connected to the power supply end of the linear voltage regulator U4, and a second end of the first filter capacitor C29 is grounded. In this embodiment, when the notebook battery charge and discharge control circuit 10 is in sleep mode, there is a virtual voltage due to the SGT process characteristics of the MOS tube. At this time, since the first filter capacitor C29 can provide a low impedance path for rapidly changing voltages (i.e. high-frequency noise or fluctuations), the high-frequency noise or fluctuations flow into the ground end through the first filter capacitor C29, thereby effectively filtering out high-frequency noise or fluctuations and smoothing the voltage fluctuations in the circuit, so that the voltage received by the linear voltage regulator U4 is more stable, thereby improving the anti-interference ability and stability of the linear voltage regulator U4.

[0034] As shown in the figure, Figures 1 to 2 As shown in the figure, in one embodiment, the notebook battery charge and discharge control circuit 10 further comprises a second voltage dividing resistor R12, a first end of the second voltage dividing resistor R12 is connected to the charge signal end CHG of the battery management chip U2, and a second end of the second voltage dividing resistor R12 is connected to the control end of the first electronic switch tube Q1. In this embodiment, when the battery management chip U2 controls the first electronic switch tube Q1 to conduct for charging, it will output a high-level signal through the charge signal end, and then pass through the second voltage dividing resistor R12, and then be transmitted to the control end of the first electronic switch tube Q1. At this time, the second voltage dividing resistor R12 plays a role of voltage division to ensure that the voltage transmitted to the control end of the first electronic switch tube Q1 is sufficient to trigger its conduction, while avoiding damaging the first electronic switch tube Q1 by too high voltage, thereby enabling the battery management chip U2 to more stably control the conduction and cutoff of the first electronic switch tube Q1.

[0035] As shown in the figure, Figures 1 to 2As shown in the figure, in one embodiment, the notebook battery charge and discharge control circuit 10 further comprises a current-limiting resistor R9, a first end of the current-limiting resistor R9 is connected with the power signal end VCC of the battery management chip U2, and a second end of the current-limiting resistor R9 is respectively connected with the second end of the first electronic switch tube Q1 and the first end of the second electronic switch tube Q2. In this embodiment, when the battery management chip U2 outputs current through the power signal end to the second end of the first electronic switch tube Q1 and the first end of the second electronic switch tube Q2, the current first passes through the current-limiting resistor R9 and then is transmitted to the second end of the first electronic switch tube Q1 and the first end of the second electronic switch tube Q2, so that the current-limiting resistor R9 can effectively control the current size passing through the second end of the first electronic switch tube Q1 and the first end of the second electronic switch tube Q2, thereby enabling the circuit to smoothly transition during startup or transient process and avoiding damage to the first electronic switch tube Q1 or the second electronic switch tube Q2 caused by excessive current impact. At the same time, the current-limiting resistor R9 can also play a certain voltage stabilizing role, so that the power supply voltage output by the battery management chip U2 can be more stably transmitted to the second end of the first electronic switch tube Q1 and the first end of the second electronic switch tube Q2 after passing through the current-limiting resistor R9, thereby improving the stability and reliability of the notebook battery charge and discharge control circuit 10.

[0036] As shown in the figure, Figures 1 to 2 In one embodiment, the notebook battery charge and discharge control circuit 10 further comprises a second pull-down resistor R5, a first end of the second pull-down resistor R5 is connected with the control end of the first electronic switch tube Q1, and a second end of the second pull-down resistor R5 is connected with the second end of the first electronic switch tube Q1. In this embodiment, when the voltage at the control end of the first electronic switch tube Q1 rises due to virtual voltage, the negative voltage chip U3 will output a voltage in the opposite direction to the control end of the first electronic switch tube Q1, and form a current path through the second pull-down resistor R5 to conduct excess charge, thereby suppressing the rise of the control end voltage. Thus, the problem of accidental conduction of the first electronic switch tube Q1 in the sleep mode is effectively avoided, thereby improving the stability of the notebook battery charge and discharge control circuit 10.

[0037] As shown in the figure, Figures 1 to 2As shown, in one embodiment, the notebook battery charging and discharging control circuit 10 further includes a Zener diode D2. The anode of the Zener diode D2 is connected to the control terminal of the second electronic switch Q2, and the cathode of the Zener diode D2 is connected to the output terminal of the negative voltage chip U3. In this embodiment, when the control terminal of the second electronic switch Q2 rises due to a false voltage in the circuit, the negative voltage chip U3 outputs a negative voltage to the Zener diode D2, causing it to quickly conduct. Then, the negative voltage is applied to the control terminal of the second electronic switch Q2. Because the Zener diode D2 has a stable breakdown voltage, when the voltage across it exceeds the breakdown voltage, the Zener diode D2 will limit the further rise of the voltage, thereby enabling the Zener diode D2 and the negative voltage chip U3 to work together, thus ensuring the voltage stability of the control terminal of the second electronic switch Q2.

[0038] like Figures 1 to 2 As shown, in one embodiment, the laptop battery charging and discharging control circuit 10 further includes a current-conducting diode D3. The positive terminal of the current-conducting diode D3 is connected to the second terminal of the second electronic switch Q2, and the negative terminal of the current-conducting diode D3 is connected to the power supply enable terminal EN1 of the linear regulator U4. In this embodiment, when the laptop battery charging and discharging control circuit 10 enters sleep mode, if a virtual voltage occurs in the circuit due to the SGT process characteristics of the MOSFET, this virtual voltage will be transmitted to the power supply enable terminal EN1 of the linear regulator U4 through the current-conducting diode D3. After detecting the virtual voltage, the linear regulator U4 starts working and outputs a voltage to start the negative voltage chip U3, thereby ensuring that the virtual voltage can be effectively guided by the current-conducting diode D3, thus improving the stability of the laptop battery charging and discharging control circuit 10.

[0039] like Figures 1 to 2As shown, in one embodiment, the first electronic switch tube and the second electronic switch tube are both SGT-NMOS tubes. In this embodiment, the first end of the first electronic switch tube Q1 is the source of the SGT-NMOS tube, the second end of the first electronic switch tube Q1 is the drain of the SGT-NMOS tube, the control end of the first electronic switch tube Q1 is the gate of the SGT-NMOS tube, the first end of the second electronic switch tube Q2 is the drain of the SGT-NMOS tube, the second end of the second electronic switch tube Q2 is the source of the SGT-NMOS tube, and the control end of the second electronic switch tube Q2 is the gate of the SGT-NMOS tube. When the charging signal end CHG of the battery management chip U2 outputs a high level signal to the control end of the first electronic switch tube Q1 and the discharging signal end DSG of the battery management chip U2 outputs a high level signal to the control end of the second electronic switch tube Q2, the first electronic switch tube Q1 and the second electronic switch tube Q2 are turned on because the voltage of the control end is greater than the turn-on threshold voltage, so that the notebook battery charging and discharging control circuit 10 can normally complete the charging and discharging work. At the same time, since the SGT process has a deep trench structure and can balance the drift region charge under reverse voltage, the resistivity of the drift region is effectively reduced, and the specific on-resistance of the first electronic switch tube Q1 and the second electronic switch tube Q2 is reduced, thereby being beneficial to reducing the energy loss of the first electronic switch tube Q1 and the second electronic switch tube Q2.

[0040] The battery management system comprises the notebook battery charge-discharge control circuit. In the embodiment, in the normal working mode, the sleep signal end PRES of the master control module 100 outputs a high level signal to the sleep control end PRES of the battery management chip U2, so that the battery management chip U2 is in the normal working state, meanwhile, the negative voltage signal end EN3 of the master control module 100 outputs a low level signal to the enable control end EN2 of the negative voltage chip U3, so that the negative voltage chip U3 is in the off state, and the charge signal end CHG of the battery management chip U2 outputs a high level signal to the control end of the first electronic switch tube Q1, and the discharge signal end DSG of the battery management chip U2 outputs a high level signal to the control end of the second electronic switch tube Q2, so that the control end voltage of the first electronic switch tube Q1 and the second electronic switch tube Q2 is greater than the conduction threshold voltage, the first electronic switch tube Q1 and the second electronic switch tube Q2 are turned on, so that the notebook battery charge-discharge control circuit 10 can normally complete the charge-discharge work. Further, when the notebook battery charge-discharge control circuit 10 needs to enter the sleep mode, the sleep signal end PRES of the master control module 100 outputs a low level signal to the sleep control end PRES of the battery management chip U2, so that the battery management chip U2 starts to enter the sleep mode, and the charge signal end CHG of the battery management chip U2 outputs a low level signal to the control end of the first electronic switch tube Q1, and the discharge signal end DSG of the battery management chip U2 outputs a low level signal to the control end of the second electronic switch tube Q2, so that the control end voltage of the first electronic switch tube Q1 and the second electronic switch tube Q2 is lower than the conduction threshold voltage, the first electronic switch tube Q1 and the second electronic switch tube Q2 are in the off state, so that the notebook battery charge-discharge control circuit 10 is in the sleep mode and stops the charge-discharge work. Further, due to the SGT process characteristics of the MOS tube, there is a voltage difference between the source and the gate of the MOS tube, which may cause the MOS tube to be mis-conducted and generate a virtual voltage in the circuit; if there is a virtual voltage in the notebook battery charge-discharge control circuit 10 in the shutdown sleep mode, the virtual voltage will enable the supply enable end EN1 of the linear voltage stabilizer U4 to obtain an enable conduction signal, specifically, the linear voltage stabilizer U4 is a high voltage signal, so that the linear voltage stabilizer U4 normally works to output a stable voltage to the power input end of the negative voltage chip U3, meanwhile, the negative voltage signal end EN3 of the master control module 100 outputs a high level signal to the enable control end EN2 of the negative voltage chip U3, so that the negative voltage chip U3 starts to work and outputs a negative voltage to the control end of the second electronic switch tube Q2.At this time, since the control end of the second electronic switch tube Q2 is affected by the negative voltage electric field, the electric field distribution in the channel of the second electronic switch tube Q2 is changed, so that the electrons cannot pass through the channel, thereby realizing the complete turn-off of the second electronic switch tube Q2, and further avoiding the problem that the notebook battery charging and discharging control circuit 10 continues to discharge in the shutdown sleep mode.

[0041] Compared with the prior art, the present disclosure has at least the following advantages:

[0042] 1. The notebook battery charging and discharging control circuit 10 described above, under the original technical framework, increases the linear voltage regulator U4 and the negative voltage chip U3. When the notebook battery charging and discharging control circuit 10 enters the shutdown sleep mode and there is a virtual voltage, the linear voltage regulator U4 detects and obtains the virtual voltage, thereby driving the negative voltage chip U3 to enter the working state and outputting a negative voltage to the control end of the second electronic switch tube Q2, so that the second electronic switch tube Q2 cannot form a conductive channel, thereby avoiding the problem of leakage of the notebook battery charging and discharging control circuit 10 in the shutdown sleep mode.

[0043] The above-described embodiments only express several embodiments of the present disclosure, and the description is more specific and detailed, but it cannot be understood as a limitation on the scope of the disclosed patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present disclosure, a number of modifications and improvements can be made, which are all within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent should be subject to the appended claims.

Claims

1. A notebook battery charging and discharging control circuit, characterized in that, The notebook battery charging and discharging control circuit comprises a main control module, a battery management chip, a first electronic switch tube, a second electronic switch tube, a first pull-down resistor, a linear voltage regulator and a negative voltage chip, a first end of the first electronic switch tube is used for being connected with a power supply end of a battery cell, a control end of the first electronic switch tube is connected with a charging signal end of the battery management chip, a second end of the first electronic switch tube is connected with a power signal end of the battery management chip, a first end of the second electronic switch tube is connected with the power signal end of the battery management chip, a control end of the second electronic switch tube is connected with a discharging signal end of the battery management chip, a second end of the second electronic switch tube is used for being connected with the main control module, a first end of the first pull-down resistor is connected with the control end of the second electronic switch tube, a second end of the first pull-down resistor is connected with the second end of the second electronic switch tube, and a power supply end of the battery management chip is used for being connected with the power supply end of the battery cell. A power supply end of the linear voltage regulator is connected with the first end of the first electronic switch tube, a power supply enable end of the linear voltage regulator is connected with the second end of the second electronic switch tube, an output end of the linear voltage regulator is connected with a power input end of the negative voltage chip, an output end of the negative voltage chip is connected with the control end of the second electronic switch tube, an enable control end of the negative voltage chip is connected with a negative voltage signal end of the main control module, and a sleep signal end of the main control module is connected with a sleep control end of the battery management chip.

2. The notebook battery charge and discharge control circuit according to claim 1, wherein The notebook battery charging and discharging control circuit further comprises a first voltage dividing resistor, a first end of the first voltage dividing resistor is connected with the first end of the first electronic switch tube, and a second end of the first voltage dividing resistor is connected with the power supply end of the linear voltage regulator.

3. The notebook battery charge and discharge control circuit according to claim 2, wherein The notebook battery charging and discharging control circuit further comprises a first filter capacitor, a first end of the first filter capacitor is connected with the power supply end of the linear voltage regulator, and a second end of the first filter capacitor is grounded.

4. The notebook battery charge and discharge control circuit according to claim 1, wherein, The notebook battery charging and discharging control circuit further comprises a second voltage dividing resistor, a first end of the second voltage dividing resistor is connected with the charging signal end of the battery management chip, and a second end of the second voltage dividing resistor is connected with the control end of the first electronic switch tube.

5. The notebook battery charge and discharge control circuit according to claim 1, wherein, The notebook battery charging and discharging control circuit further comprises a current limiting resistor, a first end of the current limiting resistor is connected with the power signal end of the battery management chip, and a second end of the current limiting resistor is connected with the second end of the first electronic switch tube and the first end of the second electronic switch tube respectively.

6. The notebook battery charge and discharge control circuit according to claim 1, wherein, The notebook battery charging and discharging control circuit further comprises a second pull-down resistor, a first end of the second pull-down resistor is connected with the control end of the first electronic switch tube, and a second end of the second pull-down resistor is connected with the second end of the first electronic switch tube.

7. The notebook battery charge and discharge control circuit according to claim 6, wherein The notebook battery charging and discharging control circuit further comprises a voltage stabilizing diode, a positive electrode of the voltage stabilizing diode is connected with the control end of the second electronic switch tube, and a negative electrode of the voltage stabilizing diode is connected with the output end of the negative voltage chip.

8. The notebook battery charge and discharge control circuit according to claim 1, wherein, The notebook battery charging and discharging control circuit further comprises a current guide diode, a positive electrode of the current guide diode is connected with a second end of the second electronic switch tube, and a negative electrode of the current guide diode is connected with a power supply enable end of the linear voltage stabilizer.

9. The notebook battery charge and discharge control circuit according to claim 1, wherein, The first electronic switch tube and the second electronic switch tube are SGT-NMOS tubes.

10. A battery management system, characterized by, The notebook battery charging and discharging control circuit comprises the notebook battery charging and discharging control circuit according to any one of claims 1 to 9.

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