Semiconductor device with field plate

Abstract

The utility model provides a semiconductor device with a field plate, which comprises a substrate, an epitaxial layer, a first dielectric layer, a second dielectric layer, a first metal layer, a third dielectric layer and a second metal layer, and is characterized in that the second dielectric layer is provided with a source metal hole and a drain metal hole which penetrate through the first dielectric layer and the second dielectric layer; forming a source electrode on the source electrode metal hole, forming a drain electrode on the drain electrode metal hole, and forming a first field plate on the second dielectric layer; a gate metal hole penetrating through the third dielectric layer and the second dielectric layer is formed in the third dielectric layer, so that a gate is formed in the gate metal hole.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of semiconductor device, especially a semiconductor device with field plate. BACKGROUND

[0002] Gallium nitride high electron mobility transistor (GaN HEMT) as the representative of wide band gap (WBG) power semiconductor device, it has huge potential in high frequency power application. In the design of lateral GaN HEMT switching device, the withstand voltage capability of switching device is a very important performance parameter, when switching device is off, the main withstand voltage structure of lateral GaN HEMT switching device is the depletion region between gate (G) and drain (D), under the same depletion region size, the electric field distribution determines the size of withstand voltage, and there is electric field concentration effect in the gate corner near the drain side, resulting in an electric field peak existing here, when the electric field peak reaches a certain critical value, electric field breakdown occurs, and then the device reliability is affected, and even irreversible damage occurs.

[0003] In order to improve the withstand voltage capability of semiconductor device, field plate structure is generally used, the main function of field plate is to adjust the electric field distribution of drift region, weaken the electric field peak existing near the gate, and improve the withstand voltage of semiconductor device. The introduction of field plate can reduce the original electric field peak, but a new electric field peak exists at the end of field plate. For high-voltage semiconductor devices, a single field plate often cannot achieve ideal electric field distribution. Generally, high-voltage semiconductor devices have multi-stage field plate structure for modulating electric field distribution. Using this method, each layer of field plate from the gate to the drain direction will further modulate the electric field peak generated by the previous field plate, and by adjusting the length and height of each stage of field plate, an optimized electric field distribution is obtained, and higher withstand voltage and reliability are achieved.

[0004] In order to realize multi-layer field plate in semiconductor device, multiple etching of dielectric and metal and multiple photolithography steps are often required in existing structures, and with more layers of field plate, the process cost and time cost will also increase significantly. For example, in the current mainstream 650V gallium nitride HEMT chip, generally 3-4 layers of field plate are required, so the production of gate and field plate metal needs 4-5 times of photolithography, which accounts for 20%-30% of the process cost and time cost of the whole chip flow process. UTILITY MODEL CONTENTS

[0005] The utility model embodiment provides a semiconductor device with field plate, which simplifies the implementation cost and time of setting field plate in semiconductor device.

[0006] The utility model embodiment provides a semiconductor device with field plate, comprising:

[0007] Substrate;

[0008] Epitaxial layer, be provided on the substrate;

[0009] First dielectric layer and second dielectric layer, be provided on the epitaxial layer, the second dielectric layer is provided with the source metal hole, drain metal hole through the first dielectric layer and the second dielectric layer;

[0010] First metal layer, be provided on the second dielectric layer, to form source on the source metal hole, form drain on the drain metal hole and form first layer field plate on the second dielectric layer;

[0011] Third dielectric layer, be provided on the first metal layer, the third dielectric layer is provided with the gate metal hole through the third dielectric layer and the second dielectric layer;And

[0012] Second metal layer, be provided on the third dielectric layer, to form gate on the gate metal hole.

[0013] The utility model embodiment provides a semiconductor device with field plate, comprising:

[0014] Substrate;

[0015] Epitaxial layer, be provided on the substrate;

[0016] First dielectric layer and second dielectric layer, be provided on the epitaxial layer, the second dielectric layer is provided with the source metal hole, drain metal hole through the first dielectric layer and the second dielectric layer;

[0017] First metal layer, be provided on the second dielectric layer, to form source on the source metal hole, form drain on the drain metal hole and form first layer field plate on the second dielectric layer;

[0018] Third dielectric layer, be provided on the first metal layer;

[0019] Second metal layer, be provided on the third dielectric layer, to form second layer field plate on the third dielectric layer, the second layer field plate is above the first layer field plate, and the projection of second layer field plate and first layer field plate in the substrate direction has the overlapping region;

[0020] Fourth dielectric layer, be provided on the second metal layer, the fourth dielectric layer is provided with the gate metal hole through the fourth dielectric layer, the third dielectric layer and the second dielectric layer;And

[0021] A third metal layer is disposed on the fourth dielectric layer to form a gate on the gate metal hole.

[0022] It can be seen that in the process of manufacturing the semiconductor device with the field plate, the first layer field plate and the source and drain are formed in the same step, so that the source and drain and the first layer field plate are formed on the same layer, which can simplify the manufacturing process of the semiconductor device, thereby reducing the cost and time of implementing the field plate in the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0024] Figure 1 is a flow chart of a manufacturing method of a semiconductor device with a field plate provided by the embodiment of the present application;

[0025] Figure 2a is a sectional view of a semiconductor device with a three-layer field plate in the embodiment of the present application;

[0026] Figure 2b is a sectional view of a semiconductor device in the process of metal deposition and metal etching in the embodiment of the present application;

[0027] Figure 2c is a schematic view of a source, a drain and a first layer field plate formed after the process of metal deposition and metal etching in the embodiment of the present application;

[0028] Figure 3 is a sectional view of another semiconductor device with a three-layer field plate in the embodiment of the present application;

[0029] Figure 4 is a sectional view of a semiconductor device with a four-layer field plate in the embodiment of the present application;

[0030] Figure 5 is a flow chart of another manufacturing method of a semiconductor device with a field plate provided by the embodiment of the present application;

[0031] Figure 6 is a sectional view of a semiconductor device with a three-layer field plate in the embodiment of the present application;

[0032] Figure 7 is a sectional view of another semiconductor device with a three-layer field plate in the embodiment of the present application;

[0033] Figure 8 is a sectional view of a semiconductor device including four field plates in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0035] The terms "first", "second", "third", "fourth" and the like in the description and claims of the present application and in the above drawings (if any) are used to distinguish similar objects, and do not necessarily have to be used to describe a particular order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented, for example, in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0036] An embodiment of the present application provides a semiconductor device with a field plate, which includes but is not limited to, for example, MIS-HEMT devices, P-GaN HEMT devices, SBD-Gate HEMT, etc. These semiconductor devices can be various semiconductor materials, such as gallium nitride (GaN), silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium oxide (GaO), etc.

[0037] The semiconductor device of the present embodiment includes a substrate 10, an epitaxial layer 11, and a first dielectric layer 12, a second dielectric layer 13, a first metal layer 130, a third dielectric layer 14 and a second metal layer arranged in sequence on the epitaxial layer 11.

[0038] The first dielectric layer 12 and the second dielectric layer 13 are arranged on the epitaxial layer 11, the second dielectric layer 13 is provided with a source metal hole and a drain metal hole penetrating through the first dielectric layer 12 and the second dielectric layer 13; the first metal layer 130 is arranged on the second dielectric layer 13 to form a source 110 on the source metal hole, a drain 112 on the drain metal hole, and a first layer field plate 1131 on the second dielectric layer 13; the third dielectric layer 14 is arranged on the first metal layer, the third dielectric layer 14 is provided with a gate metal hole penetrating through the third dielectric layer 14 and the second dielectric layer 13; the second metal layer is arranged on the third dielectric layer 14 to form a gate 111 on the gate metal hole.

[0039] Specifically, as shown in the drawings, the manufacturing method of the semiconductor device of the embodiment includes: Figure 1

[0040] In step 101, a first dielectric layer and a second dielectric layer are deposited on an epitaxial layer of a substrate, and dielectric etching is performed on the second dielectric layer and the first dielectric layer to form a source-drain dielectric.

[0041] Generally, in the manufacturing process of a semiconductor device, various parts included in the semiconductor device, such as a source, a gate, a drain, and a field plate, are arranged on an epitaxial layer of a substrate, and then the semiconductor device is obtained. The epitaxial layer is a new semiconductor layer grown on the substrate, which can improve the performance of the device, increase the conductivity, or enhance the control of impurities; the source, the gate, the drain, and the field plate are all metal parts, and the field plate can optimize the electric field between the electrodes, making the electric field distribution uniform and improving the reliability of the semiconductor device.

[0042] In the embodiment, a plurality of processes are required on the epitaxial layer of the substrate to form the final semiconductor device. First, a first dielectric layer and a second dielectric layer are deposited on the epitaxial layer of the substrate, which mainly serves as insulation and isolation. Further, when the semiconductor device includes a source and a drain, dielectric etching is performed on the second dielectric layer and the first dielectric layer to form a source-drain dielectric, so that the source and the drain are formed on the same layer.

[0043] The dielectric etching is a process of selectively removing unwanted materials from the surface of the wafer (in this embodiment, from the first dielectric layer and the second dielectric layer), which can be achieved by various methods, including physical means (such as ion milling etching) and chemical means (such as plasma etching). In the dielectric etching process, a mask is used to protect the materials that need to be retained, and the exposed materials are removed. ​

[0044] In the embodiment, the source and the gate in the semiconductor device are arranged in different layers, i.e., the source and the gate have different depths, so that the short circuit between the source and the gate can be effectively prevented. In order to facilitate the layering of the source and the gate, the first dielectric layer and the second dielectric layer need to be arranged on the epitaxial layer. When the dielectric etching is performed on the second dielectric layer and the first dielectric layer to form the source-drain dielectric, the second dielectric layer and the first dielectric layer need to be etched through, so as to expose the epitaxial layer of the source region and the drain region. When the dielectric etching is performed to form the gate dielectric, the first dielectric layer does not need to be etched through, and only the second dielectric layer needs to be etched through, so as to expose the first dielectric layer of the gate region.

[0045] The manufacturing processes of the two adjacent dielectric layers can be different, such as the first dielectric layer and the second dielectric layer, and the dielectric layer of the lower layer is denser, so that the dielectric etching speed is slower. When the etching reaches the boundary between the two adjacent dielectric layers, the etching speed will slow down, and the etching depth can be well controlled.

[0046] As shown in FIG. 1, Figure 2a FIG. 1 is a sectional view of a semiconductor device. The epitaxial layer 11 of the substrate 10 is provided with a source 110, a gate 111, a drain 112, and a plurality of layers (three layers of field plates are taken as an example in the figure) of field plates near the gate 111. The first layer of field plates 1131 in the plurality of layers of field plates is in the same layer as the source 110 and the drain 112, and the second layer of field plates 1132 is connected with the gate 111. In the embodiment, the first dielectric layer 12 is deposited on the epitaxial layer 11 of the substrate 10, and then the second dielectric layer 13 is deposited. Then, the dielectric etching is performed on the second dielectric layer 13 and the first dielectric layer 12 to form the source-drain dielectric. Specifically, the through hole is formed by passing through the second dielectric layer 13 and the first dielectric layer 12, and the epitaxial layer 11 of the source region and the drain region is exposed.

[0047] In step 102, the metal deposition and the metal etching are performed on the source-drain dielectric to form the source, the drain, and the first layer of field plates of the semiconductor device, and the gate position is reserved between the source and the first layer of field plates.

[0048] Specifically, for example Figure 2bAs shown, during metal deposition, a first metal layer 130 can be deposited on the source and drain dielectric. Then, metal etching is performed on the first metal layer 130 to form a source 110 (e.g., an ohmic metal for the source), a drain 112 (e.g., an ohmic metal for the drain), and a first field plate 1131. A gate position is reserved between the source 110 and the first field plate 1131, and the positions of other multilayer field plates (e.g., a second field plate 1132 and a third field plate 1133) are reserved between the drain 112 and the first field plate 1131. In this way, the formation of the source 110, drain 112, and first field plate 1131 is concentrated in the same step, simplifying the steps of setting each part on the epitaxial layer 11. Finally, the source 110, drain 112, and first field plate 1131 are formed on the same layer.

[0049] In this process, during metal etching, photoresist 131 can be placed at the locations where metal needs to be retained. Then, the first metal layer 130 is etched. This way, the metal at the locations with photoresist 131 is retained, while the metal at other locations is etched away. Finally, the photoresist 131 is removed, resulting in a metal layer as shown in the diagram. Figure 2c The image shows a source 110, a drain 112, and a first field plate 1131. The distance between the source 110 and the first field plate 1131 needs to be sufficient to accommodate the gate 111 formed later, and the distance between the first field plate 1131 and the drain 112 also needs to be sufficient to accommodate the other field plates formed later.

[0050] Step 103: Deposit the third dielectric layer, and perform dielectric etching on the third dielectric layer and the second dielectric layer at the gate location to form the gate dielectric. The gate location is the position between the source and the first field plate.

[0051] like Figure 2a As shown, after the source 110, drain 112, and first field plate 1131 are formed, a third dielectric layer 14 can be deposited. Then, at the gate position between the source 110 and the first field plate 1131, only the third dielectric layer 14 and the second dielectric layer 13 are etched to form the gate dielectric. Specifically, when forming the gate dielectric, it is necessary to etch through the third dielectric layer 14 and the second dielectric layer 13, and expose the first dielectric layer 12.

[0052] In this way, by depositing the second dielectric layer 13 on the first dielectric layer 12, the distances from the final gate 111 and source 110 to the substrate 10 can be different, that is, there is a certain depth difference between the depths of the gate 111 and the source 110. Since the source 110 and the first field plate 1131 are in the same layer, there is a certain depth difference between the depths of the gate 111 and the first field plate 1131.

[0053] Step 104, metal deposition (deposition of the second metal layer) and metal etching are performed on the gate dielectric to form the gate of the semiconductor device, i.e. the gate 111 is formed on the first dielectric layer 12 in the gate region.

[0054] It should be noted that the above steps 101 to 104 are mainly methods for providing a field plate in a semiconductor device. In other embodiments, multiple field plates can also be provided in the semiconductor device, such as a second field plate, a third field plate, and a fourth field plate, etc. Specifically:

[0055] (1) when forming the second field plate:

[0056] Metal deposition and metal etching are performed on the gate dielectric to also form the second field plate, the second field plate is above the first field plate, and the projection of the second field plate and the first field plate in the substrate direction has an overlapping region, wherein the gate is connected with the second field plate, or the gate is disconnected from the second field plate.

[0057] For example Figure 2a As shown in FIG. 11B, metal deposition and metal etching can be performed on the gate dielectric to simultaneously form the gate 111 and the second field plate 1132, and the gate 111 is connected with the second field plate 1132. In other embodiments, as shown in FIG. 11C, the gate 111 can be disconnected from the second field plate 1132, so that the second field plate 1132 can be connected with the source 110 or the gate 111 through subsequent metal interconnection processes. The projection of the second field plate 1132 and the first field plate 1131 in the substrate 10 direction has an overlapping region. Figure 3

[0058] (2) when forming the third field plate:

[0059] The fourth dielectric layer is deposited, and metal deposition (deposition of the third metal layer) and metal etching are performed on the fourth dielectric layer to form the third field plate, the third field plate is above the second field plate, and the projection of the third field plate and the second field plate in the substrate direction has an overlapping region.

[0060] For example Figure 2a As shown in FIG. 11B, after the gate 111 and the second field plate 1132 are formed, the fourth dielectric layer 15 can be deposited, and metal deposition and metal etching are performed on the fourth dielectric layer 15 to form the third field plate 1133, and the projection of the third field plate 1133 and the second field plate 1132 in the substrate 10 direction has an overlapping region.

[0061] (3) when forming the fourth field plate:

[0062] ​A fifth dielectric layer is deposited, and metal deposition (deposition of a fourth metal layer) and metal etching are performed on the fifth dielectric layer to form a fourth layer field plate, the fourth layer field plate being above the third layer field plate, and the fourth layer field plate and the third layer field plate having an overlapping area in the projection on the substrate direction.

[0063] For example Figure 4 As shown in the figure, after the third layer field plate 1133 is formed, a fifth dielectric layer 16 can be deposited, and metal deposition and metal etching are performed on the fifth dielectric layer 16 to form a fourth layer field plate 1134, and the fourth layer field plate 1134 and the third layer field plate 1133 have an overlapping area in the projection on the substrate 10 direction.

[0064] It can be seen that, in the process of manufacturing the semiconductor device, the formation of the first layer field plate and the source in the semiconductor device is concentrated in the same step in the embodiment of the utility model, so that the source and the first layer field plate are formed on the same layer, which can simplify the manufacturing steps of the semiconductor device, thereby simplifying the implementation cost and time of setting the field plate in the semiconductor device.

[0065] An embodiment of the utility model provides another semiconductor device with a field plate, which includes but is not limited to MIS-HEMT device, P-GaN HEMT device, SBD-Gate HEMT and the like, and these semiconductor devices can be various semiconductor materials, such as gallium nitride (GaN), silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium oxide (GaO) and the like.

[0066] The semiconductor device of the embodiment includes a substrate 20, an epitaxial layer 21, and a first dielectric layer 22, a second dielectric layer 23, a first metal layer, a third dielectric layer 24, a second metal layer, a fourth dielectric layer 25 and a third metal layer arranged in sequence on the epitaxial layer 21.

[0067] A first dielectric layer 22 and a second dielectric layer 23 are disposed on the epitaxial layer 21. A source metal via and a drain metal via penetrating the first dielectric layer 22 and the second dielectric layer 23 are disposed on the second dielectric layer 23. A first metal layer is disposed on the second dielectric layer 22 to form a source electrode 210 on the source metal via, a drain electrode 212 on the drain metal via, and a first field plate 2131 on the second dielectric layer 23. A third dielectric layer 24 is disposed on the first metal layer. A second metal layer is disposed on the third dielectric layer 24. A second field plate 2132 is formed on the third dielectric layer 24, the second field plate 2132 is above the first field plate 2131, and the projections of the second field plate 2132 and the first field plate 2131 in the substrate direction have an overlapping area; a fourth dielectric layer 25 is disposed on the second metal layer, and a gate metal hole is disposed on the fourth dielectric layer 25, penetrating the fourth dielectric layer 25, the third dielectric layer 24, and the second dielectric layer 23; a third metal layer is disposed on the fourth dielectric layer 25 to form a gate 211 on the gate metal hole.

[0068] The method for fabricating the semiconductor device in this embodiment is the same as described above. Figure 1 The manufacturing method shown is similar, except that in this embodiment, when manufacturing the semiconductor device, after forming the source and the first field plate, and before forming the gate, a second field plate also needs to be formed.

[0069] Specifically, such as Figure 5 As shown, the method for fabricating the semiconductor device in this embodiment includes:

[0070] Step 201: Deposit a first dielectric layer and a second dielectric layer on the epitaxial layer of the substrate, and perform dielectric etching on the second dielectric layer and the second dielectric layer to form source and drain dielectrics.

[0071] In general, the semiconductor device manufacturing process mainly involves setting the various parts of the semiconductor device, including the source, gate, drain, and field plate, on the epitaxial layer of the substrate to obtain the semiconductor device.

[0072] In this embodiment, when fabricating a semiconductor device, firstly, a first dielectric layer and a second dielectric layer need to be deposited on the epitaxial layer of the substrate. Furthermore, when the semiconductor device includes a source and a drain, dielectric etching is performed on the second dielectric layer and the first dielectric layer to form the source and drain dielectric, so that the source and drain formed thereafter are on the same layer.

[0073] like Figure 6The diagram shows a cross-sectional view of a semiconductor device. On the epitaxial layer 21 of the substrate 20, the following components are disposed: a source 210, a gate 211, a drain 212, and a multilayer field plate (three-layer field plates are used as an example in the diagram) near the gate 211. The first field plate 2131 is on the same layer as the source 210 and drain 212, and the third field plate 2133 is connected to the gate 211. In this embodiment, a first dielectric layer 22 is deposited on the epitaxial layer 21 of the substrate 20, followed by the deposition of a second dielectric layer 23. Then, dielectric etching is performed on the second dielectric layer 23 and the first dielectric layer 22 to form the source and drain dielectrics. Specifically, vias are etched through the second dielectric layer 23 and the first dielectric layer 22, exposing the source and drain regions of the epitaxial layer 21.

[0074] Step 202: Metal deposition and etching are performed on the source and drain dielectric to form the source, drain and first field plate of the semiconductor device, and the gate position is reserved between the source and the first field plate.

[0075] Specifically, such as Figure 6 As shown, during metal deposition, a metal layer can be deposited on the source and drain dielectric. Then, metal etching is performed on this metal layer to form the source 210 (e.g., an ohmic metal for the source), the drain 212 (e.g., an ohmic metal for the drain), and the first field plate 2131. The gate position is reserved between the source 210 and the first field plate 2131, and the positions of other multilayer field plates (e.g., the second field plate 2132 and the third field plate 2133) are reserved between the drain 212 and the first field plate 2131. In this way, the formation of the source 210, the drain 212, and the first field plate 2131 is concentrated in the same step, simplifying the steps of setting each part on the epitaxial layer 21. Finally, the source 210, the drain 212, and the first field plate 2131 are formed on the same layer.

[0076] Step 203: Deposit a third dielectric layer, perform metal deposition (deposit a second metal layer) and metal etching on the third dielectric layer to form a second field plate. The second field plate is on top of the first field plate, and the projections of the second field plate and the first field plate in the substrate direction have an overlapping area.

[0077] like Figure 6 As shown, after the source 210, drain 212 and first field plate 2131 are formed, a third dielectric layer 24 can be deposited. Then, metal deposition and metal etching are performed on the third dielectric layer 24 to form a second field plate 2132. The second field plate 2132 needs to be on the first field plate 2131, and the projections of the second field plate 2132 and the first field plate 2131 in the direction of the substrate 20 have an overlapping area.

[0078] Step 204, depositing a fourth dielectric layer, and performing dielectric etching on the fourth dielectric layer, the third dielectric layer and the second dielectric layer at the gate position to form a gate dielectric.

[0079] As shown in Figure 6 , after forming the second layer field plate 2132, the fourth dielectric layer 25 can be deposited, and then the fourth dielectric layer 25, the third dielectric layer 24 and the second dielectric layer 23 are subjected to dielectric etching at the gate position between the source electrode 210 and the first layer field plate 2131 to form a gate dielectric. Specifically, when forming the gate dielectric, the fourth dielectric layer 25, the third dielectric layer 24 and the second dielectric layer 23 need to be etched through, and the first dielectric layer 22 is exposed.

[0080] Step 205, performing metal deposition (depositing a third metal layer) and metal etching on the gate dielectric to form a gate of the semiconductor device, i.e. forming the gate 211 on the first layer dielectric 22 in the gate region.

[0081] It should be noted that the above steps 201 to 205 are mainly methods for setting two layer field plates in a semiconductor device. In other embodiments, a third layer field plate and a fourth layer field plate can also be set in the semiconductor device. Specifically:

[0082] (1) When forming the third layer field plate:

[0083] Metal deposition and metal etching are performed on the gate dielectric to also form a third layer field plate. The third layer field plate is above the second layer field plate, and the projection of the third layer field plate and the second layer field plate in the substrate direction has an overlapping area. The gate is connected to the third layer field plate, or the gate is disconnected from the third layer field plate.

[0084] For example Figure 6 , metal deposition and metal etching are performed on the gate dielectric to simultaneously form the gate 211 and the third layer field plate 2133. The gate 211 is connected to the third layer field plate 2133. In other embodiments, as shown in Figure 7 , the gate 211 can be disconnected from the third layer field plate 2133. In this way, the third layer field plate 2133 can be more flexibly connected to the source electrode 210 or the gate 211 through subsequent metal interconnection processes. The projection of the third layer field plate 2133 and the second layer field plate 2132 in the substrate 20 direction has an overlapping area.

[0085] (2) When forming the fourth layer field plate:

[0086] A fifth dielectric layer is deposited, and metal deposition (depositing a fourth metal layer) and metal etching are performed on the fifth dielectric layer to form a fourth layer field plate. The fourth layer field plate is above the third layer field plate, and the projection of the fourth layer field plate and the third layer field plate in the substrate direction has an overlapping area.

[0087] For example Figure 8 As shown, after the third field plate 2133 is formed, the fifth dielectric layer 26 can be deposited, and metal deposition and metal etching can be performed on the fifth dielectric layer 26 to form the fourth field plate 2134. The fourth field plate 2134 and the third field plate 2133 have an overlapping region in the projection of the third field plate 2133 in the direction of the substrate 20.

[0088] As can be seen, in this embodiment of the present invention, the formation of the first field plate and the source electrode in the semiconductor device are concentrated in the same step during the manufacturing process of the semiconductor device, so that the formed source electrode and the first field plate are on the same layer. This simplifies the manufacturing steps of the semiconductor device, thereby reducing the implementation cost and time of setting the field plate in the semiconductor device.

[0089] Furthermore, the fabrication of the semiconductor device in this embodiment is similar to that described above. Figure 1 Compared to the above-mentioned methods for fabricating semiconductor devices, Figure 1 The method shown in the figure is used to fabricate semiconductor devices. Since only one field plate, namely the first field plate, is formed before the gate dielectric is formed, the dielectric etching depth required to form the gate dielectric is relatively low. It is only necessary to etch the dielectric to penetrate the third dielectric layer and the second dielectric layer and expose the first dielectric layer. This can reduce the dielectric etching time and better control the gate morphology. It is generally suitable for chip designs with small circuit board size.

[0090] The above provides a detailed description of a semiconductor device with a field plate according to the embodiments of the present invention. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A semiconductor device having a field plate, characterized by, comprising, a substrate; an epitaxial layer disposed on the substrate; a first dielectric layer and a second dielectric layer disposed on the epitaxial layer, the second dielectric layer having a source metal hole and a drain metal hole disposed therethrough; a first metal layer disposed on the second dielectric layer to form a source on the source metal hole, a drain on the drain metal hole, and a first layer field plate on the second dielectric layer; a third dielectric layer disposed on the first metal layer, the third dielectric layer having a gate metal hole disposed therethrough; and a second metal layer disposed on the third dielectric layer to form a gate on the gate metal hole.

2. The semiconductor device with field plate according to claim 1, characterized by, The second metal layer further comprises a second layer field plate, the second layer field plate being above the first layer field plate, and a projection of the second layer field plate and the first layer field plate in a substrate direction having an overlapping region; wherein the gate and the second layer field plate are connected.

3. The semiconductor device with field plate according to claim 1, wherein The second metal layer further comprises a second layer field plate, the second layer field plate being above the first layer field plate, and a projection of the second layer field plate and the first layer field plate in a substrate direction having an overlapping region; wherein the gate and the second layer field plate are disconnected.

4. A semiconductor device having a field plate as claimed in claim 2 or 3, characterized in that The semiconductor device further comprises: a fourth dielectric layer disposed on the second metal layer; and a third metal layer disposed on the fourth dielectric layer to form a third layer field plate on the fourth dielectric layer, the third layer field plate being above the second layer field plate, and a projection of the third layer field plate and the second layer field plate in the substrate direction having an overlapping region.

5. The semiconductor device with field plate according to claim 4, wherein The semiconductor device further comprises: a fifth dielectric layer disposed on the third metal layer; and a fourth metal layer disposed on the fifth dielectric layer to form a fourth layer field plate on the fifth dielectric layer, the fourth layer field plate being above the third layer field plate, and a projection of the fourth layer field plate and the third layer field plate in the substrate direction having an overlapping region.

6. A semiconductor device having a field plate, characterized by comprising, a substrate; an epitaxial layer disposed on the substrate; a first dielectric layer and a second dielectric layer disposed on the epitaxial layer, the second dielectric layer having a source metal hole and a drain metal hole disposed therethrough; a first metal layer disposed on the second dielectric layer to form a source on the source metal hole, a drain on the drain metal hole, and a first layer field plate on the second dielectric layer; a third dielectric layer disposed on the first metal layer; a second metal layer disposed on the third dielectric layer to form a second layer field plate on the third dielectric layer, the second layer field plate being above the first layer field plate, and a projection of the second layer field plate and the first layer field plate in a substrate direction having an overlapping region; a fourth dielectric layer disposed on the second metal layer, the fourth dielectric layer having a gate metal hole disposed therethrough, the third dielectric layer, and the second dielectric layer; and a third metal layer disposed on the fourth dielectric layer to form a gate on the gate metal hole. The second metal layer further comprises a second layer field plate, the second layer field plate being above the first layer field plate, and a projection of the second layer field plate and the first layer field plate in a substrate direction having an overlapping region; wherein the gate and the second layer field plate are connected. The second metal layer further comprises a second layer field plate, the second layer field plate being above the first layer field plate, and a projection of the second layer field plate and the first layer field plate in a substrate direction having an overlapping region; wherein the gate and the second layer field plate are disconnected.

7. The semiconductor device with field plate according to claim 6, wherein The third metal layer further comprises a third layer of field plate, the third layer of field plate is above the second layer of field plate, and the projection of the third layer of field plate and the second layer of field plate in the substrate direction has an overlapping area; wherein the gate and the third layer of field plate are connected.

8. The semiconductor device with field plate according to claim 6, wherein The third metal layer further comprises a third layer of field plate, the third layer of field plate is above the second layer of field plate, and the projection of the third layer of field plate and the second layer of field plate in the substrate direction has an overlapping area; wherein the gate and the third layer of field plate are disconnected.

9. The semiconductor device with field plate according to claim 7 or 8, characterized in that, The semiconductor device comprises: A fifth dielectric layer is arranged on the third metal layer; and A fourth metal layer is arranged on the fifth dielectric layer to form a fourth layer of field plate on the fifth dielectric layer, the fourth layer of field plate is above the third layer of field plate, and the projection of the fourth layer of field plate and the third layer of field plate in the substrate direction has an overlapping area.

10. The semiconductor device with a field plate according to claim 6, wherein, The semiconductor device includes but is not limited to MIS-HEMT device, P-GaN HEMT device and SBD-Gate HEMT device; the material of the semiconductor device includes but is not limited to gallium nitride, silicon, silicon carbide, gallium arsenide and gallium oxide.

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