Semiconductor device
By designing a masking layer with a second trench and filling it in a semiconductor device, the problem of masking layer incompatibility under different application scenarios is solved, and the masking layer can be manufactured on the same process platform, improving the compatibility and reliability of the device.
Patent Information
- Application Number
- CN202422930979.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2034-11-28
AI Technical Summary
Masking layers in semiconductor devices for different applications are difficult to fabricate on the same process platform, resulting in poor compatibility.
The masking layer is designed with a second trench and filled with filler. By controlling the total amount and size of ion doping in the masking layer, the masking layer can be manufactured on the same process platform to meet the needs of different application scenarios.
This improves the compatibility of semiconductor devices in different application scenarios, ensures that the total amount of ion doping in the masking layer meets the requirements, and enhances the reliability and performance of the devices.
Smart Images
Figure CN223639613U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor device. BACKGROUND
[0002] Trench Gate semiconductor devices achieve precise control of the conduction channel by forming downward trenches in the semiconductor material and filling the trenches with gate material. Among them, the trench gate semiconductor device is widely used in power management, motor drive, automotive electronics and industrial control fields due to its excellent performance (such as low on-resistance, high breakdown voltage, fast switching speed and good heat dissipation performance, etc.). By adopting the trench gate structure, the performance of the device can be significantly improved, making it more suitable for various high-demand application scenarios.
[0003] Among them, in the trench gate semiconductor device in the related art, in order to improve the reliability of the device, a masking layer is formed between two adjacent semiconductor cell units in the device to reduce the electric field intensity at the trench gate corner of the device in the reverse bias state.
[0004] In the related art, before forming the masking layer, a slot for accommodating the masking layer is formed on the semiconductor epitaxial layer, and then the masking layer is formed in the slot. However, due to the different performance and size of the semiconductor device in different application scenarios, the size of the masking layer is slightly different, that is, the size of the slot for forming the masking layer in the device in different application scenarios is different, so that the masking layer in the semiconductor device in different application scenarios is difficult to be prepared and formed on the same process platform, and the compatibility is not high. UTILITY MODEL CONTENT
[0005] The semiconductor device provided by the present application can solve the problem that the masking layer in the semiconductor device in different application scenarios is difficult to be prepared and formed on the same process platform, resulting in poor compatibility.
[0006] To solve the above technical problems, one technical solution adopted by the present application is to provide a semiconductor device, comprising:
[0007] a substrate;
[0008] a semiconductor epitaxial layer disposed on a surface of the substrate;
[0009] a plurality of semiconductor cell units disposed in the semiconductor epitaxial layer and extending along a first direction away from the surface of the semiconductor epitaxial layer facing the substrate; the first direction is the direction of the first surface of the semiconductor epitaxial layer facing the substrate;
[0010] The semiconductor epitaxial layer further has a first groove between two adjacent semiconductor cell units, the first groove extending along a first direction from the surface of the semiconductor epitaxial layer away from the substrate; a mask layer is formed on the groove wall of the first groove, and the mask layer has a second groove, and the second groove is further filled with a filler.
[0011] Compared with the prior art, the semiconductor device provided by the application has the following beneficial effects: the semiconductor device comprises a substrate, a semiconductor epitaxial layer, and a plurality of semiconductor cell units; the semiconductor epitaxial layer is arranged on a surface of the substrate; the plurality of semiconductor cell units are arranged in the semiconductor epitaxial layer and extend along a first direction from the surface of the semiconductor epitaxial layer away from the substrate; the first direction is a direction in which a first surface of the semiconductor epitaxial layer faces the substrate; the semiconductor epitaxial layer further has a first groove between two adjacent semiconductor cell units, the first groove extending along the first direction from the surface of the semiconductor epitaxial layer away from the substrate; a mask layer is formed on the groove wall of the first groove, and the mask layer has a second groove, and the second groove is further filled with a filler. Specifically, the semiconductor device provided by the application has the second groove in the mask layer, so that the size of the second groove in the mask layer can be changed without changing the design size of the first groove for accommodating the mask layer, so as to ensure that the total amount of ion doping of the mask layer meets the requirements, thereby achieving the effect of manufacturing the mask layer on the same process platform and improving the compatibility of the product. BRIEF DESCRIPTION OF DRAWINGS
[0012] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.
[0013] Figure 1 Part structure schematic diagram of the semiconductor device provided by an embodiment of the application;
[0014] Figure 2 Part structure schematic diagram of the semiconductor device provided by another embodiment of the application;
[0015] Figure 3 Part structure schematic diagram of the semiconductor device provided by another embodiment of the application;
[0016] Figure 4 Part structure schematic diagram of the semiconductor device provided by another embodiment of the application.
[0017] Label explanation:
[0018] Substrate 10;
[0019] epitaxial layer 20; semiconductor cell unit 30; first cell 31; second cell 32; first doped region 33; second doped region 34;
[0020] trench electrode 40; gate electrode 41; gate dielectric layer 42;
[0021] source electrode 50;
[0022] drain electrode 60;
[0023] ohmic contact metal 70;
[0024] gate insulating layer 80;
[0025] masking layer 90; filler 100;
[0026] first trench T1; second trench T2; third trench T3. DETAILED DESCRIPTION
[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.
[0028] The terms "first", "second", "third" in the present application are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise specifically limited. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.
[0029] Reference to an "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase that the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.
[0030] Reference to an "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase that the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments. Figure 1 , Figure 1 A partial structure schematic diagram of a semiconductor device provided by an embodiment of the application is shown in FIG. 1.
[0031] Specifically, the semiconductor device provided by the application includes a substrate 10, a semiconductor epitaxial layer 20, a plurality of semiconductor cell units 30, a gate electrode 41, a source electrode 50, a drain electrode 60, and an ohmic contact metal 70.
[0032] The material of the substrate 10 includes, but is not limited to, silicon, silicon carbide, sapphire, etc.
[0033] The semiconductor epitaxial layer 20 is arranged on a surface of the substrate 10; the semiconductor epitaxial layer 20 and the substrate 10 have the same conductivity type. For example, the conductivity type of the semiconductor epitaxial layer 20 and the substrate 10 is N type, or the conductivity type of the semiconductor epitaxial layer 20 and the substrate 10 is P type, which is not limited herein.
[0034] The plurality of semiconductor cell units 30 are arranged in the semiconductor epitaxial layer 20 and extend along a first direction from the surface of the semiconductor epitaxial layer 20 away from the substrate 10; the first direction is the direction of the first surface of the semiconductor epitaxial layer 20 toward the substrate 10. The function and structure of the semiconductor cell units 30 can be the same as those of the semiconductor cell units in the existing device.
[0035] Alternatively, in some embodiments of the application, each semiconductor cell unit 30 includes a first cell 31 and a second cell 32 arranged at intervals; and the first cell 31 and the second cell 32 each include a first doped region 33 and a second doped region 34 connected to each other, the first doped region 33 is located on the side of the second doped region 34 close to the substrate 10; the first doped region 33 is different from the doping type of the semiconductor epitaxial layer 20, and the second doped region 34 is the same as the doping type of the semiconductor epitaxial layer 20. The first doped region 33 can be understood as a well region of the device, and the second doped region 34 can be understood as a source region of the device.
[0036] The gate electrode 41, the source electrode 50, and the drain electrode 60 are used for electrical connection between the device and an external circuit.
[0037] The drain electrode 60 is disposed on the surface of the substrate 10 away from the semiconductor epitaxial layer 20. The ohmic contact metal 70 is disposed on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 and is in ohmic contact with the semiconductor cell unit 30. The source electrode 50 is disposed on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 and covers the ohmic contact metal 70 to be connected to the source region in the semiconductor cell unit 30 through the ohmic contact metal 70.
[0038] Please refer to Figure 1 and Figure 2 , Figure 2 A partial structure schematic diagram of a semiconductor device provided by another embodiment of the present application is shown. In the embodiment of the present application, the semiconductor device is a trench gate semiconductor device. Specifically, the semiconductor epitaxial layer 20 further has a third trench T3 between the first cell 31 and the second cell 32 in each semiconductor cell unit 30, and the depth H1 of the third trench T3 extending along the first direction is greater than the depth H2 of the semiconductor cell unit 30 extending along the first direction. The third trench T3 is filled with a trench electrode 40, and the trench electrode 40 includes a gate electrode 41 and a gate dielectric layer 42. ， The gate dielectric layer 42 is used to insulate the gate electrode 41 from the semiconductor epitaxial layer 20 and the semiconductor cell unit 30.
[0039] Specifically, the trench gate semiconductor device is widely used in power management, motor drive, automotive electronics, industrial control and other fields due to its excellent performance (such as low on-resistance, high breakdown voltage, fast switching speed and good heat dissipation performance, etc.). By adopting the trench gate structure, the performance of the device can be significantly improved, making it more suitable for various high-demand application scenarios.
[0040] In some embodiments, the end surface of the trench electrode 40 away from the substrate 10 is higher than the surface of the first doped region 33 away from the substrate 10.
[0041] Specifically, the end surface of the trench electrode 40 away from the substrate 10 is set to be higher than the surface of the first doped region 33 away from the substrate 10, so that in the device forward bias state, the trench electrode 40 can control the region of the first doped region 33 close to the trench electrode 40 to form a channel, so as to realize electrical conduction between the semiconductor epitaxial layer 20 and the second doped region 34 through the channel formed in the first doped region 33, and further realize electrical conduction between the drain electrode 60 and the source electrode 50.
[0042] Further, as shown in Figure 2 In some embodiments, the spacing H3 between the end surface of the trench electrode 40 away from the substrate 10 and the surface of the first doped region 33 away from the substrate 10 is greater than 0.1 μm.
[0043] For example, the distance H3 between the end surface of the trench electrode 40 facing away from the substrate 10 and the surface of the first doped region 33 facing away from the substrate 10 is greater than 0.1 μm, 0.3 μm, or 0.5 μm, etc., without being limited herein.
[0044] Specifically, the distance H3 between the end surface of the trench electrode 40 facing away from the substrate 10 and the surface of the first doped region 33 facing away from the substrate 10 is greater than 0.1 μm, so as to ensure that, in the on-state of the trench electrode 40, the channel formed in the first doped region 33 can connect the semiconductor epitaxial layer 20 and the second doped region 34, thereby conducting the current path between the source electrode 50 and the drain electrode 60.
[0045] Referring to Figure 1 or Figure 3 , Figure 3 A partial structure schematic diagram of a semiconductor device provided by another embodiment of the present application is shown in FIG. 4.
[0046] In some embodiments, the semiconductor device further comprises a gate insulating layer 80, which is used to insulate the trench electrode 40 from the source electrode 50.
[0047] Referring to Figure 3 In the case where the trench electrode 40 fills the third trench T3, the gate insulating layer 80 is arranged on the surface of the semiconductor epitaxial layer 20 facing away from the substrate 10, and covers the third trench T3, and the source electrode 50 further covers the gate insulating layer 80.
[0048] Referring to Figure 1 In the case where the trench electrode 40 does not fill the third trench T3, the gate insulating layer 80 is arranged on the surface of the semiconductor epitaxial layer 20 facing away from the substrate 10, and at least part of the gate insulating layer 80 extends into the third trench T3, and the source electrode 50 further covers the gate insulating layer 80.
[0049] Specifically, arranging the trench electrode 40 not to fill the third trench T3 and at least part of the gate insulating layer 80 extending into the third trench T3 can improve the insulation capability of the gate insulating layer 80 between the trench electrode 40 and the source electrode 50.
[0050] In the trench gate semiconductor device, the electric field intensity at the corner of the trench electrode 40 is relatively large in the reverse bias state of the device, and in order to improve the reliability of the device, referring to Figure 1 The present application further forms a shielding layer 90 between two adjacent semiconductor cell units 30 in the device, so as to reduce the electric field intensity at the corner of the trench gate in the reverse bias state of the device, and improve the reliability of the device.
[0051] Specifically, the semiconductor epitaxial layer 20 also has a first trench T1 located between two adjacent semiconductor cell units 30, the first trench T1 extends along a first direction from the surface of the semiconductor epitaxial layer 20 away from the substrate 10; a mask layer 90 is formed on the trench wall of the first trench T1, and the mask layer 90 has a second trench T2, and the second trench T2 is also filled with a filler 100.
[0052] The mask layer 90 is different in conductive type from the semiconductor epitaxial layer 20. For example, the semiconductor epitaxial layer 20 is of N type, and the mask layer 90 is of P type.
[0053] In the embodiment of the present application, the mask layer 90 is formed by epitaxial growth on the trench wall of the first trench T1. Since the mask layer 90 is formed by epitaxial growth from the bottom wall and the side wall of the first trench T1 towards the inside of the first trench T1, for different application scenarios, to improve product compatibility, the size of the first trench T1 can not be changed, but the epitaxial growth of the mask layer 90 is controlled to not fill the first trench T1, and only the total amount of ion doping of the mask layer 90 needs to be determined. Since the total amount of ion doping of the mask layer 90 = thickness of the mask layer 90 * ion doping concentration of the mask layer 90, by controlling the thickness (side wall thickness, bottom wall thickness) and / or ion doping concentration of the mask layer 90, a mask layer 90 with a predetermined total amount of ion doping can be formed in the first trench T1.
[0054] It can be understood that since the mask layer 90 is formed by epitaxial growth from the bottom wall and the side wall of the first trench T1 towards the inside of the first trench T1, and the mask layer 90 does not fill the first trench T1, the mask layer 90 includes a mask layer side wall 91 epitaxially grown on the side wall of the first trench T1 and a mask layer bottom wall 92 epitaxially grown on the bottom wall of the first trench T1, and the mask layer side wall 91 and the mask layer bottom wall 92 cooperate to form the second trench T2.
[0055] It can be understood that when the total amount of ion doping and the ion doping concentration of the mask layer 90 are determined, the thickness of the mask layer side wall 91 and the mask layer bottom wall 92 of the mask layer 90 is also determined, that is, the size of the second trench T2 is also determined. Therefore, for different application scenarios, the design size of the first trench T1 for accommodating the mask layer 90 can not be changed, and only the size of the second trench T2 formed in the mask layer 90 can be changed, so as to ensure that the total amount of ion doping of the mask layer 90 meets the requirements, thereby achieving the effect of manufacturing the mask layer 90 on the same process platform and improving the compatibility of the product.
[0056] Since the second trench T2 is also filled with a filler 100, the material of the filler 100 includes but is not limited to dielectric such as silicon dioxide, silicon carbide, aluminum oxide, aluminum nitride, etc. In this way, the second groove is filled with the filler, so as to avoid affecting the subsequent process.
[0057] Referring to Figure 2 In some embodiments, the first trench T1 has a depth H4 along the first direction of 1-15 μm.
[0058] For example, the depth H4 of the first trench T1 can be 1 μm, 3 μm, 5 μm, 8 μm, 12 μm, or 15 μm, etc., without being limited herein.
[0059] It should be noted that the depth H4 of the first trench T1 along the first direction is less than the thickness of the semiconductor epitaxial layer 20. The thickness direction of the semiconductor epitaxial layer 20 is the same as the first direction.
[0060] Referring to Figure 2 In some embodiments, the depth H4 of the first trench T1 along the first direction is greater than the depth H2 of the semiconductor cell unit 30 along the first direction.
[0061] It can be understood that, since the masking layer 90 is formed in the first trench T1, the depth of the masking layer 90 along the first direction is greater than the depth H2 of the semiconductor cell unit 30 along the first direction.
[0062] Specifically, the depth H4 of the first trench T1 along the first direction is designed to be greater than the depth H2 of the semiconductor cell unit 30 along the first direction, so that the masking layer 90 can effectively reduce the electric field intensity at the corner of the trench electrode 40 in the device reverse bias state, improve the device voltage level, and further improve the device reliability.
[0063] Referring to Figure 2 Further, in some embodiments, the depth H4 of the first trench T1 along the first direction is greater than the depth H1 of the third trench T3 along the first direction.
[0064] It can be understood that, since the masking layer 90 is formed in the first trench T1, the depth of the masking layer 90 along the first direction is greater than the depth H1 of the third trench T3 along the first direction.
[0065] Specifically, the depth of the masking layer 90 along the first direction is designed to be greater than the depth H1 of the third trench T3 along the first direction, so that the masking layer 90 can effectively reduce the electric field intensity at the corner of the trench electrode 40 in the device reverse bias state, improve the device voltage level, and further improve the device reliability.
[0066] Of course, in other embodiments, referring to Figure 4 , Figure 4The partial structure diagram of the semiconductor device provided by another embodiment of the present application is shown in FIG. 6. The depth H4 of the first trench T1 extending along the first direction can also be equal to the depth H2 of the semiconductor cell unit 30 extending along the first direction. As long as the effect of reducing the electric field intensity at the corner of the trench electrode 40 and improving the reliability of the device can be achieved.
[0067] The above description is merely an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.
Claims
1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; a semiconductor epitaxial layer disposed on a surface of the substrate; a plurality of semiconductor cell units disposed in the semiconductor epitaxial layer and extending along a first direction away from the surface of the semiconductor epitaxial layer toward the substrate; the first direction is a direction of a first surface of the semiconductor epitaxial layer toward the substrate; wherein the semiconductor epitaxial layer further has a first trench between two adjacent semiconductor cell units, the first trench extending along the first direction away from the surface of the semiconductor epitaxial layer toward the substrate; a mask layer is formed on a trench wall of the first trench, and the mask layer has a second trench filled with a filler.
2. The semiconductor device according to claim 1, wherein The depth of the first trench extending along the first direction is 1-15 μm.
3. The semiconductor device of claim 1, wherein The depth of the first trench extending along the first direction is greater than the depth of the semiconductor cell unit extending along the first direction.
4. The semiconductor device of claim 1, wherein The depth of the first trench extending along the first direction is equal to the depth of the semiconductor cell unit extending along the first direction.
5. The semiconductor device according to any one of claims 1 to 3, wherein Each semiconductor cell unit comprises a first cell and a second cell, and the semiconductor epitaxial layer further has a third trench between the first cell and the second cell of each semiconductor cell unit, and the depth of the third trench extending along the first direction is greater than the depth of the semiconductor cell unit extending along the first direction. The third trench is filled with a trench electrode, and the trench electrode comprises a gate electrode and a gate dielectric layer for insulating the gate electrode from the semiconductor epitaxial layer and the semiconductor cell unit.
6. The semiconductor device of claim 5, wherein, The first cell and the second cell each comprise a first doped region and a second doped region abutting each other, and the first doped region is located on a side of the second doped region close to the substrate; the first doped region is different from the doping type of the semiconductor epitaxial layer, and the second doped region is the same as the doping type of the semiconductor epitaxial layer. An end surface of the trench electrode away from the substrate is higher than a surface of the first doped region away from the substrate.
7. The semiconductor device of claim 6, wherein, The distance between the end surface of the trench electrode away from the substrate and the surface of the first doped region away from the substrate is greater than 0.1 μm.
8. The semiconductor device of claim 5, wherein, The depth of the first trench extending along the first direction is greater than the depth of the third trench extending along the first direction.
9. The semiconductor device of claim 5, wherein, The semiconductor device further comprises a gate insulating layer, and at least part of the gate insulating layer extends into the third trench.
10. The semiconductor device of claim 1, wherein The semiconductor device further comprises: a plurality of ohmic contact metals disposed on a surface of the semiconductor epitaxial layer away from the substrate and in ohmic contact with the semiconductor cell units; a source electrode disposed on the surface of the semiconductor epitaxial layer away from the substrate and covering the ohmic contact metals; a drain electrode disposed on a surface of the substrate away from the semiconductor epitaxial layer.