Gigabit passive optical network packaging chip

Abstract

The utility model discloses a gigabit passive optical network (GPON) packaging chip, which relates to the technical field of chips and structurally comprises a chip component, a connecting component, a packaging layer, a substrate component and a conductive component, the chip component is responsible for data processing and communication functions in a GPON network, and a first electrode for signal and power transmission is arranged on the surface of the chip component; the connecting component is arranged at the position of the first electrode, so that the chip is electrically connected with an external circuit; and the packaging layer wraps the chip component, so that good insulating property and corrosion resistance are provided, and the chip is protected from being damaged by the external environment. The substrate component supports the chip component and the packaging layer and is provided with a first through hole corresponding to the first electrode; the first through hole is filled with the conductive component, stable electric connection between the chip and an external circuit is achieved, the packaging layer is provided with a plurality of through grooves in the direction parallel to the surface of the chip, the contact area between the packaging layer and the external environment is increased through the through grooves, and an additional heat conduction path is provided.

Description

Technical Field

[0001] This utility model relates to the field of chip technology, specifically a gigabit passive optical network packaged chip. Background Technology

[0002] Gigabit-Capable Passive Optical Network (GPON) is widely used in various fields such as home broadband networks, enterprise networks, government and school networks due to its high bandwidth, high efficiency, wide coverage and rich user interfaces. During the operation of GPON packaged chips, a large number of electronic components are integrated inside the chip. These components generate a lot of heat when running at high speed. Existing heat dissipation methods mainly rely on the thermal conductivity of the package layer material to conduct the heat generated by the chip to the external environment through the package layer. However, with the continuous increase in the integration of GPON packaged chips, the existing heat dissipation methods are no longer sufficient to meet the heat dissipation requirements. Utility Model Content

[0003] The purpose of this invention is to provide a gigabit passive optical network package chip to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, this utility model provides the following technical solution:

[0005] A gigabit passive optical network package chip, the structure of which includes:

[0006] A chip component, the chip component having a first surface, and a first electrode disposed at the position of the first surface;

[0007] A connecting member is arranged at the position of the first electrode;

[0008] Encapsulation layer, configured to encapsulate chip components;

[0009] A substrate component is configured to support a chip component and a packaging layer, and a first through-hole is arranged on the substrate component corresponding to the position of the first electrode.

[0010] A conductive component is arranged to fill a first through hole, and a first electrode is connected to one end of the conductive component through a connecting component.

[0011] The encapsulation layer has multiple through slots arranged along a first direction, which is parallel to the first surface of the chip component.

[0012] Preferably, the connecting member is configured as a solder ball;

[0013] And / or, the substrate component is configured as a glass substrate;

[0014] And / or, the encapsulation layer is configured as resin.

[0015] Preferably, the conductive component includes a first portion and a second portion connected to the first portion;

[0016] The outer surface area of ​​the second part that is parallel to the first surface is greater than the outer surface area of ​​the first part that is parallel to the first surface.

[0017] Preferably, all through slots are divided into multiple groups, with different groups of through slots located on different planes, and through slots in the same group located on the same plane.

[0018] Preferably, the planes formed by different groups of through slots are at different distances from the chip components, and the farther away from the chip components, the fewer through slots are included in the planes formed by the through slots.

[0019] Preferably, the surface of the encapsulation layer away from the chip component is arranged as a second surface, and the second surface is connected to a heat dissipation component.

[0020] Preferably, the encapsulation layer and the heat dissipation component form a bonding surface, the encapsulation layer forms a plurality of first grooves on the bonding surface, and the heat dissipation component has a first protrusion arranged corresponding to the first groove, the first protrusion being embedded in the first groove.

[0021] Preferably, the first protrusion is hemispherical or frustum-shaped.

[0022] Preferably, the heat dissipation component is made of copper.

[0023] Compared with the prior art, the beneficial effects of this utility model are:

[0024] This utility model discloses a gigabit passive optical network (GPON) packaged chip, the structure of which includes a chip component, a connecting component, a package layer, a substrate component, and a conductive component. The chip component is responsible for data processing and communication functions in the GPON network, and its surface is arranged with a first electrode for signal and power transmission. The connecting component is arranged at the location of the first electrode to realize the electrical connection between the chip and the external circuit. The package layer covers the chip component, providing good insulation and corrosion resistance, protecting the chip from external environmental damage. The substrate component supports the chip component and the package layer, and has a first through-hole corresponding to the first electrode. The conductive component fills the first through-hole and is made of conductive materials such as copper and gold, realizing a stable electrical connection between the chip and the external circuit. The package layer has multiple through slots arranged along a direction parallel to the chip surface. These through slots increase the contact area between the package layer and the external environment, providing additional heat conduction paths, which helps heat to be quickly transferred to the outside of the package layer and dissipated into the surrounding environment. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the packaged chip structure in one embodiment.

[0026] Figure 2 This is a side view of the encapsulation layer in one embodiment.

[0027] Figure 3 This is a schematic diagram of the heat dissipation component in one embodiment.

[0028] Figure 4 This is a schematic diagram of the structure of a substrate component in one embodiment. Detailed Implementation

[0029] The technical solution of this patent will be further described in detail below with reference to specific embodiments.

[0030] The embodiments of this patent are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this patent, and should not be construed as limiting this patent.

[0031] In the description of this patent, it should be understood that the terms "middle", "bottom", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "both sides", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this patent and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this patent.

[0032] In the description of this patent, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "assembly" should be interpreted broadly. For example, they can refer to a fixed connection or installation, a detachable connection or installation, or an integral connection or installation. Those skilled in the art can understand the specific meaning of the above terms in this patent according to the specific circumstances.

[0033] Please refer to Figures 1 to 2 One embodiment discloses a gigabit passive optical network (PON) package chip, the structure of which includes a chip component 1 having a first surface and a first electrode 11 disposed at the position of the first surface; a connecting component 2 disposed at the position of the first electrode 11; a package layer 3 configured to cover the chip component 1; a substrate component 4 configured to support the chip component 1 and the package layer 3, and a first through hole disposed at the position of the first electrode 11 corresponding to the position of the substrate component 4; a conductive component 5 disposed to fill the first through hole, and the first electrode 11 is connected to one end of the conductive component 5 through the connecting component 2; wherein, the package layer 3 is provided with a plurality of through slots 7 along a first direction, the first direction being parallel to the first surface of the chip component 1.

[0034] Specifically, chip component 1 is responsible for data processing and communication functions in the GPON network. It has a first surface on which a first electrode 11 is arranged. The first electrode 11 is used to transmit signals and power. A connecting component 2 is arranged at the position of the first electrode 11 to realize the electrical connection between chip component 1 and external circuit. An encapsulation layer 3 protects chip component 1 from external environmental damage and has good insulation and corrosion resistance. The encapsulation layer 3 covers the chip component 1, forming a closed environment to prevent dust, moisture and other harmful substances from entering the chip. A substrate component 4 supports chip component 1. A first through-hole is arranged on the substrate component 4 corresponding to the position of the first electrode 11. A conductive component 5 is arranged to fill the first through-hole to realize the electrical connection between chip component 1 and external circuit. The conductive component 5 can be made of conductive materials such as copper or gold. One end of the conductive component 5 is connected to the connecting component 2, and the other end is connected to the external circuit. Through the conductive component 5, the first electrode 11 on the chip component 1 can achieve a stable electrical connection with the external circuit. In one embodiment, the carrier of the external circuit is a PCB driving panel. Multiple through slots 7 are arranged along the first direction (parallel to the first surface of the chip component 1) and penetrate the thickness direction of the encapsulation layer 3, forming multiple channels between the interior of the encapsulation layer 3. This increases the contact area between the encapsulation layer and the external environment. When the chip component 1 generates heat during operation, this heat is first conducted to the encapsulation layer 3 through the material of the chip component 1. Since multiple through slots 7 are provided in the encapsulation layer 3, these through slots 7 provide additional heat conduction paths. Heat can be quickly transferred along the through slots 7 to the outer surface of the encapsulation layer 3 and then dissipated into the surrounding environment. In another embodiment, a cooling fan is provided outside the encapsulation layer. When there is flowing air outside the encapsulation layer 3, the heat on the surface of the encapsulation layer 3 is carried away by the flowing medium (air), thereby achieving rapid heat dissipation.

[0035] Furthermore, the connecting member 2 is configured as a solder ball; and / or, the substrate member 4 is configured as a glass substrate; and / or, the encapsulation layer 3 is configured as resin. The selection of the above materials is only an example and is not unique in the specific implementation.

[0036] Please continue to refer to this. Figure 1 In one embodiment, the conductive member 5 includes a first portion 51 and a second portion 52 connected to the first portion; wherein the outer surface area of ​​the second portion 52 parallel to the first surface is greater than the outer surface area of ​​the first portion 51 parallel to the first surface.

[0037] Specifically, the first part 51 is connected to the connecting member 2 (such as a solder ball), and is also connected to the second part 52 to achieve the transmission of electrical signals. The second part 52 is an electrode connected to an external driving circuit. It is connected to the first part 51 and extends outward to expose the surface of the substrate member 4. The outer surface area of ​​the second part 52 parallel to the first surface is larger than the outer surface area of ​​the first part 51 parallel to the first surface. The larger connection area makes it easier for the second part 52 to be connected to the external driving circuit, reducing the connection difficulty.

[0038] Please refer to Figure 2 In one implementation, all through slots 7 are divided into multiple groups. Different groups of through slots 7 are located on different planes, while the same group of through slots 7 are located on the same plane. The planes formed by different groups of through slots 7 are at different distances from the chip component 1. The farther away from the chip component 1, the fewer through slots 7 are included in the planes formed by the through slots 7.

[0039] Specifically, the encapsulation layer 3 includes multiple planes containing through-slots 7 along its thickness direction. Uniform heat dissipation is achieved at different depths of the encapsulation layer, preventing excessive heat concentration in certain areas. The distances between the planes formed by different groups of through-slots 7 and the chip component 1 vary, with fewer through-slots 7 on planes farther from the chip component 1. Areas closer to the chip experience more concentrated heat generation, and more through-slots enhance heat dissipation. However, excessive through-slots weaken the strength of the encapsulation layer, especially in areas farther from the chip where heat is less concentrated; in such areas, too many through-slots can actually increase the risk of damage to the encapsulation layer. Therefore, by reducing the number of through-slots in certain areas, the strength of the encapsulation layer can be maintained while ensuring effective heat dissipation.

[0040] Please continue to refer to this. Figure 1 In one embodiment, the surface of the encapsulation layer 3 away from the chip component 1 is arranged as a second surface, and the second surface is connected to the heat dissipation component 6. The heat dissipation component material includes metal (such as copper, aluminum, etc.), graphite, ceramic, etc.

[0041] Please refer to Figure 3 Furthermore, the encapsulation layer 3 and the heat dissipation component 6 form a bonding surface. The encapsulation layer 3 forms a plurality of first grooves on the bonding surface. The heat dissipation component 6 has a first protrusion arranged corresponding to the first groove. The first protrusion is embedded in the first groove. Specifically, when the heat dissipation component is bonded to the encapsulation layer, the first protrusion will be embedded in the first groove to form a tight mechanical connection, which enhances the bonding strength between the encapsulation layer and the heat dissipation component. Moreover, due to the setting of the first protrusion, its contact area with the encapsulation layer 3 is relatively increased. By increasing the contact area, the efficiency of heat transfer is improved. The shape of the first protrusion can be hemispherical or frustum-shaped.

[0042] Please refer to Figure 4In one embodiment, a connection groove 41 is arranged on the peripheral surface of the substrate component 4 at the location of the chip component 1. Specifically, an encapsulation layer material is uniformly coated on the substrate component 4, and the encapsulation layer material is filled into the connection groove 41. The encapsulation layer material is cured and formed on the substrate component through an appropriate curing process (such as thermosetting, ultraviolet curing, etc.). During the curing process, the connection groove 41 enables the encapsulation layer material to form more mechanical interlocking structures during curing, thereby enhancing the bonding strength with the substrate component.

[0043] In summary, this utility model discloses a gigabit passive optical network (GPON) packaged chip, the structure of which includes a chip component, a connecting component, a package layer, a substrate component, and a conductive component. The chip component is responsible for data processing and communication functions in the GPON network, and its surface is provided with a first electrode for signal and power transmission. The connecting component is arranged at the location of the first electrode to realize the electrical connection between the chip and the external circuit. The package layer covers the chip component, providing good insulation and corrosion resistance, protecting the chip from external environmental damage. The substrate component supports the chip component and the package layer, and has a first through-hole corresponding to the first electrode. The conductive component fills the first through-hole and is made of conductive materials such as copper or gold, realizing a stable electrical connection between the chip and the external circuit. The package layer has multiple through slots arranged along a direction parallel to the chip surface. These through slots increase the contact area between the package layer and the external environment, providing additional heat conduction paths, which helps heat to be quickly transferred to the outside of the package layer and dissipated into the surrounding environment.

[0044] The above are merely preferred embodiments of this utility model. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of this utility model, and these should also be considered within the scope of protection of this utility model. These will not affect the implementation effect of this utility model or the practicality of the patent.

Claims

1. A gigabit passive optical network (PON) packaged chip, characterized in that, include: A chip component (1) has a first surface and a first electrode (11) is arranged at the position of the first surface. A connecting member (2) is arranged at the position of the first electrode (11); Encapsulation layer (3), the encapsulation layer (3) is configured to cover the chip component (1); A substrate component (4) is configured to support the chip component (1) and the encapsulation layer (3). A first through hole is arranged on the substrate component (4) at the position corresponding to the first electrode (11). A conductive member (5) is arranged to fill the first through hole, and the first electrode (11) is connected to one end of the conductive member (5) through the connecting member (2). The encapsulation layer (3) has a plurality of through slots (7) arranged along a first direction, which is parallel to the first surface of the chip component (1).

2. The gigabit passive optical network package chip according to claim 1, characterized in that, The connecting member (2) is configured as a solder ball; And / or, the substrate component (4) is configured as a glass substrate; And / or, the encapsulation layer (3) is configured as resin.

3. The gigabit passive optical network packaged chip according to claim 1, characterized in that, The conductive component (5) includes a first part (51) and a second part (52) connected to the first part; The outer surface area of ​​the second part (52) that is parallel to the first surface is greater than the outer surface area of ​​the first part (51) that is parallel to the first surface.

4. A gigabit passive optical network packaged chip according to claim 1, characterized in that, All the through slots (7) are divided into multiple groups, and the through slots (7) in different groups are located on different planes, while the through slots (7) in the same group are located on the same plane.

5. A gigabit passive optical network packaged chip according to claim 4, characterized in that, The plane formed by the through slots (7) of different groups is at a different distance from the chip component (1), and the farther away from the chip component (1), the fewer the number of through slots (7) included in the plane formed by the through slots (7).

6. A gigabit passive optical network package chip according to claim 1, characterized in that, The surface of the encapsulation layer (3) away from the chip component (1) is arranged as a second surface, and the second surface is connected to the heat dissipation component (6).

7. A gigabit passive optical network package chip according to claim 6, characterized in that, The encapsulation layer (3) and the heat dissipation component (6) form a bonding surface. The encapsulation layer (3) forms a plurality of first grooves on the bonding surface. The heat dissipation component (6) has a first protrusion arranged in the first groove, and the first protrusion is embedded in the first groove.

8. A gigabit passive optical network packaged chip according to claim 7, characterized in that, The first protrusion is hemispherical or frustum-shaped.

9. A gigabit passive optical network package chip according to claim 7, characterized in that, The heat dissipation component (6) is made of copper.

10. A gigabit passive optical network packaged chip according to claim 1, characterized in that, The substrate component (4) has a connecting groove (41) arranged on the outer surface of the chip component (1).

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