Display panel and display device

Abstract

The utility model provides a display panel and a display device. The display panel comprises a substrate, a first transparent electrode layer, a second transparent electrode layer and a semiconductor layer, the first transparent electrode layer, the second transparent electrode layer and the semiconductor layer are arranged on the substrate, the first transparent electrode layer comprises a first polar plate, the second transparent electrode layer comprises a second polar plate, the semiconductor layer comprises a third polar plate, and the first polar plate, the second polar plate and the third polar plate all have overlapped parts. The first polar plate, the second polar plate and the third polar plate form a storage capacitor of the display panel; the first polar plate and the second polar plate are arranged between the substrate and the semiconductor layer, and the third polar plate is arranged by using the material of the semiconductor layer, so that the first polar plate, the second polar plate and the third polar plate form a capacitor structure arranged in parallel, and the capacitance of the storage capacitor is increased; therefore, the threshold voltage of the driving transistor is effectively compensated, and the display picture of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Organic Light-Emitting Diode (OLED) is a new type of current semiconductor light-emitting device, which is a kind of display device by controlling the carrier and excited organic material light-emitting.

[0003] With the increase of the resolution of the current OLED display panel, the area of a single sub-pixel is reduced, and there is not enough space to set a storage capacitor in the pixel area, so that the threshold voltage of the driving transistor cannot be effectively compensated, resulting in display panel display abnormality. UTILITY MODEL CONTENT

[0004] The present application provides a display panel and a display device to solve the technical problem of small capacitance of the storage capacitor in the existing OLED display panel.

[0005] To solve the above-mentioned scheme, the technical scheme provided by the present application is as follows:

[0006] The present application provides a display panel, which comprises:

[0007] a substrate substrate;

[0008] a first transparent electrode layer provided on one side of the substrate substrate, the first transparent electrode layer comprising a first electrode plate;

[0009] a second transparent electrode layer provided on the side of the first transparent electrode layer away from the substrate substrate, the second transparent electrode layer comprising a second electrode plate; and

[0010] a semiconductor layer provided on the side of the second transparent electrode layer away from the substrate substrate, the semiconductor layer comprising a third electrode plate;

[0011] Wherein, the first electrode plate, the second electrode plate and the third electrode plate all have overlapping parts, and the first electrode plate, the second electrode plate and the third electrode plate constitute the storage capacitor of the display panel.

[0012] Optionally, the display panel further comprises a light shielding layer provided between the first transparent electrode layer and the second transparent electrode layer, the semiconductor layer comprises a first active part located in the display area of the display panel, and the light shielding layer comprises a light shielding part corresponding to the first active part.

[0013] The first transparent electrode layer further comprises a transparent portion spaced apart from the first plate, and the light-shielding portion is arranged on a surface of the transparent portion away from the substrate, and the light-shielding portion and the transparent portion have the same pattern.

[0014] Optionally, a distance between the first plate and the second plate is less than a distance between the second plate and the third plate.

[0015] Optionally, the display panel further comprises:

[0016] a spacing layer arranged on a side of the light-shielding layer away from the substrate, the spacing layer covering the light-shielding layer and the first transparent electrode layer, and part of the spacing layer being in contact with the substrate;

[0017] a buffer layer arranged on a side of the second transparent electrode layer away from the substrate, the buffer layer covering the second transparent electrode layer, and part of the buffer layer being in contact with the spacing layer;

[0018] The material of the spacing layer is different from the material of the buffer layer.

[0019] Optionally, the first plate and the second plate have the same thickness, and the thickness of the first plate is less than the thickness of the third plate.

[0020] Optionally, the third plate and the first active portion have the same material.

[0021] Optionally, the display panel comprises a non-display area arranged on at least one side of the display area, and the non-display area is provided with at least one second transistor.

[0022] The semiconductor layer further comprises a second active portion of the second transistor, and the mobility of the first active portion is less than or equal to the mobility of the second active portion.

[0023] Optionally, the display panel further comprises:

[0024] a first source-drain layer arranged on a side of the semiconductor layer away from the substrate, the first source-drain layer comprising a fourth plate arranged opposite to the third plate;

[0025] a second source-drain layer arranged on a side of the first source-drain layer away from the substrate, the second source-drain layer comprising a fifth plate arranged opposite to the fourth plate;

[0026] The first plate, the second plate, the third plate, the fourth plate and the fifth plate constitute a storage capacitor of the display panel.

[0027] Optionally, the display panel further comprises:

[0028] a passivation layer disposed between the first source-drain layer and the second source-drain layer, the passivation layer covering the first source-drain layer;

[0029] a first planar layer disposed on a side of the passivation layer away from the substrate, a portion of the second source-drain layer being in contact with a surface of the first planar layer on the side away from the substrate;

[0030] wherein a first opening is formed in the first planar layer, and the fifth plate is disposed in the first opening.

[0031] Optionally, the display panel further comprises:

[0032] a protective layer comprising a first portion located in the display area and a second portion located in the non-display area, the first portion being disposed on a surface of the first active portion on a side away from the substrate, and the second portion being disposed between the second active portion and the first transparent electrode layer;

[0033] wherein the mobility of the first active portion is less than the mobility of the second active portion.

[0034] The present application also provides a display device comprising the display panel.

[0035] Other features and advantages of the present application will be illustrated in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0037] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0038] Figure 1 a structural diagram of the display panel provided by the embodiments of the present application;

[0039] Figure 2 a first structural diagram of a cross section MM; Figure 1

[0040] Figure 3 a second structural diagram of the cross section MM; Figure 1 ​​

[0041] Figure 4 For Figure 1 The third structure diagram of the middle section MM;

[0042] Figure 5 For Figure 1 The fourth structure diagram of the middle section MM. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative effort belong to the protection scope of the present application.

[0044] Please refer to Figures 1 to 5 The present application provides a display panel 100, which comprises a substrate 10 and a first transparent electrode layer TS1, a second transparent electrode layer TS2 and a semiconductor layer AS arranged on the substrate 10.

[0045] In the embodiment, the first transparent electrode layer TS1 is arranged on one side of the substrate 10, the second transparent electrode layer TS2 is arranged on the side of the first transparent electrode layer TS1 away from the substrate 10, and the semiconductor layer AS is arranged on the side of the second transparent electrode layer TS2 away from the substrate 10.

[0046] In the embodiment, the first transparent electrode layer TS1 comprises a first plate C1, the second transparent electrode layer TS2 comprises a second plate C2, and the semiconductor layer AS comprises a third plate C3. The first plate C1, the second plate C2 and the third plate C3 all have overlapping parts, and the first plate C1, the second plate C2 and the third plate C3 constitute a storage capacitor Cst of the display panel 100.

[0047] The present application sets the first plate C1 and the second plate C2 between the substrate 10 and the semiconductor layer AS, and sets the third plate C3 by using the material of the semiconductor layer AS, so that the first plate C1, the second plate C2 and the third plate C3 constitute a capacitor structure arranged in parallel, the capacitance of the storage capacitor Cst is increased, the threshold voltage of the driving transistor is effectively compensated, and the display picture of the display panel 100 is improved.

[0048] The technical solutions of the present application will be described in combination with specific embodiments.

[0049] Please refer to Figure 1The display panel 100 includes a display area AA and a non-display area NA arranged adjacent to the display area AA. Optionally, the non-display area NA surrounds the display area AA, such that the display area AA is enclosed by the non-display area NA. The display area AA is an area in the display panel 100 for displaying, and is internally provided with a plurality of sub-pixels PX for displaying. The non-display area NA can be a frame area of the display panel 100, and can be internally provided with functional components for assisting the sub-pixels PX in the display area AA to display.

[0050] Referring to Figure 1 The lower side of the display area AA can be provided with a binding terminal PD, which can be connected with an external circuit. The binding terminal PD transmits signals input by the external circuit to the data lines, so as to drive the display panel 100 to display a picture. For example, the binding terminal PD can be connected with a chip or a chip on film, and is used to provide power supply and driving signals for the display panel 100.

[0051] Referring to Figures 2 to 5 The display panel 100 can include a substrate 10, an array layer 20 arranged on the substrate 10, a pixel layer 30 arranged on the array layer 20, a light-emitting functional layer 40, and an encapsulation layer 50.

[0052] In the embodiment, the material of the substrate 10 can be glass, quartz, polyimide, or the like. For example, when the display panel 100 is a flexible panel, the material of the substrate 10 can be a flexible material such as polyimide, or can be composed of a laminated film layer of a flexible material and an inorganic material. When the display panel 100 is a rigid panel, the material of the substrate 10 can be a rigid material such as glass or quartz.

[0053] Referring to Figures 2 to 5 The array layer 20 can include a plurality of thin film transistors, which can be etch-stop type, back channel etch type, or can be divided into bottom-gate thin film transistors, top-gate thin film transistors, or the like according to the positions of the gate and the semiconductor layer AS, and the specific structure is not limited.

[0054] In the embodiment, at least one first transistor T1 is arranged in the display area AA, and at least one second transistor T2 is arranged in the non-display area NA. Meanwhile, a pixel driving circuit and a storage capacitor Cst are arranged in the display area AA, the pixel driving circuit includes the first transistor T1, and a gate driving circuit is arranged in the non-display area NA, the gate driving circuit includes the second transistor T2.

[0055] It should be noted that, in order to simplify the process, the first transistor T1 and the second transistor T2 in the display area AA and the non-display area NA can be prepared at the same time.

[0056] For example, refer to the thin film transistor shown in Figures 2 to 5 The thin film transistor can be a top-gate thin film transistor, and the array layer 20 can include a first transparent electrode layer TS1 disposed on the substrate 10, a light shielding layer LS disposed on the first transparent electrode layer TS1, an interval layer IT disposed on the light shielding layer LS, a second transparent electrode layer TS2 disposed on the interval layer IT, a buffer layer 201 disposed on the second transparent electrode layer TS2, a semiconductor layer AS disposed on the buffer layer 201, a first gate insulating layer 202 disposed on the semiconductor layer AS, a gate electrode layer GE disposed on the first gate insulating layer 202, an interval insulating layer 203 disposed on the gate electrode layer GE, a first source / drain electrode layer SD1 disposed on the interval insulating layer 203, a passivation layer 204 disposed on the first source / drain electrode layer SD1, a first planarization layer 205 disposed on the passivation layer 204, a second source / drain electrode layer SD2 disposed on the first planarization layer 205, and a second planarization layer 206 disposed on the second source / drain electrode layer SD2.

[0057] It should be noted that the number of source / drain electrode layers can be set according to the wiring space requirement, for example, the source / drain electrode layer of the present application can be two layers; at the same time, the number of gate electrode layers GE is set according to the wiring space and capacitance requirement, for example, the gate electrode layer GE of the present application is one layer.

[0058] It should be noted that the interval layer IT, the buffer layer 201, the first gate insulating layer 202, the interval insulating layer 203, and the passivation layer 204 can all be inorganic materials composed of elements such as nitrogen, silicon, oxygen, and aluminum, for example, a single layer or a multi-layer inorganic film layer composed of one of silicon nitride, silicon oxide, and aluminum oxide.

[0059] It should be noted that the planarization layer of the present application is provided to ensure the flatness of the film layer, and the number of planarization layers is set according to the flatness requirement of the film layer, for example, the planarization layer of the present application can be two layers.

[0060] Please refer to Figures 2 to 5 The pixel layer 30 can include a first pixel definition layer 310 and a second pixel definition layer 320, the first pixel definition layer 310 is disposed on the side of the second planarization layer 206 away from the substrate 10, and the second pixel definition layer 320 is disposed on the surface of the first pixel definition layer 310 away from the substrate 10.

[0061] It should be noted that, since the light-emitting layer 402 of the present application is prepared by using the inkjet printing process, in order to reduce the precision of the inkjet printing, the first pixel definition layer 310 of the present application can include a plurality of first shielding strips staggered in the horizontal and vertical directions, and the plurality of first shielding strips staggered in the horizontal and vertical directions enclose a plurality of pixel openings corresponding to the sub-pixels. The second pixel definition layer 320 includes a plurality of second shielding strips in the horizontal or vertical direction, and the plurality of sub-pixels between any two adjacent second shielding strips are of the same color. In the inkjet printing process, the plurality of sub-pixels between any two adjacent second shielding strips can be printed simultaneously along the arrangement direction of the second shielding strips, thereby reducing the precision of the inkjet printing and improving the process efficiency.

[0062] It should be noted that the first pixel definition layer 310 and the second pixel definition layer 320 of the present application can be formed in one process, i.e., a film layer of the first pixel definition layer 310 and the second pixel definition layer 320 is formed at the same time, and the first pixel definition layer 310 and the second pixel definition layer 320 are patterned in the same mask, so that the first pixel definition layer 310 forms a plurality of first shielding strips, and the second pixel definition layer 320 forms a plurality of second shielding strips. For example, the present application can include a plurality of first shielding strips extending in the second direction and arranged in the first direction, and a plurality of second shielding strips extending in the first direction and arranged in the second direction.

[0063] In the present embodiment, since the second shielding strip mainly functions to isolate sub-pixels of different colors, the thickness of the second shielding strip of the present application can be greater than the thickness of the first shielding strip.

[0064] It should be noted that the display panel 100 further includes a support layer (not shown) integrally arranged with the pixel layer 30. The support layer is arranged on the surface of the second pixel definition layer 320 away from the first pixel definition layer 310, and the support layer and the pixel layer 30 can be formed in the same mask process. The support layer can be used to carry a mask plate.

[0065] It should be noted that the materials of the pixel layer 30 and the support layer can be organic positive photoresist.

[0066] Please refer to Figures 2 to 5 The light-emitting functional layer 40 can include an anode layer 401 arranged on the second planar layer, a light-emitting layer 402 arranged on the anode layer 401, and a cathode layer 403 arranged on the light-emitting layer 402. The anode layer 401 includes a plurality of anodes corresponding one-to-one to the pixel openings, and the light-emitting layer 402 can include a plurality of light-emitting pixels corresponding one-to-one to the plurality of anodes.

[0067] Please refer to Figures 2 to 5The encapsulation layer 50 covers the pixel layer 30 and continuously covers multiple pixel openings and multiple light-emitting pixels; the encapsulation layer 50 may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are stacked sequentially.

[0068] In this embodiment, the display panel may further include a color filter layer (not shown) disposed on the encapsulation layer 50 and a cover plate layer (not shown) disposed on the color filter layer. The color filter layer includes a plurality of color resists and light-shielding units disposed on both sides of the color resists, with one color resist corresponding to one light-emitting pixel. The cover plate layer is disposed on the side of the color filter layer away from the substrate 10. The cover plate layer may be a glass cover or formed directly on the color filter layer.

[0069] The following is a summary of this application. Figure 2 The structure of the middle array layer 20 is described in detail.

[0070] Please see Figure 2 The first transparent electrode layer TS1 is disposed on the surface of one side of the substrate 10, and the material of the first transparent electrode layer TS1 can be a transparent material such as indium tin oxide.

[0071] Please see Figure 2 The material of the light-shielding layer LS may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the light-shielding layer LS may be a stacked structure composed of a MoTi layer and a Cu layer.

[0072] In this embodiment, since the device effect of the transistor drifts under the action of light, the light-shielding layer LS can be provided between the transistor and the substrate 10 to block the active part in the transistor; and since a light-shielding structure is provided in the non-display area NA, external light cannot enter the area where the gate driving circuit is located, so the light-shielding layer LS can be located in the display area AA, and there is no need to provide a light-shielding layer LS in the non-display area NA.

[0073] In this embodiment, the first transparent electrode layer TS1 and the light-shielding layer LS can be fabricated in one photomask process, for example, using a halftone photomask to form the first transparent electrode layer TS1 with a first electrode plate C1 and a transparent portion TS1a spaced apart, and the light-shielding layer LS forms a light-shielding portion LS1 corresponding to the first transistor T1. The light-shielding portion LS1 and the transparent portion TS1a are formed in the same etching process. Therefore, the transparent portion TS1a and the light-shielding portion LS1 in this application have the same pattern.

[0074] In this embodiment, the thickness of the first transparent electrode layer TS1 can be in the range of 50nm to 100nm, for example, the thickness of the first transparent electrode layer TS1 can be 60nm.

[0075] Referring to Figure 2 The spacer layer IT covers the light shielding layer LS and the first transparent electrode layer TS1, and part of the spacer layer IT is in contact with the substrate 10, and the spacer layer IT is used to isolate the first transparent electrode layer TS1 and the light shielding layer LS from the upper conductive layer.

[0076] In this embodiment, the material of the spacer layer IT can be silicon oxide, and the thickness of the spacer layer IT can range from 100 nm to 200 nm, for example, the thickness of the spacer layer IT can be 130 nm.

[0077] Referring to Figure 2 The second transparent electrode layer TS2 is arranged on the surface of the spacer layer IT away from the substrate 10, and the second transparent electrode layer TS2 includes the second plate C2 of the storage capacitor Cst, and the second plate C2 is arranged opposite to the first plate C1.

[0078] In this embodiment, the material of the second transparent electrode layer TS2 can be transparent material such as indium tin oxide.

[0079] In this embodiment, the thickness of the second transparent electrode layer TS2 can range from 50 nm to 100 nm, for example, the thickness of the second transparent electrode layer TS2 can be equal to the thickness of the first transparent electrode layer TS1.

[0080] Referring to Figure 2 The buffer layer 201 covers the second transparent electrode layer TS2, and part of the buffer layer 201 is in contact with the surface of the spacer layer IT away from the substrate 10.

[0081] In this embodiment, the material of the buffer layer 201 is different from the material of the spacer layer IT, for example, the material of the buffer layer 201 of the present application can be a stacked structure of a silicon nitride layer and a silicon oxide layer.

[0082] In this embodiment, the thickness of the silicon nitride layer of the buffer layer 201 can range from 20 nm to 40 nm, and the thickness of the silicon oxide layer can range from 200 nm to 300 nm, for example, the thickness of the silicon nitride layer can be 30 nm, and the thickness of the silicon oxide layer can be 250 nm.

[0083] Referring to Figure 2The semiconductor layer AS is disposed on the side of the buffer layer 201 away from the substrate 10. The semiconductor layer AS can be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O, or other metal oxides. Figure 2 The semiconductor layer AS can be IGZO.

[0084] In this embodiment, the semiconductor layer AS includes a first active portion AS1 of the first transistor T1 and a second active portion AS2 of the second transistor T2. The first active portion AS1 and the second active portion AS2 can be made of the same material, i.e., the mobility of the first active portion AS1 can be equal to the mobility of the second active portion AS2.

[0085] In this embodiment, the first active portion AS1 and the second active portion AS2 are in contact with the buffer layer 201 on the side away from the gate electrode layer GE.

[0086] In this embodiment, the semiconductor layer AS can further include a third plate C3 corresponding to the second plate C2. The third plate C3 is in contact with the buffer layer 201 on the side away from the light shielding layer LS, and the third plate C3 is disposed opposite to the first plate C1. The second plate C2 is a capacitor plate of the storage capacitor Cst.

[0087] In this embodiment, the thickness of the third plate C3 can be less than the thickness of the first plate C1 and the second plate C2. For example, the thickness of the third plate C3 can be 30 nm.

[0088] Referring to Figure 2 The first gate insulating layer 202 includes a first sub-portion 202a and a second sub-portion 202b. The first sub-portion 202a is disposed on the side of the first active portion AS1 away from the substrate 10, and the second sub-portion 202b is disposed on the side of the second active portion AS2 away from the substrate 10. The first gate insulating layer 202 is used to insulate the semiconductor layer AS from the upper conductive layer.

[0089] Referring to Figure 2 The gate electrode layer GE includes a first gate electrode GE1 of the first transistor T1 and a second gate electrode GE2 of the second transistor T2. The first gate electrode GE1 is disposed on the side of the first sub-portion 202a away from the substrate 10, and the second gate electrode GE2 is disposed on the side of the second sub-portion 202b away from the substrate 10.

[0090] In the embodiment, the material of the gate electrode layer GE can include Cr, W, Ti, Ta, Mo, Al, Cu or other metal or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals; for example, the material of the first electrode layer 120 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0091] In the embodiment, the thickness of the gate electrode layer GE can range from 100 nm to 200 nm.

[0092] Referring to Figure 2 , the interlayer insulating layer 203 is arranged on the side of the gate electrode layer GE away from the substrate 10, the interlayer insulating layer 203 is uniformly laid, and the interlayer insulating layer 203 covers the gate insulating layer and is in contact with the buffer layer 201.

[0093] Referring to Figure 2 , the first source-drain layer SD1 includes the first source T1S and the first drain T1D of the first transistor T1 and the second source T2S and the second drain T2D of the second transistor T2, the first source T1S is connected through the first via hole HL1 and one end of the first active part AS1, the first drain T1D is connected through the second via hole HL2 and the other end of the first active part AS1, the second source T2S is connected through the third via hole HL3 and one end of the second active part AS2, and the second drain T2D is connected through the fourth via hole HL4 and the other end of the second active part AS2.

[0094] In the embodiment, the first source T1S is also electrically connected through the fifth via hole HL5 and the light shielding part LS1, so that the light shielding part LS1 is multiplexed as the bottom gate of the first transistor T1, and the turn-on rate of the first transistor T1 is improved.

[0095] In the embodiment, the material of the first source-drain layer SD1 can include Cr, W, Ti, Ta, Mo, Al, Cu or other metal or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals; for example, the first source-drain layer SD1 can be a laminated structure composed of a MoTi layer and a Cu layer, the thickness of the MoTi layer can range from 10 nm to 30 nm, and the thickness of the Cu layer can range from 400 nm to 600 nm, for example, the thickness of the MoTi layer can be 20 nm, and the thickness of the Cu layer can be 500 nm.

[0096] Referring to Figure 2The passivation layer 204 is disposed on the side of the first source-drain layer SD1 away from the substrate 10, the passivation layer 204 is fully laid, and the passivation layer 204 covers the first source-drain layer SD1 and is in contact with the interlayer insulation layer 203.

[0097] Referring to Figure 2 The first planarization layer 205 is disposed on the side of the passivation layer 204 away from the substrate 10, and the first planarization layer 205 covers part of the passivation layer 204.

[0098] In this embodiment, since the thickness of the first source-drain layer SD1 is relatively thick, there is a large step difference between the region where the first source-drain layer SD1 is disposed and the region where the first source-drain layer SD1 is not disposed, and the passivation layer 204 is an inorganic material with poor leveling property, so the flatness of the surface of the passivation layer 204 on the side away from the substrate 10 is poor; and the material of the first planarization layer 205 can be an organic material with good leveling property, such as polyimide, which improves the flatness of the surface of the film layer.

[0099] Referring to Figure 2 The second source-drain layer SD2 includes a first connection electrode CT1 located in the display area AA and a bus BS located in the non-display area NA, the first connection electrode CT1 is connected with the first source electrode T1S through the seventh via hole HL7, and the bus BS can be connected with the second gate electrode GE2, the second source electrode T2S or the second drain electrode T2D in the second transistor T2 through the eighth via hole HL8.

[0100] In this embodiment, the bus BS can include a high-potential line, a low-potential line, a data line, a clock signal line and the like; by disposing the bus BS on the side of the second transistor T2 away from the substrate 10, the application reduces the frame space occupied by the bus BS on the display panel 100, and realizes a narrow frame design.

[0101] In this embodiment, the material of the second source-drain layer SD2 can include Cr, W, Ti, Ta, Mo, Al, Cu and the like, or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals; for example, the first source-drain layer SD1 can be a laminated structure composed of a Ti layer, an Al layer and a Ti layer, the thickness of the Ti layer can range from 40 nm to 60 nm, and the thickness of the Al layer can range from 400 nm to 600 nm, for example, the thickness of the Ti layer can be 50 nm, and the thickness of the Al layer can be 500 nm.

[0102] In the embodiment, the first source-drain layer SD1 further comprises a second connection electrode CT2, one end of the second connection electrode CT2 is connected with the third plate C3 through a first contact hole HLa, and the other end of the second connection electrode CT2 is connected with the first plate C1 through a second contact hole HLb.

[0103] Referring to Figure 2 , the second planar layer 206 is arranged on the side of the second source-drain layer SD2 away from the substrate 10, and the material of the second planar layer 206 can be the same as that of the first planar layer 205, for example, the second planar layer 206 and the first planar layer 205 can both be made of a material with good flow planarity, such as polyimide.

[0104] In the embodiment, the material of the second planar layer 206 can be different from that of the first planar layer 205, for example, the photosensitivity of the second planar layer 206 can be greater than that of the first planar layer 205, that is, the second planar layer 206 has stronger photosensitivity, so that the time of the exposure process can be reduced and the efficiency of the exposure process can be improved when the second planar layer 206 is exposed.

[0105] Referring to Figure 2 , the anode layer 401 is arranged on the side of the second planar layer 206 away from the substrate 10, and the anode layer 401 is connected with the connection electrode CT through a tenth via hole HL10. The material of the anode layer 401 can include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0106] Referring to Figure 3 , the binding terminal PD can include a first terminal PD1 and a second terminal PD2, the first terminal PD1 can be prepared in the patterning process of the first source-drain layer SD1, the second terminal PD2 can be prepared in the patterning process of the second source-drain layer SD2, and the second terminal PD2 is electrically connected with the first terminal PD1 through an eleventh via hole HL11.

[0107] In the structure of Figure 3 , the application sets the first plate C1 and the second plate C2 between the substrate 10 and the semiconductor layer AS, and sets the third plate C3 by using the material of the semiconductor layer AS, so that the first plate C1, the second plate C2 and the third plate C3 form a parallel capacitor structure, the capacitance of the storage capacitor Cst is increased, the threshold voltage of the driving transistor is effectively compensated, and the display picture of the display panel 100 is improved.

[0108] Referring to Figure 1 , Figure 3 of the applicationFigure 2 the second structure diagram of the middle section MM, Figure 3 the structure in Figure 3 is the same or similar to the structure in

[0109] Please refer to Figure 3 , the material of the first active part AS1 is different from the material of the second active part AS2, and the mobility of the first active part AS1 is less than the mobility of the second active part AS2.

[0110] In the embodiment, the trend of narrow frame design of the display panel 100 is shown, the size of the frame of the display panel 100 is reduced, the driving current capability of the gate driving circuit needs to be improved to reduce the size of the driving circuit, and the driving current capability of the transistor in the gate driving circuit is improved by increasing the mobility of the second active part AS2 in the second transistor T2 in the application, the frame size of the non-display area NA is reduced, the narrow frame design is realized, and the driving stability of the non-display area NA can be ensured.

[0111] In the embodiment, the material of the first active part AS1 can be IGZO, and the material of the second active part AS2 can be IGZTO, IZO (InZnO) or InIZO.

[0112] In the embodiment, in order to differentiate the mobility of the first active part AS1 and the second active part AS2, the first active part AS1 and the second active part AS2 need to be prepared in two mask processes, and in order to affect the active part in the previous process by the subsequent process, the application can set a protective layer 207 between the two processes.

[0113] Please refer to Figure 4 , the protective layer 207 can include a first part 207a located in the display area AA and a second part 207b located in the non-display area NA, the first part 207a is arranged on the surface of the first active part AS1 away from the light shielding layer LS, and the second part 207b is arranged between the second active part AS2 and the buffer layer 201.

[0114] In the embodiment, the protective layer 207 can be laid in an integral layer, or only the second part 207b can be arranged in the structure shown in the figure. Figure 4 At the same time, the material of the protective layer 207 can be the same as the material of the first gate insulating layer 202.

[0115] This application improves the driving current capability of transistors in the gate drive circuit and reduces the bezel size of the non-display area NA by making the mobility of the second active part AS2 greater than that of the first active part AS1, thus achieving a narrow bezel design. At the same time, the protective layer 207 can protect the first active part AS1 and prevent the process of the second active part AS2 from affecting the first active part AS1.

[0116] Please see Figure 1 , Figure 4 For this application Figure 2 The third structural diagram of the mid-section MM. Figure 4 medium structure and Figure 4 The structures in the two are the same or similar, but the differences are:

[0117] Please see Figure 5 The first source-drain layer SD1 also includes a fourth plate C4 of the storage capacitor Cst. The fourth plate C4 is connected to the second plate C2 through a sixth via HL6. The third plate C3 is disposed opposite to the fourth plate C4.

[0118] In this embodiment, a first opening 205a is provided on the first flat layer 205.

[0119] In this embodiment, the second source-drain layer SD2 may further include the fifth electrode C5 of the storage capacitor Cst. The fifth electrode C5 may be located within the first opening 205a, that is, part of the second source-drain layer SD2 is in contact with the surface of the first planarization layer 205 away from the substrate 10. The fifth electrode C5 may pass through the ninth via HL9 and be connected to the second connecting electrode CT2. The fifth electrode C5 is disposed opposite to the fourth electrode C4.

[0120] In this embodiment, the depth of the first opening 205a can be less than or equal to the thickness of the first planarization layer 205. For example, in this application, the depth of the first opening 205a is equal to the thickness of the first planarization layer 205. The third electrode C3 contacts the passivation layer 204 in the first opening 205a. The arrangement of the first opening 205a reduces the distance between the fifth electrode C5 and the fourth electrode C4, thereby increasing the capacitance of the storage capacitor Cst.

[0121] exist Figure 5In this structure, the present application provides a first electrode C1 and a second electrode C2 between the substrate 10 and the semiconductor layer AS, a third electrode C3 is provided using the material of the semiconductor layer AS, a fourth electrode C4 is provided using the material of the first source-drain layer SD1, and a fifth electrode C5 is provided using the material of the second source-drain layer SD2. This allows the first electrode C1, the second electrode C2, the third electrode C3, the fourth electrode C4, and the fifth electrode C5 to form a capacitor structure connected in parallel, further increasing the capacitance of the storage capacitor Cst. This effectively compensates for the threshold voltage of the driving transistor and improves the display screen of the display panel 100.

[0122] Please see Figure 1 , Figure 5 For this application Figure 4 The third structural diagram of the mid-section MM. Figure 3 medium structure and Figure 5 The structures in the two are the same or similar, but the differences are:

[0123] and Figure 5 The structures are similar, the material of the first active part AS1 is different from the material of the second active part AS2, and the mobility of the first active part AS1 is less than the mobility of the second active part AS2.

[0124] In this embodiment, the material of the first active part AS1 can be IGZO, and the material of the second active part AS2 can be IGZTO, IZO (InZnO), or InIZO.

[0125] In this embodiment, to avoid interference between the first active part AS1 and the second active part AS2 during the manufacturing process, a protective layer 207 can be provided between the two processes. Please refer to [link to relevant documentation]. Figure 3 The protective layer 207 may include a first portion 207a located in the display area AA and a second portion 207b located in the non-display area NA. The first portion 207a is disposed on the surface of the first active part AS1 away from the light-shielding layer LS, and the second portion 207b is disposed between the second active part AS2 and the buffer layer 201.

[0126] In this embodiment, the protective layer 207 can be laid as a whole layer, or it can be only provided as an attachment. ​ and ​ In the structure shown; meanwhile, the material of the protective layer 207 can be the same as the material of the first gate insulating layer 202.

[0127] The application further provides a display device comprising the display panel.

[0128] The application provides a display panel and a display device.

[0129] In the description of the application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0130] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0131] The embodiments, implementation manners and related technical features of the application can be combined or replaced without conflict.

[0132] The above is only a preferred embodiment of the application, and does not limit the application in any form. Any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the application without departing from the technical solution of the application still falls within the scope of the technical solution of the application.

Claims

1. A display panel, characterized in that, include: Substrate; A first transparent electrode layer is disposed on one side of the substrate, and the first transparent electrode layer includes a first electrode plate; A second transparent electrode layer is disposed on the side of the first transparent electrode layer away from the substrate, and the second transparent electrode layer includes a second electrode plate; as well as A semiconductor layer is disposed on the side of the second transparent electrode layer away from the substrate, and the semiconductor layer includes a third electrode plate; The first electrode plate, the second electrode plate, and the third electrode plate all have overlapping portions, and the first electrode plate, the second electrode plate, and the third electrode plate constitute the storage capacitor of the display panel.

2. The display panel according to claim 1, characterized in that, The display panel further includes a light-shielding layer disposed between the first transparent electrode layer and the second transparent electrode layer, the semiconductor layer includes a first active portion located within the display area of ​​the display panel, and the light-shielding layer includes a light-shielding portion corresponding to the first active portion; The first transparent electrode layer further includes a transparent portion spaced apart from the first electrode plate, and the light-shielding portion is disposed on the surface of the transparent portion away from the substrate, and the light-shielding portion and the transparent portion have the same pattern.

3. The display panel according to claim 2, characterized in that, The distance between the first electrode plate and the second electrode plate is smaller than the distance between the second electrode plate and the third electrode plate.

4. The display panel according to claim 2, characterized in that, The display panel also includes: A spacer layer is disposed on the side of the light-shielding layer away from the substrate, the spacer layer covers the light-shielding layer and the first transparent electrode layer, and a portion of the spacer layer is in contact with the substrate. A buffer layer is disposed on the side of the second transparent electrode layer away from the substrate, the buffer layer covers the second transparent electrode layer, and a portion of the buffer layer is in contact with the spacer layer; The materials of the spacer layer and the buffer layer are different.

5. The display panel according to claim 2, characterized in that, The thickness of the first electrode plate is the same as the thickness of the second electrode plate, and the thickness of the first electrode plate is less than the thickness of the third electrode plate.

6. The display panel according to claim 2, characterized in that, The material of the third electrode plate is the same as the material of the first active part.

7. The display panel according to any one of claims 2 to 6, characterized in that, The display panel includes a non-display area disposed on at least one side of the display area, and at least one second transistor is disposed in the non-display area; The semiconductor layer further includes a second active portion of the second transistor, wherein the mobility of the first active portion is less than or equal to the mobility of the second active portion.

8. The display panel according to claim 7, characterized in that, The display panel also includes: A first source-drain layer is disposed on the side of the semiconductor layer away from the substrate, and the first source-drain layer includes a fourth electrode plate disposed opposite to the third electrode plate; The second source-drain layer is disposed on the side of the first source-drain layer away from the substrate, and the second source-drain layer includes a fifth electrode plate disposed opposite to the fourth electrode plate; The first electrode plate, the second electrode plate, the third electrode plate, the fourth electrode plate, and the fifth electrode plate constitute the storage capacitor of the display panel.

9. The display panel according to claim 8, characterized in that, The display panel also includes: A passivation layer is disposed between the first source / drain layer and the second source / drain layer, and the passivation layer covers the first source / drain layer; A first planarization layer is disposed on the side of the passivation layer away from the substrate, and a portion of the second source / drain electrode is in contact with the surface of the first planarization layer away from the substrate. The first flat layer has a first opening, and the fifth electrode plate is disposed in the first opening.

10. The display panel according to claim 7, characterized in that, The display panel also includes: The protective layer includes a first portion located in the display area and a second portion located in the non-display area. The first portion is disposed on the surface of the first active portion away from the substrate, and the second portion is disposed between the second active portion and the first transparent electrode layer. The mobility of the first active part is less than that of the second active part.

11. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 10.

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