Mainboard compatible with single-layer and double-layer structures

Abstract

The utility model provides a mainboard compatible with a single-layer and double-layer structure, and belongs to the technical field of electronic circuits. Comprising a mainboard; the power supply management chip is connected to the mainboard, and the power supply management chip is used for receiving external power supply input; and the I / O chip is connected to the mainboard, an input pin of the I / O chip is connected with an output pin of the power management chip, and the I / O chip is used for processing signal interaction. According to the utility model, through the power supply management chip, the first chip resistor, the power supply filter circuit, the first ceramic capacitor and the like, the purposes of providing a stable and adaptive power supply for a single-layer and double-layer structure and accurately converting and transmitting signals between the single-layer and double-layer structure are achieved; and through mutual cooperation among the USB interface, the I / O chip, the second chip resistor, the self-recovery fuse and the second ceramic capacitor, the purpose that the USB interface is stably compatible with various external USB devices is achieved.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic circuit technical field, especially a kind of mainboard compatible with single double-layer structure. BACKGROUND

[0002] With the rapid development of electronic technology, electronic equipment has been significantly improved in function and performance. Among many electronic devices, the mainboard as the core component carries various circuit elements and chips, and its rationality and compatibility of design play a crucial role in the overall performance of the device. From simple consumer electronics to complex industrial control devices, the mainboard needs to meet the integration needs of different functional modules, while ensuring the collaborative work between modules.

[0003] However, in some complex electronic device mainboard designs, there may be modules with both double-layer structure and single-layer structure. Double-layer structure modules usually have higher integration and functional complexity, for example, they may integrate advanced FPGA chips, etc., which require precise power supply and complex signal transmission mechanisms. While single-layer structure modules may be relatively simple, but have their own characteristics in terms of signal type and voltage requirements. Current mainboard designs often lack effective compatibility design when dealing with such single and double-layer structure coexistence. In terms of power supply, there is no suitable power management mechanism to provide stable and adaptive voltage for single and double-layer structures, which can easily cause some modules to malfunction due to excessive or insufficient voltage. In terms of signal transmission, due to the differences in signal format and level standards between double-layer structure and single-layer structure, there is a lack of reliable signal conversion and buffering mechanism, which can cause signal incompatibility problems such as signal loss, error code, etc., seriously affecting the stability and reliability of the entire electronic device. SUMMARY

[0004] The technical problem to be solved by the utility model is to provide a mainboard compatible with single and double-layer structures to solve the technical problems of single and double-layer structure compatibility and interface compatibility in the prior art.

[0005] Technical scheme: To achieve the above object, the utility model discloses a kind of mainboard compatible with single double-layer structure, comprising: mainboard;Power management chip, connect on mainboard, the power management chip is used to receive external power input;I / O chip, connect on mainboard, the I / O chip input pin is connected with power management chip output pin, and the I / O chip is used to process signal interaction;Double-layer structure, set on mainboard, the double-layer structure is connected with the output pin of power management chip, and the double-layer structure is connected with I / O chip signal;Single-layer structure, set on mainboard, the single-layer structure is connected with the output pin of power management chip, and the single-layer structure is connected with I / O chip signal;The power management chip is used to ensure that stable, adaptive power supply is provided for double-layer structure and single-layer structure, and the I / O chip is used to build reliable signal bridge between double-layer structure and single-layer structure, to overcome the signal incompatibility of the two due to structural difference, wherein the mainboard is manufactured using multilayer printed circuit board (PCB) process, its layer number is not less than 4, and has good electrical insulation performance and mechanical strength.Power management chip uses chip model with multiple output and adjustable voltage function, and its output voltage precision is within ±2%.I / O chip needs to support at least two different signal standards, including but not limited to LVDS (low voltage differential signal) and TTL (transistor-transistor logic level), and its signal processing frequency range is not less than 100MHz.Double-layer structure and single-layer structure on the layout of mainboard are optimized and designed to reduce electromagnetic interference and signal crosstalk, and the connection pin of the two with power management chip and I / O chip uses gold plating process, to improve the reliability and conductivity of connection.

[0006] In further embodiment, power input interface is set on mainboard, the power input interface is connected with the input pin of power management chip in series, and the power input interface is used to connect external DC power supply, wherein external DC power supply can be in various forms, such as stable DC voltage provided by power adapter, or DC output by battery pack, and through this interface, electrical energy is introduced into mainboard, to power subsequent circuit and element.

[0007] In a further embodiment, a first chip resistor is connected in series between the power input interface and the input pin of the power management chip, and is used for current limiting to prevent excessive instantaneous current from impacting the power management chip; a power filter circuit is connected in parallel between the power input interface and the input pin of the power management chip, and is used for filtering high-frequency and low-frequency noise in the power input, wherein the first chip resistor has a resistance value in the range of 10Ω-100Ω, a power not less than 0.25W, and is made of a high-precision, low-temperature-drift metal film first chip resistor. The capacitor in the power filter circuit has a total capacitance in the range of 10μF-100μF and an inductance in the range of 10μH-100μH, and the filter circuit has an attenuation capability of at least 40dB for noise in the frequency range of 10kHz-1MHz.

[0008] In a further embodiment, a plurality of first ceramic capacitors are connected in parallel between the power input line between the I / O chip and the power management chip, and are used for filtering high-frequency noise on the power line, wherein the first ceramic capacitors can be multi-layer first ceramic capacitors (MLCC) with a capacitance in the range of 0.01μF-0.1μF and a withstand voltage not less than 16V. This type of capacitor has good high-frequency characteristics and can effectively filter high-frequency noise above 1MHz.

[0009] In a further embodiment, a USB interface is provided on the mainboard, the D+ and D- pins of the USB interface are connected to the D+ and D- pins of the I / O chip respectively, the GND pin of the USB interface is connected to the ground plane of the mainboard through a via, and the VCC pin of the USB interface is connected to the power input line between the I / O chip and the power management chip. The USB interface is used for connecting external USB devices, wherein the USB interface can be a standard USB Type-A interface or other type of interface compatible with USB2.0 and above standards, the characteristic impedance of the data transmission line (D+ and D- pins) is 90Ω±15%, the output voltage of the VCC pin of the USB interface is 5V±0.25V, and the maximum output current is 500mA; the diameter of the via is in the range of 0.3mm-0.5mm, and the inner wall of the via is plated with copper to reduce the first chip resistance of the via.

[0010] In a further embodiment, a second patch resistor is connected in series on the connection line between the D+ and D- pins on the USB interface and the D+ and D- pins on the I / O chip, the second patch resistor being used for impedance matching to ensure the integrity of the USB signal during transmission; a self-recovery fuse is connected in series on the connection line between the VCC pin on the USB interface and the power input line, the self-recovery fuse being used to prevent overloading or short circuit of the USB interface circuit; a second ceramic capacitor has one end connected to the VCC pin on the USB interface and the other end grounded, the second ceramic capacitor being used for decoupling filtering of the power supply of the USB interface, wherein the resistance of the second patch resistor can be 22Ω±5%, the rated power can be 0.125W, and the 0603 or 0805 package can be used. The rated current of the self-recovery fuse can be 1A, the operating current can be 1.5A, the maximum voltage resistance can be 60V, and the recovery time can be between 1 second and 10 seconds. The second ceramic capacitor can use a tantalum capacitor with a capacitance of 10μF and a voltage resistance of 16V.

[0011] In a further embodiment, the double-layer structure includes an upper layer circuit and a lower layer circuit, the upper layer circuit is provided with an FPGA chip, and the lower layer circuit is provided with an Ethernet PHY chip, the double-layer structure is also provided with a power supply layer and a ground layer, the power supply layer provides stable working voltage for the FPGA chip and the Ethernet PHY chip through internal wiring, and the ground layer provides a reference potential for signal transmission and reduces electromagnetic interference, wherein the FPGA chip can use a medium-high end model produced by a well-known manufacturer such as Xilinx or Altera, the number of logic units is not less than 10,000, and the working frequency is not less than 100MHz. The Ethernet PHY chip supports 10 / 100 / 1000Mbps Ethernet standard, and the connection with the RJ45 interface meets the IEEE802.3 standard. The power supply layer adopts a multi-layer plane design and can provide two stable voltages of 3.3V and 1.8V, and the voltage adjustment rate is within ±1%. The ground layer is connected to the ground plane of the mainboard through a plurality of vias, the via spacing is not greater than 5mm, to ensure good grounding effect.

[0012] In a further embodiment, the output pins of the FPGA chip and the input pins of the Ethernet PHY chip are connected in the form of microstrip line and via, and the output pins of the FPGA chip and the input pins of the Ethernet PHY chip are connected to the power supply layer and the ground layer in the form of microstrip line and via to ensure the stability of the reference potential during signal transmission, wherein the line width of the microstrip line can be between 0.15mm and 0.25mm, the dielectric thickness can be 0.1mm-0.2mm, and the characteristic impedance can be 50Ω±5%. The diameter of the via can be 0.2mm-0.3mm, the via wall can use a copper plating process, the parasitic capacitance is less than 0.5pF, and the parasitic inductance is less than 1nH.

[0013] In a further embodiment, the single-layer structure comprises a TL082 operational amplifier, a plurality of resistors, a plurality of capacitors and a potentiometer, the plurality of resistors comprising a first resistor (R3), a second resistor (R4) and a third resistor (R5), the plurality of capacitors comprising a first capacitor (C5) and a second capacitor (C6), the non-inverting input pin of the TL082 operational amplifier being connected in series with the first resistor, the connection line between the non-inverting input pin and the first resistor being connected in parallel with the first capacitor, one end of the first capacitor being connected to the connection line between the non-inverting input pin and the first resistor and the other end being grounded, wherein the bandwidth of the TL082 operational amplifier should be not less than 3MHz, the offset voltage is less than 5mV, and the input bias current is less than 200nA. The resistance of the first resistor is between 1kΩ and 10kΩ, and the capacitance of the first capacitor is between 0.01μF and 0.1μF, and high-precision and low-temperature coefficient components are used.

[0014] In a further embodiment, the inverting input pin of the TL082 operational amplifier is connected in series with the second resistor, the second resistor is connected in series with the fixed end of the potentiometer, the other fixed end of the potentiometer is grounded, the sliding end of the potentiometer is connected in series with the first capacitor, the first capacitor is connected in series with the third resistor, and the third resistor is connected in series with the output end of the TL082 operational amplifier, wherein the resistance of the second resistor can be between 1kΩ and 10kΩ, and the resistance of the third resistor can be between 10kΩ and 100kΩ. The resistance of the potentiometer can be in the range of 10kΩ to 100kΩ, the linearity is not less than 0.5%, and the resolution is not less than 10%. The capacitance of the first capacitor can be between 0.01μF and 0.1μF, and all components need to meet the performance stability requirements under the industrial temperature range (-40℃ to 85℃).

[0015] Beneficial effects: 1. Through the cooperation among the power management chip, the first patch resistor, the power filter circuit, the first ceramic capacitor, the power wiring on the mainboard for single and double layer structure, the I / O chip, the FPGA chip and the Ethernet PHY chip in the double layer structure, the TL082 operational amplifier and the related first patch resistor, capacitor and potentiometer in the single layer structure, the purpose of providing stable and adaptive power supply for each module in the single and double layer structure and accurately converting and transmitting signals between the double layer structure and the single layer structure is realized; wherein the power management chip outputs corresponding voltage according to the voltage demand of different structures, the first patch resistor limits the instantaneous large current to protect the power management chip, the power filter circuit and the first ceramic capacitor filter out power clutter; the I / O chip processes signals of different formats and levels, and the mainboard wiring provides a stable channel for signal transmission; the effect of ensuring that the FPGA chip, the Ethernet PHY chip in the double layer structure and the TL082 operational amplifier and other elements in the single layer structure can work stably under appropriate voltage, avoiding damage or performance reduction of elements caused by voltage fluctuation, reducing signal loss, error code and other phenomena, ensuring accurate and reliable communication between elements in the double layer structure and the single layer structure, and improving the stability of the whole system is achieved.

[0016] 2. Through the cooperation among the USB interface, the I / O chip, the second patch resistor, the self-recovery fuse and the second ceramic capacitor, the purpose of making the USB interface compatible with a variety of external USB devices is realized; the USB interface is connected with the I / O chip to realize data transmission, the second patch resistor performs impedance matching to ensure the integrity of the USB signal, the self-recovery fuse prevents overload short circuit, and the second ceramic capacitor decouples and filters the power supply; the effect of expanding the function and application range of the mainboard is achieved, no matter whether the low-speed mouse, keyboard or high-speed USB device such as U disk and mobile hard disk can be stably connected with the mainboard and communicate normally. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0018] Fig. 1 The overall circuit diagram of the present application.

[0019] Fig. 2 The circuit diagram of the double layer structure.

[0020] Fig. 3 The circuit diagram of the single layer structure.

[0021] The reference signs in the figure are: 1, mainboard; 2, power input interface; 3, first patch resistor; 4, power management chip; 5, power filter circuit; 6, first ceramic capacitor; 7, I / O chip; 8, USB interface; 9, second patch resistor; 10, self-recovery fuse; 11, second ceramic capacitor; 12, double-layer structure; 13, single-layer structure. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the utility model clearer, the technical scheme in the utility model is described clearly and completely, obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by the person skilled in the art without creative labor belong to the protection scope of the utility model.

[0023] The utility model discloses a kind of mainboard compatible with single double-layer structure, solve the technical problem of single double-layer structure compatibility and interface compatibility in prior art.In actual use, it realizes the good compatibility of single double-layer structure on power supply, signal transmission, simultaneously realizes the stable, compatible connection purpose of multiple interfaces (especially USB interface) with external device.

[0024] In order to better understand the above technical scheme, the above technical scheme will be described in detail in the description of the drawings and specific embodiments.

[0025] REFERENCE Figs. 1-3 A kind of mainboard compatible with single double-layer structure, including: mainboard 1;Power management chip 4, connect on mainboard 1, the power management chip 4 is used to receive external power input;I / O chip 7, connect on mainboard 1, the input pin of I / O chip 7 is connected with the output pin of power management chip 4, the I / O chip 7 is used to process signal interaction;Double-layer structure 12, it is set on mainboard 1, the double-layer structure 12 is connected with the output pin of power management chip 4, the double-layer structure 12 is connected with I / O chip 7 signal;Single-layer structure 13, it is set on mainboard 1, the single-layer structure 13 is connected with the output pin of power management chip 4, the single-layer structure 13 is connected with I / O chip 7 signal;The power management chip 4 is used to ensure that stable, adaptive power supply is provided for double-layer structure 12 and single-layer structure 13, the I / O chip 7 is used to build reliable signal bridge between double-layer structure 12 and single-layer structure 13, to overcome the signal incompatibility of both due to structural difference.

[0026] The power management chip 4 ensures that the double-layer structure 12 and the single-layer structure 13 can obtain stable and adaptive power supply, so that the elements in each structure can work normally and avoid faults caused by power supply problems. The I / O chip 7 builds a signal bridge between the double-layer structure 12 and the single-layer structure 13, overcomes the signal incompatibility problem caused by structural differences, ensures the accurate interaction of signals between different structures, and ensures smooth communication of the entire system.

[0027] The power input interface 2 is arranged on the mainboard 1, the power input interface 2 is connected in series with the input pin of the power management chip 4, and the power input interface 2 is used to connect an external DC power supply.

[0028] By connecting the power input interface 2 and the input pin of the power management chip 4 in series, the function of introducing the external DC power supply into the mainboard 1 is realized, an interface path is provided for the power supply of the entire mainboard 1 system, the external power supply can be smoothly connected, and the power supply of the subsequent circuit is ensured.

[0029] The first patch resistor 3 is connected in series between the power input interface 2 and the input pin of the power management chip 4, and the first patch resistor 3 is used for current limiting to prevent excessive instantaneous current from impacting the power management chip 4; and the power filter circuit 5 is connected in parallel between the power input interface 2 and the input pin of the power management chip 4, and the power filter circuit 5 is used to filter high-frequency and low-frequency noise in the power input.

[0030] The first patch resistor 3 is connected in series between the power input interface 2 and the power management chip 4, which realizes the limiting effect of instantaneous large current, effectively protects the power management chip 4 from excessive current impact, and improves the working safety and stability of the power management chip 4; and the power filter circuit 5 is connected in parallel between the corresponding pins, which realizes the filtering effect of high-frequency and low-frequency noise in the power input, provides clean and stable power supply for the power management chip 4, and reduces the interference of noise on the chip C37I / O and the subsequent circuit.

[0031] A plurality of first ceramic capacitors 6 are provided, and the plurality of first ceramic capacitors 6 are all connected in parallel on the power input line between the I / O chip 7 and the power management chip 4, and the first ceramic capacitors 6 are used to filter high-frequency noise on the power line.

[0032] The plurality of first ceramic capacitors 6 are connected in parallel on the power input line between the I / O chip 7 and the power management chip 4, which realizes the effect of filtering high-frequency noise on the power line, makes the power supply more pure, reduces the influence of high-frequency noise on the working of the I / O chip 7 and the power management chip 4, and improves the stability of signal processing and power supply.

[0033] The USB interface 8 is arranged on the mainboard 1, the D+ and D- pins of the USB interface 8 are connected with the D+ and D- pins of the I / O chip 7 respectively, the GND pin of the USB interface 8 is connected with the ground plane of the mainboard 1 through a via hole, the VCC pin of the USB interface 8 is connected with the power input line between the I / O chip 7 and the power management chip 4, and the USB interface 8 is used for connecting external USB devices.

[0034] The arrangement of the USB interface 8 on the mainboard 1 and the connection with the I / O chip 7 and the power input line realize the function of connecting external USB devices, provide a physical interface for data transmission and power supply between the external USB devices and the mainboard 1, and expand the function extension and compatibility of the mainboard 1.

[0035] The second chip resistor 9 is connected in series on the connection line between the D+ and D- pins of the USB interface 8 and the D+ and D- pins of the I / O chip 7, the second chip resistor 9 is used for impedance matching to ensure the integrity of the USB signal in the transmission process; the self-restoring fuse 10 is connected in series on the connection line between the VCC pin of the USB interface 8 and the power input line, the self-restoring fuse 10 is used for preventing the USB interface 8 circuit from overloading or short circuit; and the second ceramic capacitor 11 is connected with the VCC pin of the USB interface 8 at one end and grounded at the other end, the second ceramic capacitor 11 is used for decoupling filtering of the power supply of the USB interface 8.

[0036] The second chip resistor 9 is connected in series on the connection line between the USB interface 8 and the I / O chip 7, realizes the impedance matching effect of the USB signal transmission line, guarantees the integrity of the USB signal in the transmission process, reduces signal reflection and distortion, and ensures accurate USB data transmission; the self-restoring fuse 10 is connected in series between the VCC pin of the USB interface 8 and the power input line, realizes the effect of preventing the USB interface 8 circuit from overloading or short circuit, automatically cuts off the circuit when an abnormal condition occurs, and automatically recovers after troubleshooting, improves the safety and reliability of the USB interface 8 circuit; and the second ceramic capacitor 11 is connected with the VCC pin of the USB interface 8 at one end and grounded at the other end, realizes the decoupling filtering effect of the power supply of the USB interface 8, reduces the influence of power fluctuation on the USB interface 8, and makes the power supply of the USB interface 8 more stable.

[0037] The double-layer structure 12 includes an upper layer circuit and a lower layer circuit, the FPGA chip is arranged in the upper layer circuit, the Ethernet PHY chip is arranged in the lower layer circuit, the double-layer structure 12 further includes a power supply layer and a ground layer, the power supply layer provides stable working voltage for the FPGA chip and the Ethernet PHY chip through internal wiring, and the ground layer provides a reference potential for signal transmission and reduces electromagnetic interference.

[0038] In the double-layer structure 12, through the setting of the FPGA chip of the upper-layer circuit, the Ethernet PHY chip of the lower-layer circuit, the power supply layer and the ground layer, the power supply layer provides stable working voltage for the FPGA chip and the Ethernet PHY chip, which guarantees the normal work of the two key chips C37I / O; the ground layer provides reference potential for signal transmission and reduces electromagnetic interference, which improves the quality and stability of signal transmission in the double-layer structure 12 and is conducive to the communication between the FPGA chip and the Ethernet PHY chip.

[0039] The output pin of the FPGA chip and the input pin of the Ethernet PHY chip C37I / O are connected in the form of microstrip line and via, and the output pin of the FPGA chip and the input pin of the Ethernet PHY chip C37I / O are connected to the power supply layer and the ground layer in the form of microstrip line and via, so as to guarantee the stability of the reference potential in the signal transmission process.

[0040] The output pin and the input pin of the FPGA chip and the Ethernet PHY chip are connected in the form of microstrip line and via, and are connected to the power supply layer and the ground layer, which realizes the effect of guaranteeing the stability of the reference potential in the signal transmission process, reduces signal jitter and noise, and ensures the accuracy and reliability of high-speed signal transmission between the FPGA chip and the Ethernet PHY chip.

[0041] The single-layer structure 13 includes a TL082 operational amplifier, a plurality of resistors, a plurality of capacitors and a potentiometer, the plurality of resistors include a first resistor, a second resistor and a third resistor, the plurality of capacitors include a first capacitor and a second capacitor, the first resistor is connected in series to the non-inverting input pin of the TL082 operational amplifier, the first capacitor is connected in parallel to the connection line between the non-inverting input pin and the first resistor, one end of the first capacitor is connected to the connection line between the non-inverting input pin and the first resistor, and the other end is grounded.

[0042] In the single-layer structure 13, through the connection of the TL082 operational amplifier with the first resistor, the first capacitor and other elements, a specific circuit structure is formed. The connection mode of the first capacitor and the first resistor at the non-inverting input pin (+) realizes the preliminary processing effect of the input signal, for example, it can realize the filtering of high-frequency noise or the adjustment of the phase of the input signal, which provides a better input signal for the subsequent signal processing of the operational amplifier.

[0043] The non-inverting input pin (-) of the TL082 operational amplifier is connected in series with the second resistor, the second resistor is connected in series with the fixed end of the potentiometer, the other fixed end of the potentiometer is grounded, the sliding end of the potentiometer is connected in series with the first capacitor, the first capacitor is connected in series with the third resistor, and the third resistor is connected in series with the output end of the TL082 operational amplifier.

[0044] The TL082 operational amplifier is connected with the second resistor, the potentiometer, the first capacitor, the third resistor and the like elements at the inverting input pin and the output end, realizes the effect of constructing a variable gain inverting amplifier, the gain of the amplifier can be changed through the adjustment of the potentiometer, so that the amplification times of the input signal between-1 to-10 are realized, and different signal processing requirements are met.

[0045] In use, the external DC power supply is connected to the mainboard 1 through the power input interface 2, the power input interface 2 is connected in series with the input pin of the power management chip 4, at this time, the first SMD resistor 3 connected in series between them limits the possible excessive instantaneous current, prevents the impact on the power management chip 4, and the power filter circuit 5 connected in parallel between the power input interface 2 and the input pin of the power management chip 4 filters out high and low frequency noise in the power input; the power management chip 4 receives the processed power supply, and then outputs stable and adaptive voltage according to the different needs of the double-layer structure 12 and the single-layer structure 13 to supply power for them; in terms of signal processing, the I / O chip 7 obtains power from the power management chip 4, the input pin of which is connected with the output pin of the power management chip 4; the double-layer structure 12 and the single-layer structure 13 are connected with the output pin of the power management chip 4 to obtain power and are connected with the I / O chip 7 for signal connection; the I / O chip 7 interacts and processes the signals between the double-layer structure 12 and the single-layer structure 13, overcoming the signal incompatibility problem caused by the structural difference between them; when a USB device is connected to the USB interface 8, the D+ and D- pins of the USB interface 8 are connected with the D+ and D- pins of the I / O chip 7 respectively for data transmission, the GND pin is connected with the ground plane of the mainboard 1 through a via, and the VCC pin is connected with the power input line between the I / O chip 7 and the power management chip 4 to obtain power; the second SMD resistor 9 connected in series on the connection line between the D+ and D- pins of the USB interface 8 and the D+ and D- pins of the I / O chip 7 performs impedance matching, ensuring the integrity of the USB signal in the transmission process, the self-resetting fuse 10 connected in series between the VCC pin of the USB interface 8 and the power input line prevents the USB interface 8 circuit from overloading or short circuiting, the second ceramic capacitor 11 with one end connected with the VCC pin of the USB interface 8 and the other end grounded decouples and filters the power of the USB interface 8; in the double-layer structure 12, the power layer provides stable working voltage for the FPGA chip in the upper layer circuit and the Ethernet PHY chip in the lower layer circuit through internal wiring, the output pin of the FPGA chip is connected with the input pin of the Ethernet PHY chip in the form of microstrip line and via, and the pins of them are connected with the power layer and the ground layer in the form of microstrip line and via, ensuring the stability of the reference potential in the signal transmission process, and the ground layer provides reference potential for signal transmission and reduces electromagnetic interference; in the single-layer structure 13, a first resistor is connected in series with the non-inverting input pin of the TL082 operational amplifier, a first capacitor is connected in parallel on the connection line between the non-inverting input pin and the first resistor, one end of the first capacitor is connected with the connection line between the non-inverting input pin and the first resistor, and the other end is grounded, for processing the input signal;The inverting input pin of the TL082 operational amplifier is connected with the second resistor in series, the second resistor is connected with the fixed end of the potentiometer in series, the other fixed end of the potentiometer is grounded, the sliding end of the potentiometer is connected with the first capacitor in series, the first capacitor is connected with the third resistor in series, the third resistor is connected with the output end of the TL082 operational amplifier in series, and the variable gain inverting amplification function of the input signal is realized.

[0046] The figures in the drawings are example figures, and the purpose is only to more intuitively show the key structure and connection relationship of the main board compatible with single and double-layer structures of the utility model; in actual application, the appearance and size of the device can be adjusted and optimized according to specific requirements.

[0047] The utility model covers any alternative, modification, equivalent method and scheme made on the essence and range of the utility model. In order to enable the public to have a thorough understanding of the utility model, the specific details are explained in the above preferred embodiment of the utility model, and the utility model can also be completely understood without the description of these details for the person skilled in the art. In addition, in order to avoid unnecessary confusion to the essence of the utility model, well-known methods, processes, flows, elements and circuits are not explained in detail.

[0048] The above is only the preferred embodiment of the utility model, and it should be pointed out that, for the ordinary skilled person in the art, on the premise of not departing from the principle of the utility model, a plurality of improvements and refinements can also be made, and these improvements and refinements should also be regarded as the protection range of the utility model.

Claims

1. A motherboard compatible with single and dual-layer structures, characterized in that, include: Motherboard (1); A power management chip (4) is connected to the motherboard (1) and is used to receive external power input. I / O chip (7) is connected to the motherboard (1). The input pin of the I / O chip (7) is connected to the output pin of the power management chip (4). The I / O chip (7) is used to process signal interaction. A dual-layer structure (12) is set on the motherboard (1). The dual-layer structure (12) is connected to the output pin of the power management chip (4) and the dual-layer structure (12) is connected to the I / O chip (7) for signal connection. A single-layer structure (13) is set on the motherboard (1). The single-layer structure (13) is connected to the output pin of the power management chip (4) and the single-layer structure (13) is connected to the I / O chip (7) for signal connection. The power management chip (4) is used to ensure a stable and compatible power supply for the dual-layer structure (12) and the single-layer structure (13). The I / O chip (7) is used to build a reliable signal bridge between the dual-layer structure (12) and the single-layer structure (13) to overcome the signal incompatibility caused by the structural differences between the two.

2. A motherboard compatible with single and double layer structures according to claim 1, characterized in that, Also includes: The power input interface (2) is located on the motherboard (1). The power input interface (2) is connected in series with the input pin of the power management chip (4). The power input interface (2) is used to connect to an external DC power supply.

3. A motherboard compatible with single and double layer structures according to claim 2, characterized in that, Also includes: The first surface mount resistor (3) is connected in series between the power input interface (2) and the input pin of the power management chip (4). The first surface mount resistor (3) is used to limit current to prevent excessive instantaneous current from impacting the power management chip (4). A power filter circuit (5) is connected in parallel between the power input interface (2) and the input pin of the power management chip (4). The power filter circuit (5) is used to filter out high-frequency and low-frequency noise in the power input.

4. A motherboard compatible with single and double layer structures according to claim 1, characterized in that, Also includes: Multiple first ceramic capacitors (6) are provided, and multiple first ceramic capacitors (6) are connected in parallel on the power input line between the I / O chip (7) and the power management chip (4). The first ceramic capacitors (6) are used to filter out high-frequency noise on the power line.

5. A motherboard compatible with single and double layer structures according to claim 1, characterized in that, Also includes: The USB interface (8) is located on the motherboard (1). The D+ and D- pins on the USB interface (8) are connected to the D+ and D- pins on the I / O chip (7) respectively. The GND pin on the USB interface (8) is connected to the ground plane on the motherboard (1) through a via. The VCC pin on the USB interface (8) is connected to the power input line between the I / O chip (7) and the power management chip (4). The USB interface (8) is used to connect external USB devices.

6. A motherboard compatible with single and double layer structures according to claim 5, characterized in that, Also includes: The second surface mount resistor (9) is connected in series on the connection line between the D+ and D- pins of the USB interface (8) and the D+ and D- pins of the I / O chip (7). The second surface mount resistor (9) is used for impedance matching to ensure the integrity of the USB signal during transmission. A resettable fuse (10) is connected in series on the connection line between the VCC pin and the power input line of the USB interface (8). The resettable fuse (10) is used to prevent overload or short circuit in the USB interface (8) circuit. The second ceramic capacitor (11) is connected at one end to the VCC pin on the USB interface (8) and at the other end to ground. The second ceramic capacitor (11) is used to decouple and filter the power supply of the USB interface (8).

7. A motherboard compatible with single and double layer structures according to claim 1, characterized in that: The dual-layer structure (12) includes an upper-layer circuit and a lower-layer circuit. The upper-layer circuit contains an FPGA chip, and the lower-layer circuit contains an Ethernet PHY chip. The dual-layer structure (12) also contains a power layer and a ground layer. The power layer provides a stable operating voltage for the FPGA chip and the Ethernet PHY chip through internal wiring, and the ground layer provides a reference potential for signal transmission and reduces electromagnetic interference.

8. A motherboard compatible with single and double layer structures according to claim 7, characterized in that: The output pins of the FPGA chip and the input pins of the Ethernet PHY chip are connected via microstrip lines and vias. Both the output pins of the FPGA chip and the input pins of the Ethernet PHY chip are connected to the power plane and the ground plane via microstrip lines and vias to ensure the stability of the reference potential during signal transmission.

9. A motherboard compatible with single and double layer structures according to claim 1, characterized in that: The single-layer structure (13) includes a TL082 operational amplifier, multiple resistors, multiple capacitors and potentiometers. The multiple resistors include a first resistor, a second resistor and a third resistor. The multiple capacitors include a first capacitor and a second capacitor. A first resistor is connected in series on the non-inverting input pin of the TL082 operational amplifier. A first capacitor is connected in parallel on the connection line between the non-inverting input pin and the first resistor. One end of the first capacitor is connected to the connection line between the non-inverting input pin and the first resistor, and the other end is grounded.

10. A motherboard compatible with single and double layer structures according to claim 9, characterized in that: The inverting input pin of the TL082 operational amplifier is connected in series with a second resistor, the second resistor is connected in series with a fixed terminal of a potentiometer, the other fixed terminal of the potentiometer is grounded, the sliding terminal of the potentiometer is connected in series with a first capacitor, the first capacitor is connected in series with a third resistor, and the third resistor is connected in series with the output terminal of the TL082 operational amplifier.

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