Semiconductor structure

Abstract

The embodiment of the utility model provides a semiconductor structure. The semiconductor structure comprises a first integrated circuit component and a second integrated circuit component which are stacked with each other and electrically coupled. The first integrated circuit component includes a first bonding dielectric layer and a first bonding feature disposed in the first bonding dielectric layer and a first alignment pattern disposed in the first bonding dielectric layer. The second integrated circuit component includes a second bonding dielectric layer bonded to the first bonding dielectric layer and a second bonding feature disposed in the second bonding dielectric layer and bonded to the first bonding feature, and a second alignment pattern disposed in the second bonding dielectric layer and aligned with the first alignment pattern in a staggered manner. In a top view, the second alignment pattern is disposed within a boundary of the first integrated circuit component. By aligning the first and second alignment patterns in a staggered manner within the overlapping region, the size of the first integrated circuit component can be arbitrarily increased or decreased without being limited by the position of the second alignment pattern.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor structure, and more particularly, to a semiconductor structure with an alignment pattern. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various components (e.g., transistors, diodes, resistors, capacitors, etc.). Such improvements in integration density have come in large part from a continual reduction in the minimum feature size, which allows more components to be integrated into a given area. Technological advances in integrated circuit (IC) design have produced several generations of ICs, each having more and smaller features than the last. There is a continuing effort to develop new mechanisms for forming semiconductor structures having improved electrical performance. SUMMARY

[0003] Embodiments of the present application provide a semiconductor structure including a first integrated circuit component and a second integrated circuit component below and electrically coupled to the first integrated circuit component. The first integrated circuit component includes a first bonding structure and a first alignment pattern. The second integrated circuit component includes a second bonding structure and a second alignment pattern. The first bonding structure includes a first bonding dielectric layer and a first bonding feature disposed in the first bonding dielectric layer. The first alignment pattern is disposed in the first bonding dielectric layer. The second bonding structure includes a second bonding dielectric layer bonded to the first bonding dielectric layer and a second bonding feature disposed in the second bonding dielectric layer and bonded to the first bonding feature. The second alignment pattern is disposed in the second bonding dielectric layer and is aligned with the first alignment pattern in a staggered manner. In a top view, the second alignment pattern is disposed within a boundary of the first integrated circuit component.

[0004] Embodiments of the present application provide a semiconductor structure including a first integrated circuit component and a second integrated circuit component below and electrically coupled to the first integrated circuit component. The first integrated circuit component includes a first functional region, a first alignment region outside the first functional region, and a first alignment pattern disposed in the first alignment region. The second integrated circuit component has a size greater than a size of the first integrated circuit component. The second integrated circuit component includes a second functional region electrically coupled to the first functional region, a second alignment region outside the second functional region and overlapping the first alignment region in a stacking direction of the first integrated circuit component and the second integrated circuit component, and a second alignment pattern disposed in the second alignment region and aligned with the first alignment pattern in a staggered manner in the stacking direction. The first alignment pattern and the second alignment pattern are electrically floating.

[0005] Based on the above, the embodiments of the present application provide a semiconductor structure by aligning the first alignment pattern and the second alignment pattern in the overlapping second region in a staggered manner, the size of the first integrated circuit component can be arbitrarily increased or decreased, and is not limited by the position of the second alignment pattern of the second integrated circuit component. By configuring the alignment region of the second integrated circuit component to overlap the alignment region of the first integrated circuit component, the alignment and measurement are not affected by the change in the size of the first integrated circuit component. In addition, damage to the integrated circuit component caused by misalignment can be reduced or avoided.

[0006] In order to make the above-mentioned features and advantages of the embodiments of the present application more obvious and easy to understand, the following embodiments are specifically described, and the detailed description is made below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1A A schematic cross-sectional view of a first integrated circuit (IC) component is shown, according to some embodiments.

[0008] Figure 1B A schematic top plan view of the first IC component shown in Figure 1A is shown, according to some embodiments.

[0009] Figure 2A A schematic cross-sectional view of a second IC component is shown, according to some embodiments.

[0010] Figure 2B A schematic top plan view of the second IC component shown in Figure 2A is shown, according to some embodiments.

[0011] Figure 3A 、 Figure 3D and Figure 3E A schematic cross-sectional view of an intermediate step during a process of forming a semiconductor structure is shown, according to some embodiments.

[0012] Figure 3B A schematic top plan view of the bonded structure shown in Figure 3A is shown, according to some embodiments.

[0013] Figure 3C A schematic partial perspective view of the bonded structure shown in Figure 3A is shown, according to some embodiments.

[0014] Figure 4A A schematic cross-sectional view of a first integrated circuit (IC) component is shown, according to some embodiments.

[0015] Figure 4Bschematic top plan view of a first IC structure shown in Figure 4A schematic top plan view of a first IC structure shown in

[0016] Figure 5A and Figure 5B schematic cross-sectional views of intermediate steps during a process of forming a semiconductor structure, according to some embodiments.

[0017] Figure 6A and Figure 6B schematic cross-sectional views of different semiconductor structures, according to some embodiments.

[0018] BRIEF DESCRIPTION OF DRAWINGS

[0019] 10A, 10B, 10C, 10D: semiconductor structure; 12F: bonding interface; 12G: void; 100A, 100B, 100C, 100D: first IC component; 100Ab: backside; 100e: die edge; 101: first semiconductor substrate; 101a, 201a: frontside; 101b, 201b: backside; 102: substrate via / TSV; 102a: first end; 102b: second end; 103: first interconnect structure; 104: first bonding structure; 105, 105A, 105B, 105C, 105': first alignment pattern; 105-1, 205-1: first level pattern; 105-1P, 105-2P, 205-1P, 205-2P: pad portion; 105-1V, 105-2V, 205-1V, 205-2V: via portion; 105-2, 205-2: second level pattern; 105s, 105s', 205s, 220b: surface; 200, 200A, 200B: second IC component; 201: second semiconductor substrate; 203: second interconnect structure; 204: second bonding structure; 205, 205A, 205B, 205C, 205': second alignment pattern; 220, 220': insulating encapsulation; 230: redistribution structure; 231: dielectric layer; 232: conductive pattern; 240: conductive terminal; 1031: first dielectric layer; 1031s, 1041s1, 1041s2: top surface; 1032: first metallization pattern; 1041, 1041': first bonding dielectric layer; 1041-1, 2041-1: first sublayer; 1041-2, 2041-2: second sublayer; 1041A: first portion; 1041B: second portion; 1041R: recess; 1041s, 2041s, 2042s: bonding surface; 1041s3: sidewall; 1042: first bonding feature; 1042s: bonding surface / top surface; 1042P, 2042P: bonding pad; 2031: second dielectric layer; 2032: second metallization pattern; 2041: second bonding dielectric layer; 2042: second bonding feature; 2201: protruding portion; R11, R21: first region; R12, R12', R22: second region; THK1, THK2: thickness; W1, W2, WF1: lateral size; X, Y: direction. DETAILED DESCRIPTION

[0020] The following disclosure provides different embodiments or examples for implementing various features of the present disclosure. Specific examples of structures and arrangements are presented herein to simplify the present disclosure. These are, of course, merely examples and are in no way limiting of the scope of the present disclosure. For example, although a first feature can be described as being formed "on" or "above" a second feature in the following description, examples of the implementation can include embodiments where a first feature and a second feature are formed in direct contact, or where additional features can be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure can use repeating

[0021] Furthermore, spatial or directional terms, such as "below", "lower", "bottom", "above", "upper", and the like, can be used herein for ease of describing different components and features of the figures. The spatial and directional terms should, however, be understood bi the skilled artisan as references to the components' and features' relative locations and orientations as shown in the figures, unless otherwise noted. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial or directional terms would be interpreted accordingly.

[0022] Embodiments discussed herein are directed to providing various semiconductor structures including integrated circuit (IC) structures with alignment marks and methods for forming semiconductor structures with such IC structures. By forming IC structures with alignment marks, undesirable shifting or misalignment of the IC structures can be reduced or avoided when the IC structures are bonded to another IC structure. Furthermore, damage to the IC structures caused by misalignment can be reduced or avoided. In some embodiments, a semiconductor structure including an upper IC structure bonded to a lower IC structure is described herein. The semiconductor structure can be or include a system on integrated chip (SoIC) or the like.

[0023] According to some embodiments, Figure 1A a schematic cross-sectional view of a first IC structure is shown and Figure 1B a schematic top plan view of the first IC structure shown in Figure 1A It is noted that, Figure 1A and Figure 1B are provided for illustrative purposes only, and according to alternative embodiments, the first IC structure can utilize fewer or additional components.

[0024] Reference is made to Figure 1AA first IC structure 100A is provided. In some embodiments, the first IC structure 100A is implemented as a semiconductor die (or chip) that can be formed in a device wafer (not shown), and the device wafer can include more than one functional region (or die region) that is singulated to form multiple semiconductor dies in subsequent steps. For example, the first IC structure 100A includes a first semiconductor substrate 101, such as a doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The first semiconductor substrate 101 can include other semiconductor materials (such as germanium), compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or combinations thereof. Other substrates (such as a multilayer substrate or a graded substrate) can be used. The first semiconductor substrate 101 can include a front side 101a and a back side 101b opposite the front side 101a. Devices (not shown individually, such as transistors, diodes, capacitors, resistors, or the like) can or can not be formed at the front side 101a of the first semiconductor substrate 101.

[0025] In some embodiments, the first IC structure 100A includes a first interconnect structure 103 disposed above the first semiconductor substrate 101. The first interconnect structure 103 can be formed from alternating layers of dielectric (such as low-k dielectric material) and conductive material (such as copper) with vias interconnecting the layers of conductive material, and can be formed by any suitable process (such as deposition, single damascene, dual damascene, or the like). For example, the first interconnect structure 103 includes one or more first dielectric layers 1031 and first metallization patterns 1032 disposed in the first dielectric layers 1031. The first metallization patterns 1032 can include wires, conductive pads, and vias, and can be electrically coupled to devices to form an integrated circuit. In some embodiments, the first IC structure 100A includes through substrate vias (TSVs) 102 formed in the first semiconductor substrate 101, which are formed by depositing one or more diffusion barrier or isolation layers in a trench of the first semiconductor substrate 101, depositing a seed layer, and depositing a conductive material (such as tungsten, titanium, aluminum, copper, any combination thereof, and / or the like). For example, a respective TSV 102 includes a first end 102a physically and electrically connected to one of the first metallization patterns 1032, and a second end 102b opposite the first end 102b, where at this stage the second end 102b can be buried in the first semiconductor substrate 101.

[0026] Continuing to refer to Figure 1AThe first IC component 100A can include a first bonding structure 104 disposed over the first interconnect structure 103. The first bonding structure 104 can include one or more first bonding dielectric layers 1041 and first bonding features 1042 laterally covered by the first bonding dielectric layers 1041. The first bonding dielectric layers 1041 used for bonding later include one or more dielectric materials (e.g., silicon nitride, silicon oxide, and / or the like. In some embodiments, the first bonding dielectric layers 1041 and the first dielectric layers 1031 underneath the first bonding dielectric layers 1041 include different dielectric materials. The first bonding dielectric layers 1041 can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), a spin-on process, a combination thereof, or the like. The corresponding first bonding features 1042 can be or include bonding pads 1042P and / or bonding vias 1042V, and can be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The first bonding features 1042 can include one or more conductive materials, which can be metallic materials including a metal or a metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, or an alloy thereof.

[0027] In the illustrated embodiment, the bonding vias 1042V land on a topmost one of the first metallization patterns 1032, and the bonding pads 1042P overlie the bonding vias 1042V. In alternative embodiments, the bonding pads 1042P are omitted, and the corresponding bonding vias 1042V through the first bonding dielectric layers 1041 have one end landing on any of the first metallization patterns 1032 and an opposite end that is substantially flush with (and / or exposed by) the first bonding dielectric layers 1041. According to some other embodiments, the first bonding structure 104 can have other configurations. In some embodiments, a planarization process (e.g., chemical mechanical polishing (CMP), lapping, etching, a combination thereof, or the like) is performed on the first bonding structure 104 such that bonding surfaces 1042s of the first bonding features 1042 and bonding surfaces 1041s of the first bonding dielectric layers 1041 are substantially flush (or coplanar) within a process variation range.

[0028] Still referring to Figure 1AThe first IC component 100A can include one or more first alignment patterns 105 formed in the first bonding structure 104. For example, the first alignment pattern 105 is laterally covered by the first bonding dielectric layer 1041. The first alignment pattern 105 can be made of an electrically conductive material. For example, the first alignment pattern 105 is formed concurrently with the first bonding features 1042 (e.g., bonding pads 1042P). In other embodiments, the first bonding features 1042 and the first alignment pattern 105 are formed in different steps and include different electrically conductive materials. In some embodiments, the first alignment pattern 105 is a dummy structure that is electrically decoupled or electrically isolated from any electrically conductive features in the first IC component 100A. The first alignment pattern 105 can be electrically floating in the first IC component 100A. In some embodiments, the first alignment pattern 105 is made of a non-conductive material (e.g., an insulating material or the like). The non-conductive material of the first alignment pattern 105 can be different from the first bonding dielectric layer 1041 such that there is a visible difference between the first alignment pattern 105 and the first bonding dielectric layer 1041. In some embodiments, during a planarization process performed on the first bonding structure 104, the surface 105s of the first alignment pattern 105 can be planarized to be substantially flush (or coplanar) with the bonding surface 1042s of the first bonding features 1042 and the bonding surface 1041s of the first bonding dielectric layer 1041 within a process variation range.

[0029] Referring to Figure 1B and referring to Figure 1A The first IC component 100A can include a first region R11 and a second region R12 surrounding the first region R11. For example, the first region R11 is a functional region (or active region) and the first bonding features 1042 are disposed in the functional region, and the second region R12 is a non-functional region (e.g., a non-active region or a peripheral region) and the first alignment pattern 105 is disposed in the second region R12. In some embodiments, a seal ring structure (not shown) is disposed at the interface of the first region R11 and the second region R12 to separate functional features in the first region R11 from non-functional features in the second region R12. In some embodiments, the first alignment pattern 105 is distributed at the corners of the die, as shown in FIG. 1A. Figure 1BThe first alignment pattern 105 can be placed at any location within the second region R12 of the first IC component 100A. In some embodiments, the first alignment pattern 105' is located at (or near) the midpoint of two opposite die edges 100e in the top plan view, where the first alignment patterns 105' at the two opposite die edges 100e can be arranged in a symmetrical manner. In alternative embodiments, multiple first alignment patterns 105 are arranged next to the die edges 100e and can (or can not) be arranged in a symmetrical manner.

[0030] Continuing to refer to Figure 1B , according to some embodiments, designs of possible first alignment patterns are shown. For example, a top view of the first alignment pattern 105A is a continuous cross shape and is located at the center of a dashed box that encloses the alignment pattern. In some embodiments, a top view of the first alignment pattern 105B includes separate square (or rectangular) segments that are arranged to form a cross shape in a dashed box that encloses the alignment pattern. In some embodiments, a top view of the first alignment pattern 105C includes separate vertical bars and separate horizontal bars, where the separate vertical bars are located at the upper and left portions of a dashed box that encloses the alignment pattern, and the separate horizontal bars are located at the lower and right portions of the dashed box. The shapes of the first alignment patterns (105A, 105B, and 105C) are provided for illustrative purposes only and are not intended to limit the scope of the embodiments described herein. Any shape (e.g., a circle, an ellipse, a triangle, a square, an L-shape, a combination thereof, or the like) can be used as the first alignment pattern 105. The top view shape of the first alignment pattern 105 at each die corner (or each die edge) can be the same or similar. In other embodiments, the top view shape of the first alignment pattern 105 at different locations can be different. The first alignment pattern 105 can be used to precisely align the first IC component 100A with a second IC component (see Figure 3A labeled "200" in FIG. 2).

[0031] According to some embodiments, Figure 2A a schematic cross-sectional view of a second IC component is shown and Figure 2B a schematic top plan view of the second IC component shown in Figure 2A is shown. It is noted that Figure 2A and Figure 2B are provided for illustrative purposes only, and according to alternative embodiments, the second IC component can use fewer or additional components.

[0032] Referring toFigure 2A Referring also to Figure 1A , a second IC structure 200 is provided. In some embodiments, the second IC structure 200 is implemented as a semiconductor wafer, which can include one or more functional regions. For example, the second IC structure 200 includes a second semiconductor substrate 201. The material of the second semiconductor substrate 201 can be similar to the material of the first semiconductor substrate 101 described above. The second semiconductor substrate 201 can include a front side 201a and a back side 201b opposite the front side 201a. Devices (not shown individually, such as transistors, diodes, capacitors, resistors, or the like) can or can not be formed at the front side 201a of the second semiconductor substrate 201. Figure 1A

[0033] In some embodiments, the second IC structure 200 includes a second interconnect structure 203 disposed over the second semiconductor substrate 201. For example, the second interconnect structure 203 includes one or more second dielectric layers 2031 and second metallization patterns 2032 disposed in the second dielectric layers 2031. The second metallization patterns 2032 can include wires, conductive pads, and vias and can be electrically coupled to the devices to form an integrated circuit. The second dielectric layers 2031 and the second metallization patterns 2032 of the second interconnect structure 203 can be similar to the first dielectric layers 1031 and the first metallization patterns 1032 of the first interconnect structure 103, respectively.

[0034] Continuing to refer to Figure 2A and Figure 1A , the second IC structure 200 can include a second bonding structure 204 disposed over the second interconnect structure 203. The second bonding structure 204 can include one or more second bonding dielectric layers 2041 overlying the second dielectric layers 2031 and second bonding features 2042 laterally covered by the second bonding dielectric layers 2041. The second bonding dielectric layers 2041 and the second bonding features 2042 can be similar to the first bonding dielectric layers 1041 and the first bonding features 1042, respectively. The respective second bonding features 2042 can be or include bonding pads 2042P and / or bonding vias 2042V. The bonding vias 2042V can land on one of the second metallization patterns 2032, and the bonding pads 2042P overlie the bonding vias 2042V. In alternative embodiments, the bonding pads 2042P are omitted, and the respective bonding vias 2042V through the second bonding dielectric layers 2041 have one end landing on one of the second metallization patterns 2032 and an opposite end exposed by the second bonding dielectric layers 2041. In some embodiments, bonding surfaces 2042s of the second bonding features 2042 and bonding surfaces 2041s of the second bonding dielectric layers 2041 are substantially flush (or coplanar) within a process variation range.

[0035] Still referring to​Figure 2A and Figure 1A The second IC component 200A may include one or more second alignment patterns 205 formed in the second bonding structure 204 and laterally covered by the second bonding dielectric layer 2041. The material of the second alignment pattern 205 may be similar to... Figure 1A The first alignment pattern 105 is described. In some embodiments, the second alignment pattern 205 includes one or more conductive materials and may be formed simultaneously with the formation of the second bonding feature 2042 (e.g., bonding pad 2042P). Alternatively, the second bonding feature 2042 and the second alignment pattern 205 may be formed in different steps and / or may include different conductive materials. In some embodiments, the second alignment pattern 205 is a dummy structure electrically decoupled or electrically isolated from any conductive feature in the second IC component 200. The second alignment pattern 205 may be electrically floating in the second IC component 200. In some embodiments, the second alignment pattern 205 is made of a non-conductive material (e.g., an insulating material or any suitable material), and there is a visible interface between the second alignment pattern 205 and the second bonding dielectric layer 2041. In some embodiments, during the planarization process of the second bonding structure 204, the surface 205s of the second alignment pattern 205 may be planarized to be substantially flush (or coplanar) with the bonding surface 2042s of the second bonding feature 2042 and the bonding surface 2041s of the second bonding dielectric layer 2041 within the range of process variations.

[0036] refer to Figure 2B And refer to Figure 2A and Figure 1B The second IC component 200 may include a first region R21 and a second region R22 surrounding the first region R21. For example, the first region R21 is a functional region (or active region) and the second engagement feature 2042 is disposed in the first region R21, and the second region R22 is a non-functional region (e.g., an inactive region or a peripheral region). In some embodiments, a sealing ring structure (not shown) is disposed at the junction of the first region R21 and the second region R22 to separate the functional feature in the first region R21 from the non-functional feature in the second region R22. A second alignment pattern 205 may be disposed in the second region R22 without affecting the first region R21. In some embodiments, the second alignment pattern 205 is distributed near (or corresponding to) a corner of the first region R21, such as... Figure 2B As shown in the top plan view. In some embodiments, in the top plan view, the second alignment pattern 205' is located at (or near) the midpoint of opposite sides of the first region R21, wherein the second alignment patterns 205' on opposite sides of the first region R21 may be arranged symmetrically. In alternative embodiments, the second alignment patterns 205 are disposed next to opposite sides of the first region R21 and may (or may not) be arranged symmetrically.

[0037] With continued reference to Figure 2B , according to some embodiments, designs of possible second alignment patterns are shown. By way of example, a top view of a second alignment pattern 205A includes separate square (or rectangular) segments arranged at the corners of a dashed-line box that frames the alignment pattern. In some embodiments, a top view of a second alignment pattern 205B includes separate vertical bars and separate horizontal bars, where the separate vertical bars are at the upper-left and lower-right portions of a dashed-line box that frames the alignment pattern, and the separate horizontal bars are at the upper-right and lower-left portions of the dashed-line box. In some embodiments, a top view of a second alignment pattern 205C includes separate vertical bars and separate horizontal bars, where the separate vertical bars are at the upper-left portion of a dashed-line box that frames the alignment pattern and the separate horizontal bars are at the lower-left portion of the dashed-line box. The shapes of the second alignment patterns (205A, 205B, and 205C) are provided for illustrative purposes only and are not intended to limit the scope of the embodiments described herein. Any shape (e.g., circular, elliptical, triangular, square, L-shaped, combinations thereof, or the like) can be used as the second alignment pattern 205. The top view shapes of the second alignment pattern 205 near each corner of the first region R21 (or along each side of the first region R21) can be the same or similar. In other embodiments, the top view shapes of the second alignment pattern 205 at different locations can be different. The top view shape / profile of the second alignment pattern 205 can be different from the top view shape / profile of the first alignment pattern 105. In some embodiments, the second alignment pattern 205 and the first alignment pattern 105 are formed to identify a correct orientation / position of the first IC component 100A on the second IC component 200. There are various advantages to using first / second alignment patterns. By way of example, undesirable shifting of the first IC component 100A when joining the first IC component 100A to the second IC component 200 can be reduced or avoided. In addition, damage to the first IC component 100A caused by misalignment can be reduced or avoided. This will be described in more detail in connection with Figures 3A-3E .

[0038] According to some embodiments, Figure 3A , Figure 3D and Figure 3E schematic cross-sectional views of intermediate steps during a process of forming a semiconductor structure are shown, Figure 3B schematic top plan views of the joined structures shown in Figure 3A schematic partial perspective views of the joined structures shown in Figure 3C schematic partial perspective views of the joined structures shown in Figure 3A , the materials of the components in these embodiments are substantially as described in Figures 1A-1B and Figures 2A-2BLike elements in the illustrated embodiments are designated with like reference numerals. Although method embodiments can be discussed as being performed in a particular order, other method embodiments can be performed in any logical order.

[0039] Referring Figures 3A-3C and referring Figures 1A-1B and Figures 2A-2B The first IC member 100A can be stacked on and bonded to the second IC member 200 in the illustrated embodiment. The lateral size Wl of the first IC member 100A can be smaller than the lateral size W2 of the second IC member 200. In some embodiments, multiple first IC members 100A are bonded to the second IC member 200, with the first IC members 100A positioned in different regions of the second IC member 200 and laterally separated from one another. In some embodiments, the first IC member 100A is a semiconductor die, the second IC member 200 is a semiconductor wafer, and the bonding involves die-to-wafer bonding.

[0040] In some embodiments, the first IC member 100A is disposed on the second IC member 200 using a pick-and-place process. For example, a pick-and-place tool (not shown) including a pick head, a robotic arm, a controller, sensors, and / or any other components is configured to perform the pick-and-place process. In some embodiments, the first IC member 100A (e.g., a known good die) is picked up by the pick-and-place tool and transferred to an intended location on the second IC member 200. The first IC member 100A carried by the pick-and-place tool can be positioned over and aligned with the second IC member 200. The first IC member 100A can then be placed on the second IC member 200. For example, the first IC member 100A is placed on the second IC member 200 at a location where the first regions (Rl l and R21) are aligned and overlap one another and the second regions (R12 and R22) are aligned and overlap one another. The first bonding features 1042 can overlap and be generally aligned with the second bonding features 2042 within a process variation range.

[0041] It is appreciated that the precise alignment can reduce manufacturing defects and allow for subsequent formation of a redistribution structure design with smaller buffer zones and finer pitches. In some embodiments, the first alignment pattern 105 and the second alignment pattern 205 are used to align the first IC member 100A on the second IC member 200 during a pick-and-place process and / or a subsequently performed bonding process. For example, the alignment includes aligning the first alignment pattern 105 with the second alignment pattern 205. In some embodiments, the first alignment pattern 105 and / or the second alignment pattern 205 can be sensed by one or more sensors of a pick-and-place tool via visible light, infrared, or any other suitable electromagnetic radiation of suitable wavelengths. For example, the sensors are configured to monitor the alignment and transmit appropriate signals to a controller, and the pick head can be moved accordingly until the first alignment pattern 105 of the first IC member 100A is aligned with the second alignment pattern 205 of the second IC member 200. The precise alignment can avoid a shift of the first IC member 100A that can result in electrical malfunction of the resulting semiconductor structure.

[0042] With continued reference to Figures 3A-3C After the first IC member 100A is disposed on the second IC member 200, the first alignment pattern 105 and the second alignment pattern 205 can be arranged in a matrix in an interleaved manner in cross-sectional and top plan views. For example, in a cross-sectional view of Figure 3A the segment of the first alignment pattern 105 is directly above a gap between separate segments of the second alignment pattern 205. The segment of the first alignment pattern 105 can be laterally and vertically offset from the separate segments of the second alignment pattern 205. In some embodiments, in a top plan view, the area enclosing the first alignment pattern 105 and the area enclosing the second alignment pattern 205 can coincide. For example, the dashed box enclosing the first alignment pattern 105 overlaps and coincides with the dashed box of the second alignment pattern 205, as shown in Figure 3B In a top plan view, the segment of the first alignment pattern 105 does not overlap with the segment of the second alignment pattern 205. In some embodiments, when the first alignment pattern 105 is aligned with the second alignment pattern 205, the segment of the first alignment pattern 105 has an offset in the X direction and the Y direction, respectively, relative to the segment of the second alignment pattern 205.

[0043] Still with reference to Figure 3B and Figure 3CThe boundary of the first IC structure 100A can be entirely disposed within the boundary of the second IC structure 200. For example, after alignment and placement, the top view of the first alignment pattern 105 and the second alignment pattern 205 can have various shapes. For example, in one case, the first alignment pattern 105A is aligned with the second alignment pattern 205A, where the separate square (or rectangular) segments of the second alignment pattern 205A are located at the corners of the dashed line box that frames the alignment pattern, and in the top view, the continuous cross-shaped segment of the first alignment pattern 105A is located at the center of the dashed line box without overlapping the second alignment pattern 205A. In another case, the first alignment pattern 105B is aligned with the second alignment pattern 205A, where the separate square (or rectangular) segments of the first alignment pattern 105A and the second alignment pattern 205A are alternately arranged along the sides of the dashed line box that frames the alignment pattern, and the separate cross-shaped center segment of the second alignment pattern 205A is located at the center of the dashed line box. In yet another case, the first alignment pattern 105B is aligned with the second alignment pattern 205B, where the center of the separate cross-shaped segment of the first alignment pattern 105B is at the center of the dashed line box that frames the alignment pattern, and in the top view, the separate vertical bars and the separate horizontal bars of the second alignment pattern 205B are arranged at the corners of the dashed line box without overlapping the first alignment pattern 105B. In another case, the first alignment pattern 105C is aligned with the second alignment pattern 205C, where the separate vertical bars of the first alignment pattern 105C and the second alignment pattern 205C are arranged in the upper portion of the dashed line box that frames the alignment pattern, and the separate horizontal bars of the first alignment pattern 105C and the second alignment pattern 205C are arranged in the lower portion of the dashed line box. Other configurations of the aligned first and second alignment patterns (105 / 205) are also possible. The top view shapes of the aligned first and second alignment patterns (105 / 205) provided herein are for illustrative purposes only and are not intended to limit the scope of the embodiments described herein.

[0044] In some embodiments, the first alignment pattern 105 and the second alignment pattern 205 are referred to as overlay marks for measuring overlay error or checking alignment accuracy. For example, when measuring overlay error using the first alignment pattern 105 and the second alignment pattern 205, the deviation in the X direction is measured along the X direction of the first alignment pattern 105 and the second alignment pattern 205, and the deviation in the Y direction is measured along the Y direction of the first alignment pattern 105 and the second alignment pattern 205. By aligning the first alignment pattern 105 and the second alignment pattern 205 in a staggered manner within the overlapping second regions (R12 / R22), the size of the first IC component 100A can be arbitrarily increased or decreased without being limited by the position of the second alignment pattern 205 of the second IC component 200. For example, if the second alignment pattern 205 is disposed at a position outside the region in which the first IC component 100A is to be disposed, the die edge of the first IC component 100A can affect alignment and measurement due to being too close to the second alignment pattern 205 during the bonding process. In addition, in the case where the second alignment pattern 205 is disposed on a region outside the region in which the first IC component 100A is to be bonded, the first IC component 100A cannot be arbitrarily increased in size because the size of the first IC component 100A is too large to partially or completely block the second alignment pattern 205, affecting alignment and measurement during the bonding process. By configuring the alignment region (e.g., R22) of the second IC component 200 to overlap with the alignment region (e.g., R12) of the first IC component 100A, alignment and measurement are not affected by the size of the first IC component 100A being too large.

[0045] Returning to Figure 3AAfter the first IC component 100A is placed on the second IC component 200, a bonding process can be performed to bond the first IC component 100A to the second IC component 200. In some embodiments, prior to performing the bonding process, a surface treatment (e.g., a plasma treatment) is performed on the bonding surfaces of the first bonding structure 104 and the second bonding structure 204. After the surface treatment, the bonding surfaces of the first bonding structure 104 and the second bonding structure 204 can be cleaned by a chemical cleaning and / or deionized water cleaning. The bonding surfaces of the first bonding structure 104 and the second bonding structure 204 can then be bonded together. The respective first bonding features 1042 and second bonding features 2042 can be aligned with and pre-bonded to each other. In the illustrated embodiment, each of the bonding pads 1042P is aligned with and bonded to any of the bonding pads 2042P. Alternatively, the bonding involves via-to-pad bonding (e.g., bonding the vias 1042V to the bonding pads 2042P or bonding the bonding pads 1042P to the bonding vias 2042V) or via-to-via bonding (e.g., bonding the vias 1042V and 2042V together), depending on the configuration of the bonding structures. After the pre-bonding, the dielectric materials and the conductive materials of the first bonding structure 104 are bonded to the dielectric materials and the conductive materials of the second bonding structure 204, respectively. For example, the first bonding structure 104 of the first IC component 100A is physically and electrically connected to the second bonding structure 204 of the second IC component 200. In some embodiments, the first bonding dielectric layer 1041 is bonded to the second bonding dielectric layer 2041, and the first bonding features 1042 and the second bonding features 2042 are bonded to each other.

[0046] The bonds of the first bonding structure 104 and the second bonding structure 204 can be strengthened in an annealing process. During annealing, the metals in the first bonding features 1042 and the second bonding features 2042 can diffuse into each other to form metal-to-metal bonds. After the bonding process, metal-to-metal (e.g., copper-to-copper) bonds and dielectric-to-dielectric (e.g., oxide-to-oxide) bonds can be formed at the bonding interface 12F of the first IC component 100A and the second IC component 200. The bonding interface 12F can be substantially planar and horizontal within a process variation range. The first alignment pattern 105 and the second alignment pattern 205 can be laterally offset from each other, and the first alignment pattern 105 and the second alignment pattern 205 can not be directly bonded to each other. For example, the first alignment pattern 105 formed of conductive material is bonded to the second bonding dielectric layer 2041, and the second alignment pattern 205 formed of conductive material is bonded to the first bonding dielectric layer 1041. Metal-to-dielectric (e.g., copper-to-oxide) bonds and dielectric-to-dielectric (e.g., oxide-to-oxide) bonds can be formed at the bonding interface 12F within the second region (R12 / R22).

[0047] Referring toFigure 3D Referring also to Figure 3A An insulative encapsulant 220 can be formed over the second IC component 200 to laterally cover the first IC component 100A. The insulative encapsulant 220 can be or include a molding compound, a molding underfill, an epoxy, or the like, and can be applied by compression molding, transfer molding, or the like. To form the insulative encapsulant 220, a curing process can be selectively performed to harden the insulative material for optimal protection. In alternative embodiments, the insulative encapsulant 220 includes a dielectric material (e.g., an oxide, a nitride, or the like) and can be formed using CVD, PVD, ALD, or the like. In some embodiments, the insulative encapsulant 220 is formed by forming an insulative material over the second IC component 200 to bury the first IC component 100A and performing a planarization process (e.g., CMP, grinding, etching, and / or the like) to remove excess portions of the insulative material. During the planarization process, a portion of the first semiconductor substrate 101 can be removed to expose the TSVs 102 in an accessible manner. For example, the backside 101b of the first semiconductor substrate 101 is thinned to expose the second ends 102b of the TSVs 102 for further electrical connections. The backside 101b of the first semiconductor substrate 101 and the second ends 102b of the TSVs 102 can be collectively considered as a back surface 100Ab of the first IC component 100A. In some embodiments, a surface 220b of the insulative encapsulant 220 is substantially planar (or coplanar) with the back surface 100Ab of the first IC component 100A within a process variation range.

[0048] Referring also to Figure 3E Referring also to Figure 3DA rewire structure 230 can be formed on the insulating encapsulation 220 and the first IC member 100A. The rewire structure 230 can include a dielectric layer 231 and a conductive pattern 232 formed in / on the dielectric layer 231. The rewire structure 230 is shown as an example, but more dielectric layers and conductive patterns can be formed in the rewire structure. The material of the dielectric layer 231 can be or include a photosensitive material, such as PBO, PI, BCB, a combination thereof, or the like. The dielectric layer 231 can be deposited on the surface 220b of the insulating encapsulation 220 and the backside 100Ab of the first IC member 100A, and the dielectric layer 231 can expose at least a portion of the second end 102b of the TSV 102. The material(s) of the conductive pattern 232 can be or include copper, nickel, titanium, an alloy thereof, a combination thereof, or the like. The conductive pattern 232 can include conductive features, such as wires, vias, and / or conductive pads, and these conductive features are collectively referred to as a rewire layer or a rewire. A bottommost one of the conductive pattern 232 can be in physical and electrical contact with the second end 102b of the TSV 102. In some embodiments, a topmost one of the conductive pattern 232 includes an under bump metallization (UBM) pad, on which a subsequently formed terminal lands.

[0049] In some embodiments, a plurality of conductive terminals 240 are formed on a topmost one of the conductive pattern 232. The conductive terminals 240 can include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, and / or a combination thereof. The conductive terminals 240 can be or include solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) bumps, ball grid array (BGA) connections, and / or the like, and can be formed by ball placement, evaporation, plating, printing, solder transfer, or any suitable process. The semiconductor structure 10A is thus provided. In some embodiments, one or more semiconductor processes (such as singulation, packaging, coupling to another member, and / or the like) are performed on the semiconductor structure 10A to form a semiconductor product.

[0050] According to some embodiments, Figure 4A a schematic cross-sectional view of the first IC member is shown and Figure 4B a schematic top plan view of the first IC member shown in Figure 4A a schematic top plan view of the first IC member shown in Figure 1A and 1BSimilar components in the illustrated embodiments are the same, and similar components are designated by like reference numbers.

[0051] Referring to Figures 4A-4B and referring to Figures 1A-1B , the first IC component 100B can be similar to the first IC component 100A described in Figures 1A-1B , and thus the detailed description is not repeated for brevity. The differences between the first IC components (100A and 100B) include that the first bonding dielectric layer 1041’ of the first IC component 100B can include a first portion 1041A in the first region R11 and a second portion 1041B surrounding the first portion 1041A and in the second region R12’. In some embodiments, the thickness THK1 of the first portion 1041A is less than the thickness THK2 of the second portion 1041B. For example, after depositing a bonding dielectric material on the first interconnect structure 103, the recess 1041R can be performed by using etching or any suitable removal process to thin a portion of the bonding dielectric material in the second region R12’ to form the first bonding dielectric layer 1041’. The recess 1041R around the periphery of the first IC component 100B can provide stress relief for the stress generated during the subsequent bonding / molding process. The top surface 1041s2 of the second portion 1041B can be between the top surface 1031s of the first dielectric layer 1031 of the first interconnect structure 103 and the top surface 1041s1 of the first portion 1041A. The sidewall 1041s3 of the first bonding dielectric layer 1041’ can be connected to the top surfaces (1041s1 and 1041s2), where the sidewall 1041s3 can be located at the interface of the first region R11 and the second region R12’.

[0052] In some embodiments, the first bonding feature 1042 is formed in the first portion 1041A of the first bonding dielectric layer 1041’, and the first alignment pattern 105 is under the recess 1041R and formed in the second portion 1041B of the first bonding dielectric layer 1041’. The first IC component 100B can be precisely placed onto the intended position of the second IC component 200 by using the first alignment pattern 105. The surface 105s’ of the first alignment pattern 105 can be under the top surface 1042s of the first bonding feature 1042. The top surface 1042s of the first bonding feature 1042 can be substantially flush (or coplanar) with the top surface 1041s1 of the first portion 1041A and can be above the top surface 1041s2 of the second portion 1041B. The first alignment pattern 105 can be disposed at a corner of the first IC component 100B. Alternatively, the first alignment pattern 105 can be disposed at any location in the second region R12’. Figure 4B The first alignment pattern 105A shown in is exemplary, and the first alignment pattern can be replaced by other shaped alignment marks as previously described.

[0053] Figure 5A and Figure 5B schematic cross-sectional views of intermediate steps during a process of forming a semiconductor structure are shown. Unless otherwise noted, the materials of the components in these embodiments are substantially the same as the similar components in the embodiments shown in Figures 3A-3E FIGS. 1-8, and like components are indicated by like reference numbers. Thus, material details regarding the components can be found in the discussion of the embodiments shown in Figures 3A-3E FIGS. 1-8. While method embodiments can be discussed as being performed in a particular order, other method embodiments can be performed in any logical order.

[0054] Referring to Figure 5A and referring to Figures 4A-4B and Figures 3A-3C , the first IC component 100B can be stacked on and physically and electrically bonded to the second IC component 200. For example, the first IC component 100B is picked and placed on the second IC component 200 with the first alignment pattern 105 and the second alignment pattern 205 to ensure the alignment accuracy of the subsequent processes, and then a bonding process is performed to bond the first IC component 100B to the second IC component 200. The process can be similar to the process described in Figures 3A-3C . The difference includes that after the bonding process, a gap 12G is formed between the first IC component 100B and the second IC component 200, where the gap 12G corresponds to the recess 1041R of the first bonding dielectric layer 1041’ and is located in the overlapped second region (R12’ / R22). The gap 12G can act as a stress buffer during the bonding process, thereby effectively reducing the cracking / delamination of the interface. The lateral size WF1 of the bonding interface 12F can be smaller than the lateral size W1 of the first IC component 100B. In some embodiments, the lateral size WF1 of the bonding interface 12F is the lateral size of the first portion 1041A of the first bonding dielectric layer 1041’. The second portion 1041B of the first bonding dielectric layer 1041’ can be vertically spaced apart from the second bonding dielectric layer 2041. The first alignment pattern 105 can be offset from the second alignment pattern 205 in the X, Y, and Z directions.

[0055] Referring to Figure 5B and referring to Figure 5A and Figures 3D-3E , an insulating encapsulation 220’ can be formed on the second IC component 200 to cover the first IC component 100B. Except that the insulating encapsulation 220’ can have a protruding portion 2201 extending into the gap 12G between the first IC component 100B and the second IC component 200, the material and formation process of the insulating encapsulation 220’ can be similar to the insulating encapsulation 220 shown in Figure 3DThe materials and formation processes of the insulative encapsulation 220 described in the middle. The voids 12G can act as stress buffers when forming the insulative encapsulation 220’ (e.g., during a molding process), thereby effectively reducing the interface cracking / delamination. The surfaces 105s’ of the first alignment pattern 105, the surfaces 205s of the second alignment pattern 205, and the sidewalls 1041s3 of the first bonding dielectric layer 1041’ can be in direct contact with the protruding portions 2201 of the insulative encapsulation 220’.

[0056] In some embodiments, after forming the insulative encapsulation 220’, a re- wiring structure 230 is formed on the insulative encapsulation 220’ and the first IC Figure 3E structure 100B. Conductive terminals 240 can be formed on the re-wiring structure 230 to be electrically connected with the conductive patterns 232. The formation of the re- wiring structure 230 and the conductive terminals 240 can be similar to the processes described in

[0057] Figure 6A and Figure 6B schematic cross-sectional views of different semiconductor structures according to some embodiments are shown. Like reference numbers indicate like elements, unless otherwise specified.

[0058] Reference is made to Figure 6A and Figure 3E , in addition to the bonding structures and alignment patterns, Figure 6A The semiconductor structure 10C shown can be similar to the semiconductor structure 10B described in Figure 3EThe semiconductor structure 10A shown in FIG. 1. For example, the first bonding dielectric layer 1041 of the first bonding structure 104 of the first IC component 100C includes a first sub-layer 1041-1 connected to the first interconnect structure 103 and a second sub-layer 1041-2 connected to the first sub-layer 1041-1 and bonded to the second bonding dielectric layer 2041. In some embodiments, a bonding pad 1042P of the first bonding feature 1042 is formed in the second sub-layer 1041-2, and a bonding via 1042V of the first bonding feature 1042 connected to the bonding pad 1042P penetrates the first sub-layer 1041-1 and the second sub-layer 1041-2 to connect to the first interconnect structure 103. The first alignment pattern 105 can be formed in both the first sub-layer 1041-1 and the second sub-layer 1041-2 within the second region R12. For example, a first level pattern 105-1 of the first alignment pattern 105 is formed in the first sub-layer 1041-1, and a second level pattern 105-2 of the first alignment pattern 105 is formed in the second sub-layer 1041-2 and vertically aligned with the first level pattern 105-1 of the first alignment pattern 105. The first level pattern 105-1 and the second level pattern 105-2 of the first alignment pattern 105 can overlap in a top-down view (not shown).

[0059] In some embodiments, the second bonding dielectric layer 2041 of the second bonding structure 204 of the second IC component 200A includes a first sub-layer 2041-1 connected to the second interconnect structure 203 and a second sub-layer 2041-2 connected to the first sub-layer 2041-1 and bonded to the first bonding dielectric layer 1041. In some embodiments, a bonding pad 2042P of the second bonding feature 2042 is formed in the second sub-layer 2041-2 and bonded to the bonding pad 1042P, and a bonding via 2042V of the second bonding feature 2042 connected to the bonding pad 2042P penetrates the first sub-layer 2041-1 and the second sub-layer 2041-2 to connect to the second interconnect structure 203. The second alignment pattern 205 can be formed in both the first sub-layer 2041-1 and the second sub-layer 2041-2 within the second region R22. For example, a first level pattern 205-1 of the second alignment pattern 205 is formed in the first sub-layer 2041-1, and a second level pattern 205-2 of the second alignment pattern 205 is formed in the second sub-layer 2041-2 and vertically aligned with the first level pattern 205-1 of the second alignment pattern 205. The first level pattern 205-1 and the second level pattern 205-2 of the second alignment pattern 205 can overlap in a top-down view (not shown).

[0060] In some embodiments, the position of the first IC feature 100C on the second IC feature 200A is determined by the first alignment pattern 105 and the second alignment pattern 205 during a pick-and-place process, so as to precisely place the first IC feature 100C onto a predetermined position of the second IC feature 200A. In some embodiments, after the first IC feature 100C is bonded to the second IC feature 200A, the first level pattern 105-1 and the second level pattern 105-2 of the first alignment pattern 105 are aligned with the first level pattern 205-1 and the second level pattern 205-2 of the second alignment pattern 205 in a staggered manner in a cross-sectional view and a top plan view, where the top plan view can be referenced with respect to the description of FIG. 1A. Figure 3B

[0061] Referring to Figure 6B and Figure 6A , in addition to the alignment patterns, Figure 6B the semiconductor structure 10D shown can be similar to the semiconductor structure 10C shown in Figure 6A . For example, the first level pattern 105-1 of the first alignment pattern 105 formed in the first sub-layer 1041-1 of the first bonding dielectric layer 1041 of the first IC feature 100D includes a landing pad portion 105-1P and a via portion 105-1V connected to the landing pad portion 105-1P and landing on the first interconnect structure 103. Similarly, the second level pattern 105-2 of the first alignment pattern 105 formed in the second sub-layer 1041-2 of the first bonding dielectric layer 1041 includes a landing pad portion 105-2P and a via portion 105-2V connected to the landing pad portion 105-2P and landing on the landing pad portion 105-1P. The landing pad portion and the via portion (e.g., 105-1P and 105-1V or 105-2P and 105-2V) can collectively have an inverted T-shaped cross-section.

[0062] ​In some embodiments, the first level pattern 205-1 of the second alignment pattern 205 formed in the first sub-layer 2041-1 of the second bonding dielectric layer 2041 of the second IC component 200B includes a landing pad portion 205-1P and a via portion 205-1V connected to the landing pad portion 205-1P and landing on the second interconnect structure 203. Similarly, the second level pattern 205-2 of the second alignment pattern 205 formed in the second sub-layer 1041-2 of the second bonding dielectric layer 2041 of the second IC component 200B includes a landing pad portion 205-2P and a via portion 205-2V connected to the landing pad portion 205-2P and landing on the landing pad portion 205-1P. The landing pad portion and the via portion (e.g., 205-1P and 205-1V or 205-2P and 205-2V) can collectively have an inverted T-shaped cross-section. During a pick-and-place process, the position of the first IC component 100D on the second IC component 200B can be determined by the first alignment pattern 105 and the second alignment pattern 205, so that the first IC component 100D is precisely placed on the second IC component 200B at a predetermined position. After the first IC component 100D is bonded to the second IC component 200B, the first level pattern 105-1 and the second level pattern 105-2 of the first alignment pattern 105 and the first level pattern 205-1 and the second level pattern 205-2 of the second alignment pattern 205 are aligned in a staggered manner in a matrix in a cross-sectional view and a top plan view.

[0063] The first alignment pattern 105 and the second alignment pattern 205 can be used to check the alignment accuracy between the first IC component and the second IC component. By using the first alignment pattern 105 and the second alignment pattern 205, undesirable shifting and rotation of the first IC component can be reduced or avoided. In addition, damage to the first IC component due to misalignment can be reduced or avoided. It should be appreciated that as design rules shrink and manufacturing of integrated circuits tends to use multi-layer designs, the area cost problem of alignment marks becomes very high. By configuring the alignment region (e.g., R22) of the second IC component to overlap with the alignment region (e.g., R12) of the first IC component and within the boundary of the first IC component, the alignment and measurement are not affected by the size of the first IC component becoming larger and the area cost of the alignment pattern can be reduced.

[0064] Other features and processes can also be included. For example, test structures can be incorporated to facilitate verification testing of the 3D package or 3DIC device. The test structures can include, for example, test pads formed on a redistribution layer or a substrate that allow for testing of the 3D package or 3DIC, use of probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.

[0065] According to some embodiments, a semiconductor structure includes a first IC member and a second IC member below and electrically coupled to the first IC member. The first IC member includes a first bonding structure and a first alignment pattern, the first bonding structure includes a first bonding dielectric layer and a first bonding feature disposed in the first bonding dielectric layer, and the first alignment pattern is disposed in the first bonding dielectric layer. The second IC member includes a second bonding structure and a second alignment pattern, the second bonding structure includes a second bonding dielectric layer bonded to the first bonding dielectric layer and a second bonding feature disposed in the second bonding dielectric layer and bonded to the first bonding feature, and the second alignment pattern is disposed in the second bonding dielectric layer and aligned with the first alignment pattern in a staggered manner. In a top view, the second alignment pattern is disposed within a boundary of the first IC member.

[0066] In some embodiments, bonding surfaces of the first bonding dielectric layer and the first bonding feature are substantially planar with bonding surfaces of the first alignment pattern bonded to the second bonding dielectric layer. In some embodiments, bonding surfaces of the second bonding dielectric layer and the second bonding feature are substantially planar with bonding surfaces of the second alignment pattern bonded to the first bonding dielectric layer. In some embodiments, the semiconductor structure further includes an insulative encapsulation disposed on the second integrated circuit member and laterally covering the first integrated circuit member. In some embodiments, the first integrated circuit member further includes a semiconductor substrate disposed above the first bonding structure and a substrate via extending through the semiconductor substrate and electrically coupled to the first bonding feature. In some embodiments, the first bonding dielectric layer includes a first portion and a second portion, the first bonding feature is disposed in the first portion, and the first alignment pattern is disposed in the second portion, wherein a thickness of the second portion is less than a thickness of the first portion. In some embodiments, the semiconductor structure further includes an insulative encapsulation disposed on the second integrated circuit member and covering the first integrated circuit member, the insulative encapsulation including a protruding portion extending into a void between the second bonding dielectric layer and the second portion of the first bonding dielectric layer. In some embodiments, the insulative encapsulation is in physical contact with the first alignment pattern and the second alignment pattern. In some embodiments, the first bonding dielectric layer includes a first sublayer and a second sublayer connected to the first sublayer and the second bonding dielectric layer, and the first alignment pattern includes a first level pattern in the first sublayer and a second level pattern in the second sublayer and vertically aligned with the first level pattern. In some embodiments, the first level pattern of the first alignment pattern is vertically spaced apart from the second level pattern by the second sublayer of the first bonding dielectric layer. In some embodiments, each of the first level pattern and the second level pattern of the first alignment pattern includes a landing portion and a via portion, and the via portion of the second level pattern is connected to the landing portion of the second level pattern and the landing portion of the first level pattern.

[0067] According to some alternative embodiments, a semiconductor structure includes a first IC component and a second IC component under the first IC component and electrically coupled to the first IC component. The second IC component has a size greater than a size of the first IC component. The first IC component includes a first functional region, a first alignment region outside the first functional region, and a first alignment pattern disposed within the first alignment region. The second IC component includes a second functional region electrically coupled to the first functional region, a second alignment region outside the second functional region and overlapping the first alignment region in a stacking direction of the first IC component and the second IC component, and a second alignment pattern disposed within the second alignment region and aligned with the first alignment pattern in the stacking direction in a staggered manner. The first alignment pattern and the second alignment pattern are electrically floating.

[0068] In some embodiments, the first integrated circuit component further includes a first bonding dielectric layer disposed throughout the first functional region and the first alignment region, wherein the first alignment pattern is disposed in the first bonding dielectric layer, and a first bonding feature disposed in the first bonding dielectric layer within the first functional region, the first bonding feature electrically coupled to the second integrated circuit component. In some embodiments, bonding surfaces of the first bonding dielectric layer and the first bonding feature are substantially planar with bonding surfaces of the first alignment pattern. In some embodiments, a bonding interface of the first integrated circuit component and the second integrated circuit component is substantially planar and free of solder material. In some embodiments, the semiconductor structure further includes an insulative encapsulation disposed on the second integrated circuit component and covering the first integrated circuit component, the insulative encapsulation including a protruding portion vertically interposed between the first alignment region and the second alignment region.

[0069] According to some alternative embodiments, a method of manufacturing a semiconductor structure includes providing a first IC component, providing a second IC component, and bonding the first IC component to the second IC component. The first IC component includes a first bonding structure and a first alignment pattern, the first bonding structure including a first bonding dielectric layer and a first bonding feature disposed in the first bonding dielectric layer, and the first alignment pattern disposed in the first bonding dielectric layer. The second IC component includes a second bonding structure and a second alignment pattern, the second bonding structure including a second bonding dielectric layer bonded to the first bonding dielectric layer and a second bonding feature disposed in the second bonding dielectric layer and bonded to the first bonding feature, and the second alignment pattern disposed in the second bonding dielectric layer. The first IC component is bonded to the second IC component through the first alignment pattern and the second alignment pattern. After bonding the first IC component to the second IC component, the second alignment pattern is aligned with the first alignment pattern in a staggered manner, and in a top-down view, the second alignment pattern is disposed within a boundary of the first IC component.

[0070] In some embodiments, bonding the first integrated circuit component to the second integrated circuit component includes aligning the first alignment pattern of the first integrated circuit component with the second alignment pattern of the second integrated circuit component, contacting the first bonding feature of the first integrated circuit component with the second bonding feature of the second integrated circuit component, and annealing the first bonding feature and the second bonding feature to form a metal-to-metal bond at an interface of the first integrated circuit component and the second integrated circuit component. In some embodiments, the method of manufacturing further includes forming an insulative encapsulation on the second integrated circuit component to laterally cover the first integrated circuit component after bonding the first integrated circuit component to the second integrated circuit component. In some embodiments, providing the first integrated circuit component includes recessing a region of a bonding dielectric material to form the first bonding dielectric layer, the first bonding dielectric layer including a first portion and a second portion that is thinner than the first portion, forming the first bonding feature in the first portion of the first bonding dielectric layer, and forming the first alignment pattern in the second portion of the first bonding dielectric layer.

[0071] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, and are not intended to limit the present application; even though the above-described embodiments of the present application have been described in detail, those skilled in the art should understand that the technical solutions recorded in the above-described embodiments can still be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized by, comprising: a first integrated circuitry member comprising: a first bonding structure comprising a first bonding dielectric layer and a first bonding feature disposed in the first bonding dielectric layer; and a first alignment pattern disposed in the first bonding dielectric layer; and a second integrated circuitry member below and electrically coupled to the first integrated circuitry member, the second integrated circuitry member comprising: a second bonding structure comprising a second bonding dielectric layer bonded to the first bonding dielectric layer and a second bonding feature disposed in the second bonding dielectric layer and bonded to the first bonding feature; and a second alignment pattern disposed in the second bonding dielectric layer and aligned with the first alignment pattern in a staggered manner, wherein the second alignment pattern is disposed within a boundary of the first integrated circuitry member in a top-down view.

2. The semiconductor structure of claim 1, wherein, wherein bonding surfaces of the first bonding dielectric layer and the first bonding feature are substantially flush with bonding surfaces of the first alignment pattern bonded to the second bonding dielectric layer.

3. The semiconductor structure of claim 1, wherein, wherein bonding surfaces of the second bonding dielectric layer and the second bonding feature are substantially flush with bonding surfaces of the second alignment pattern bonded to the first bonding dielectric layer.

4. The semiconductor structure of claim 1, wherein, further comprising: an insulative encapsulation disposed on the second integrated circuitry member and laterally covering the first integrated circuitry member.

5. The semiconductor structure of claim 1, wherein, wherein the first integrated circuitry member further comprises a semiconductor substrate disposed above the first bonding structure and a substrate via through the semiconductor substrate and electrically coupled to the first bonding feature.

6. The semiconductor structure of claim 1, wherein, wherein the first bonding dielectric layer comprises a first portion and a second portion, the first bonding feature is disposed in the first portion, and the first alignment pattern is disposed in the second portion, wherein a thickness of the second portion is less than a thickness of the first portion.

7. The semiconductor structure of claim 1, wherein, wherein: the first bonding dielectric layer comprises a first sub-layer and a second sub-layer connected to the first sub-layer and the second bonding dielectric layer, and the first alignment pattern comprises a first level pattern in the first sub-layer and a second level pattern in the second sub-layer and aligned perpendicularly with the first level pattern.

8. A semiconductor structure, characterized by comprising: a first integrated circuitry member comprising a first functional region, a first alignment region outside the first functional region, and a first alignment pattern disposed within the first alignment region; and a second integrated circuitry member below and electrically coupled to the first integrated circuitry member, the second integrated circuitry member having a size greater than a size of the first integrated circuitry member, and the second integrated circuitry member comprising: a second functional region electrically coupled to the first functional region; a second alignment region outside the second functional region and overlapping the first alignment region in a stacking direction of the first integrated circuitry member and the second integrated circuitry member; and a second alignment pattern disposed within the second alignment region and aligned with the first alignment pattern in a staggered manner in the stacking direction, wherein the first alignment pattern and the second alignment pattern are electrically floating.

9. The semiconductor structure of claim 8, wherein, wherein the first integrated circuitry member further comprises: a first bonding dielectric layer disposed across the first functional region and the first alignment region, wherein the first alignment pattern is disposed in the first bonding dielectric layer; and a first bonding feature disposed in the first bonding dielectric layer within the first functional region, the first bonding feature electrically coupled to the second integrated circuit member.

10. The semiconductor structure of claim 8, wherein, Also included are: an insulative encapsulation disposed on the second integrated circuit member and covering the first integrated circuit member, the insulative encapsulation including a protruding portion that is vertically interposed between the first alignment region and the second alignment region.

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