Chip packaging structure and electronic equipment

Abstract

The embodiment of the utility model discloses a chip packaging structure and electronic equipment. The chip packaging structure comprises a substrate, a packaging shell, a chip set and fluororubber. A containing cavity is defined by the packaging shell and the substrate, and a through hole communicating the interior of the containing cavity with the exterior of the packaging shell is formed in the packaging shell. The chip set is located in the containing cavity, and the fluororubber wraps the chip set. In the thickness direction of the substrate, the fluorine rubber is recessed towards the substrate to form a recessed portion, the position, away from the substrate, of the recessed portion with the smallest distance from the substrate is a first preset position, the position, away from the substrate, of the chip set with the largest distance from the substrate is a first reference position, and the first preset position is far away from the substrate compared with the first reference position. The vertical distance between the first preset position and the first reference position is larger than 0 micrometer and smaller than 500 micrometers. According to the invention, the first reference position is taken as a reference, and the first preset position is reasonably adjusted, so that the lowest point of the fluororubber and the minimum thickness of the fluororubber are accurately controlled, and the phenomenon of rubber climbing is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor package, in particular to a chip package structure and electronic equipment. BACKGROUND

[0002] At present, the application scene of semiconductor chip is more and more extensive, when using in some acid-base or other corrosive gas and liquid environment, the anticorrosion ability requirement of semiconductor device is higher. In order to improve the waterproof performance, anticorrosion performance of semiconductor chip, the inside of the package shell is usually filled with silica gel, the semiconductor chip in the package shell is wrapped by silica gel, so as to isolate the acid-base or corrosive gas and liquid in the external environment, protect the chip from corrosion and water vapor, and improve the long-term stability and reliability of the chip.

[0003] However, under some extreme conditions (such as high temperature, strong alkaline environment), silica gel may be corroded and decomposed, therefore, in order to ensure the air tightness and anticorrosion performance of the chip, more silica gel needs to be filled in the packaging process. Before solidification, the glue may produce "glue climbing" phenomenon due to high fluidity, that is, the glue diffuses along the inner wall of the package shell and climbs to the top of the shell. This phenomenon may cause many adverse effects on the subsequent process in actual application. For example, in the sealing test, the glue may bond the product and the test cover, resulting in detection failure; in the surface mount (SMT) process, the glue may bond the product and the suction nozzle, interfering with the normal pickup and installation of the chip. SUMMARY

[0004] The embodiment of the utility model provides a chip package structure to effectively avoid the phenomenon that glue climbs out of the package shell when the chip is packaged.

[0005] In order to solve the above technical problem, the embodiment of the utility model discloses the following technical scheme:

[0006] On the one hand, a chip package structure is provided, comprising:

[0007] a substrate;

[0008] a package shell fixed on the substrate, which forms a containing cavity together with the substrate, a through hole is arranged on the side of the package shell away from the substrate, and the through hole communicates the containing cavity and the outside of the package shell;

[0009] a chip set fixed on the substrate and located in the containing cavity;

[0010] fluorine glue filled in the containing cavity and covering the chip set;

[0011] The fluorine glue forms a recessed portion in the thickness direction of the substrate, the side surface of the recessed portion away from the substrate has a first preset position, the side of the chip set away from the substrate has a first reference position, the first preset position is farther away from the substrate than the first reference position, and the vertical distance between the first preset position and the first reference position is greater than 0 um and less than 500 um.

[0012] In addition to one or more features disclosed above, or as an alternative, the side surface of the package shell away from the substrate is provided with a waist portion, and the waist portion surrounds the port of the through hole away from the substrate.

[0013] In addition to one or more features disclosed above, or as an alternative, the fluorine glue is adhered to the inner wall of the waist portion, and the projection of the first preset position is located within the projection range of the through hole in the thickness direction of the substrate.

[0014] In addition to one or more features disclosed above, or as an alternative, the projection of the chip set overlaps the projection of the through hole in the thickness direction of the substrate, and the projection of the first preset position does not overlap the projection of the first reference position.

[0015] In addition to one or more features disclosed above, or as an alternative, the chip set includes at least a MEMS chip, an ASIC chip, and a plurality of leads, the MEMS chip and the ASIC chip are electrically connected through leads, and the MEMS chip and the ASIC chip are arranged in layers or spaced apart on the substrate.

[0016] In addition to one or more features disclosed above, or as an alternative, the chip set includes at least a MEMS chip, an ASIC chip, and a plurality of leads, the MEMS chip and the ASIC chip are electrically connected through leads, and are arranged in layers on the substrate.

[0017] In addition to one or more features disclosed above, or as an alternative, the projection of the MEMS chip does not overlap the projection of the through hole in the thickness direction of the substrate, and the projection of the ASIC chip does not overlap the projection of the through hole.

[0018] In addition to one or more features disclosed above, or as an alternative, the chip set includes at least a MEMS chip, an ASIC chip, and a plurality of leads, the MEMS chip and the ASIC chip are electrically connected through leads, and are arranged in layers on the substrate.

[0019] In addition to one or more features disclosed above, or as an alternative, the projection of the chip set does not overlap the projection of the through hole in the thickness direction of the substrate.

[0020] In addition to one or more of the above disclosed features, or as an alternative, the inner wall of the waist portion is provided with a plurality of spaced grooves extending along the thickness direction of the substrate, and the fluorine glue is filled in the interior of the grooves.

[0021] In addition to one or more of the above disclosed features, or as an alternative, the inner wall of the waist portion is provided with a plurality of spaced grooves extending along the thickness direction of the substrate, and the fluorine glue is filled in the interior of the grooves.

[0022] In addition to one or more of the above disclosed features, or as an alternative, the inner wall of the waist portion is provided with a plurality of spaced grooves extending along the thickness direction of the substrate, and the fluorine glue is filled in the interior of the grooves.

[0023] In another aspect, an electronic device is provided, comprising the chip packaging structure of any of the above.

[0024] One of the above technical solutions has the following advantages or beneficial effects: the fluorine glue with excellent waterproofness, corrosion resistance and high temperature resistance is used to replace the traditional silica gel material in the present application. Since the waterproofness, corrosion resistance and high temperature resistance of the fluorine glue are all superior to those of the silica gel, the fluorine glue can not only provide sufficient barrier effect, but also reduce the height of the filled glue, thereby reducing the occurrence of the glue climbing phenomenon. Meanwhile, the present application takes the first reference position (the position where the chip set side away from the substrate is farthest from the substrate, i.e. the highest point of the chip set) as the reference, and adjusts the position of the first preset position (the surface of the recessed part of the fluorine glue away from the substrate is the lowest point of the fluorine glue) reasonably, so as to realize the precise control of the lowest point position of the fluorine glue and the minimum value of the fluorine glue thickness, limit the flow range of the fluorine glue before solidification, and effectively inhibit the fluorine glue from climbing to the top of the packaging shell and the outside, thereby further improving the glue climbing phenomenon. BRIEF DESCRIPTION OF DRAWINGS

[0025] The technical scheme and other beneficial effects of the present application will be apparent from the following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

[0026] Figure 1 is a structural schematic diagram of a chip packaging structure according to an embodiment of the present application Figure 1 ;

[0027] Figure 2 is a structural schematic diagram of a chip packaging structure according to an embodiment of the present application Figure 2 ;

[0028] Figure 3 is a structural schematic diagram of a chip packaging structure according to an embodiment of the present application Figure 3 ;

[0029] Figure 4 is a structural diagram of a chip packaging structure according to an embodiment of the present application Figure 4

[0030] Figure 5 is a structural diagram of a chip packaging structure according to an embodiment of the present application Figure 5

[0031] Legend:

[0032] 10, substrate;

[0033] 20, packaging shell; 21, through hole;

[0034] 30, chip set; 31, first reference position; 32, MEMS chip; 33, ASIC chip; 34, lead;

[0035] 40, fluorine glue; 41, recess; 411, first preset position;

[0036] 50, waist part. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and beneficial effects of the present application clearer, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described in the specification are only for the purpose of explaining the present application, and are not intended to limit the present application.

[0038] In the description of the present application, it should be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like are based on the orientations or positional relationships shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and are not intended to indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0039] ​​In the description of the utility model, it is necessary to explain, unless another explicit provision and limitation, the term "installation", "connection", "connect" should be broad sense understanding, for example, can be fixed connection, can be detachable connection, or integrally connected;Can be mechanical connection, can be directly connected, can be indirectly connected through the intermediate medium, can be two elements inside the communication or the interaction relationship of two elements.For ordinary skilled in the art, the above-mentioned terms can be understood according to the specific meaning of the utility model.

[0040] In the utility model, unless another explicit provision and limitation, the first feature is "on" or "under" the second feature can include the first and second features direct contact, can include the first and second features are not direct contact but contact through the additional features between them.Moreover, the first feature is "on", "above" and "on" the second feature includes the first feature is directly above and obliquely above the second feature, or just indicates that the horizontal height of the first feature is higher than the second feature.The first feature is "under", "below" and "under" the second feature includes the first feature is directly above and obliquely above the second feature, or just indicates that the horizontal height of the first feature is less than the second feature.

[0041] The utility model discloses a kind of chip packaging structures, which includes: substrate 10, packaging shell 20, chip group 30 and fluorine glue 40.Packaging shell 20 is fixed on substrate 10, and is enclosed to form containing cavity with substrate 10, and the side of packaging shell 20 deviating from substrate 10 is equipped with through hole 21, and through hole 21 is communicated with the inside of containing cavity and the outside of packaging shell 20.Chip group 30 is fixed on substrate 10, and is located in containing cavity.Fluorine glue 40 is filled in containing cavity, and covers chip group 30.Specifically, in the thickness direction of substrate 10, fluorine glue 40 is recessed to form recessed portion 41 towards substrate 10, the side surface of recessed portion 41 deviating from substrate 10 and the position of minimum distance with substrate 10 is first preset position 411, the side of chip group 30 deviating from substrate 10 and the position of maximum distance with substrate 10 is first reference position 31, first preset position 411 is compared with first reference position 31 and away from substrate 10, and the vertical distance between first preset position 411 and first reference position 31 is greater than 0um and less than 500 μm (refer to Figure 1 )。

[0042] The fluorine glue with excellent waterproofness, corrosion resistance and high temperature resistance is used to replace the traditional silica gel material in the application. Since the waterproofness, corrosion resistance and high temperature resistance of the fluorine glue are all superior to those of the silica gel, the fluorine glue can not only provide sufficient barrier effect, but also reduce the height of the filling glue, thereby reducing the occurrence of the glue climbing phenomenon. Meanwhile, the first reference position 31 (the position farthest from the substrate 10 on the side of the chip set 30 away from the substrate 10, that is, the highest point of the chip set 30) is taken as the reference, and the position of the first preset position 411 (the surface on the side of the fluorine glue 40 away from the substrate 10 farthest from the substrate 10, that is, the lowest point of the fluorine glue 40) is reasonably adjusted, so that the precise control of the lowest point position of the fluorine glue 40 and the minimum value of the thickness of the fluorine glue 40 is realized, the flow range of the fluorine glue 40 before solidification is limited, and the fluorine glue 40 is effectively inhibited from climbing to the top and outside of the packaging shell 20, thereby further improving the glue climbing phenomenon.

[0043] With reference to the foregoing Figure 1 In some embodiments, the surface on the side of the packaging shell 20 away from the substrate 10 is further provided with a waist portion 50, the waist portion 50 is centrally penetrated, and is arranged around the port of the through hole 21 away from the substrate 10. It should be noted that the waist portion 50 and the packaging shell 20 can be integrally formed, or can be fixedly connected through welding.

[0044] In some embodiments, the substrate 10 is a circuit board, and the chip set 30 is fixed on the substrate 10 and electrically connected with the substrate 10. In detail, the chip set 30 at least includes a MEMS chip 32, an ASIC chip 33 and a plurality of lead wires 34, the MEMS chip 32 and the ASIC chip 33 are electrically connected through the lead wires 34, the ASIC chip 33 is electrically connected with the substrate 10 through the lead wires 34, the MEMS chip 32 is used for receiving an analog signal, and the ASIC chip 33 is used for processing the signal from the MEMS chip 32.

[0045] The first reference position 31 of the chip group 30 can be located on the surface of the MEMS chip 32 or the surface of the ASIC away from the substrate 10, or on the lead 34. Specifically, taking the surface of the substrate 10 carrying the MEMS chip 32 and the ASIC chip 33 as a reference surface, when there is a lead 34 in the plurality of leads 34 that is higher than the MEMS chip 32 and higher than the ASIC chip 33, the highest point of the lead 34 is the first reference position 31; when there is no lead 34 in the plurality of leads 34 that is higher than the MEMS chip 32 and higher than the ASIC chip 33, the distance from the surface of the MEMS chip 32 away from the substrate 10 to the substrate 10 is compared with the distance from the surface of the ASIC away from the substrate 10 to the substrate 10, and when the distance from the surface of the MEMS chip 32 away from the substrate 10 to the substrate 10 is large, the first reference position 31 is located on the surface of the MEMS chip 32 away from the substrate 10, and when the distance from the surface of the ASIC chip 33 away from the substrate 10 to the substrate 10 is large, the first reference position 31 is located on the surface of the ASIC chip 33 away from the substrate 10.

[0046] Referring to Figure 1 and Figure 2 In the first embodiment disclosed in the present application, the fluorine glue 40 is adhered to the inner wall of the waist 50, and in the thickness direction of the substrate 10, the projection of the first preset position 411 is located within the projection range of the through hole 21, in other words, the recessed part 41 of the fluorine glue 40 is also located within the projection range of the through hole 21. The projection of the chip group 30 overlaps the projection of the through hole 21, and the projection of the first reference position 31 also overlaps the projection of the through hole 21, and specifically, at this time, the MEMS chip 32 and the ASIC chip 33 included in the chip group 30 can be in a structure stacked on the substrate 10 or in a structure spaced apart from the substrate 10. It should be noted that in the first embodiment, although the first preset position 411 and the first reference position 31 are both located within the projection range of the through hole 21, the first preset position 411 and the first reference position 31 can overlap or not overlap. It should also be noted that although the first reference position 31 is located on the lead 34 that is higher than the MEMS chip 32 and higher than the ASIC chip 33 in the first embodiment, when there is no lead 34 in the plurality of leads 34 that is higher than the MEMS chip 32 and higher than the ASIC chip 33, the first reference position 31 can be located on the surface of the MEMS chip 32 or the surface of the ASIC chip 33. Figure 1 and Figure 2 In the first embodiment, when there is no lead 34 in the plurality of leads 34 that is higher than the MEMS chip 32 and higher than the ASIC chip 33, the first reference position 31 can be located on the surface of the MEMS chip 32 or the surface of the ASIC chip 33.

[0047] Referring to Figure 4In the second embodiment disclosed in the present application, the MEMS chip 32 and the ASIC chip 33 are arranged on the substrate 10 in a spaced manner, and the projection of the MEMS chip 32 and the projection of the through hole 21 do not overlap in the thickness direction of the substrate 10, and the projection of the ASIC chip 33 and the projection of the through hole 21 do not overlap. In the second embodiment disclosed in the present application, the MEMS chip 32 and the ASIC chip 33 can be better wrapped by the fluorine glue 40. In actual cases, generally, the height of the MEMS chip 32 is greater than the height of the ASIC chip 33. If the height (the distance from the side of the MEMS chip 32 or the ASIC chip 33 or the lead 34 away from the substrate 10 to the substrate 10) of the lead 34 connecting the MEMS chip 32 and the ASIC chip 33 is reasonably controlled, so that there is no lead 34 both higher than the MEMS chip 32 and higher than the ASIC chip 33 in the plurality of leads 34, the first reference position 31 is located on the side surface of the MEMS chip 32 away from the substrate, and the vertical distance between the first preset position 411 and the first reference position 31 can be controlled to be close to 0 um. In this way, the fluorine glue 40 can not only provide sufficient barrier effect for the chip set 30, but also effectively avoid the fluorine glue 40 climbing to the top of the packaging shell 20 and the outside.

[0048] With reference to Figure 5 In the third embodiment disclosed in the present application, the MEMS chip 32 and the ASIC chip 33 are arranged on the substrate 10 in a stacked manner, and the projection of the chip set 30 and the projection of the through hole 21 do not overlap in the thickness direction of the substrate 10 (in other words, the projection of the MEMS chip 32 and the projection of the ASIC chip 33 do not overlap with the projection of the through hole 21). In the third embodiment disclosed in the present application, the MEMS chip 32 and the ASIC chip 33 can also be better wrapped by the fluorine glue 40. In the third embodiment, whether the first reference position 31 is located on the surface of the MEMS chip 32 or on the lead 34, the vertical distance between the first preset position 411 and the first reference position 31 can be controlled to be close to 0 um. In this way, the fluorine glue 40 can not only provide sufficient barrier effect for the chip set 30, but also effectively avoid the fluorine glue 40 climbing to the top of the packaging shell 20 and the outside.

[0049] To further prevent the fluorine glue 40 from climbing, in some embodiments, the inner wall of the waist portion 50 is provided with a plurality of spaced grooves extending along the thickness direction of the substrate 10, and the fluorine glue 40 is filled in the grooves. Or, in some embodiments, the inner wall of the waist portion 50 is further provided with a spiral groove around the axial direction of the waist portion 50. Specifically, the spiral groove spirals on the inner wall of the waist portion 50 from the end of the waist portion 50 away from the substrate 10 to the end of the waist portion 50 close to the substrate 10 along the axial direction of the waist portion 50. It should be noted that one of the main driving forces for the fluorine glue 40 to climb is the surface tension. The inner wall of the waist portion 50 is provided with the extending grooves or the spiraling spiral groove, which can break the continuous distribution of the fluorine glue 40 on the inner wall of the waist portion 50, form a plurality of “break points”, weaken the overall force of the surface tension, and reduce the climbing ability of the fluorine glue 40. At the same time, the grooves or the spiral groove also provide additional accommodation space, so that part of the fluorine glue 40 can enter, thereby reducing the volume and height of the fluorine glue 40 on the inner wall of the waist portion 50, and further inhibiting the climbing.

[0050] Further, with reference to Figure 3 In some embodiments, the climbing of the fluorine glue 40 is further prevented by changing the inner diameter of the waist portion 50. Specifically, the inner diameter of the end of the waist portion 50 away from the through hole 21 is smaller than the inner diameter of the end of the waist portion 50 close to the through hole 21. The narrowing of the inner diameter reduces the surface tension range of the fluorine glue 40, so that the fluorine glue 40 is more difficult to overcome the geometric limitation and climb to a higher position.

[0051] It should be noted that the above measures for further preventing the fluorine glue 40 from climbing can be applied in any embodiment disclosed in the present application alone or in combination.

[0052] The electronic device provided by the embodiments of the present application includes any of the chip packaging structures described above, and can be a waterproof pressure measuring device, a barometer, or other products for detecting pressure.

[0053] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0054] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A chip package structure, characterized by, The package comprises: a substrate (10); a package shell (20) fixed on the substrate (10) and cooperatively enclosing a receiving cavity with the substrate (10), the package shell (20) being provided with a through hole (21) on a side away from the substrate (10), the through hole (21) communicating the receiving cavity and the outside of the package shell (20); a chip set (30) fixed on the substrate (10) and located in the receiving cavity; a fluorine glue (40) filled in the receiving cavity and covering the chip set (30); wherein, in the thickness direction of the substrate (10), the fluorine glue (40) is recessed to form a recess (41) towards the substrate (10), the position where the side surface of the recess (41) away from the substrate (10) is closest to the substrate (10) is a first preset position (411), the position where the side of the chip set (30) away from the substrate (10) is farthest from the substrate (10) is a first reference position (31), the first preset position (411) is farther away from the substrate (10) than the first reference position (31), and the vertical distance between the first preset position (411) and the first reference position (31) is greater than 0 um and less than 500 um.

2. The chip package structure of claim 1, wherein, The side surface of the package shell (20) away from the substrate (10) is provided with a waist portion (50), and the waist portion (50) is arranged around the port of the through hole (21) away from the substrate (10).

3. The chip package structure of claim 2, wherein, The fluorine glue (40) is adhered to the inner wall of the waist portion (50), and in the thickness direction of the substrate (10), the projection of the first preset position (411) is located within the projection range of the through hole (21).

4. The chip package structure of claim 3, wherein, In the thickness direction of the substrate (10), the projection of the chip set (30) overlaps the projection of the through hole (21), and the projection of the first preset position (411) does not overlap the projection of the first reference position (31).

5. The chip package structure of claim 4, wherein, The chip set (30) comprises at least a MEMS chip (32), an ASIC chip (33) and a plurality of leads (34), the MEMS chip (32) and the ASIC chip (33) are electrically connected through the leads (34), and the MEMS chip (32) and the ASIC chip (33) are arranged in layers or spaced apart on the substrate (10).

6. The chip package structure of claim 1 or 2, wherein, The chip set (30) comprises at least a MEMS chip (32), an ASIC chip (33) and a plurality of leads (34), the MEMS chip (32) and the ASIC chip (33) are electrically connected through the leads (34), and the MEMS chip (32) and the ASIC chip (33) are arranged in layers or spaced apart on the substrate (10); wherein, in the thickness direction of the substrate (10), the projection of the MEMS chip (32) does not overlap the projection of the through hole (21), and the projection of the ASIC chip (33) does not overlap the projection of the through hole (21).

7. The chip package structure of claim 1 or 2, wherein, The chip set (30) comprises at least a MEMS chip (32), an ASIC chip (33) and a plurality of leads (34), the MEMS chip (32) and the ASIC chip (33) are electrically connected through the leads (34) and are stacked on the substrate (10); Wherein, in the thickness direction of the substrate (10), the projection of the chip set (30) does not overlap with the projection of the through hole (21).

8. The chip package structure of claim 2, wherein, The inner wall of the waist portion (50) is provided with a plurality of spaced grooves, the grooves extend along the thickness direction of the substrate (10), and the fluorine glue (40) is filled in the grooves.

9. The chip package structure of claim 2, wherein, The inner wall of the waist portion (50) is provided with a spiral groove around the axial direction of the waist portion (50).

10. The chip package structure of claim 2, wherein, The inner diameter of the end of the waist portion (50) away from the through hole (21) is smaller than the inner diameter of the end of the waist portion (50) toward the through hole (21).

11. An electronic device, comprising: The chip package structure comprises the chip package structure according to any one of claims 1-10.

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