Chip module optical test fixture and test equipment

Abstract

The embodiment of the utility model provides a chip module optical test fixture and test equipment. The jig comprises a carrying platform which comprises a carrying surface and a carrier, and the carrying surface comprises a plane part used for placing the display chip; a first gas channel is formed in the carrier and penetrates out of the carrying surface, and the first gas channel is connected with a vacuum system. The jig is used for installing the chip module, the display chip is fixed through vacuum adsorption force, the display chip can be fixed and disassembled only by controlling the vacuum negative pressure without applying extra acting force, and the risk that the display chip is damaged due to external force application is avoided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display chip testing, and in particular to a chip module optical testing jig and testing equipment. BACKGROUND

[0002] Display chips need to be tested for various performances before being shipped, and for different tests, the display chips need to be provided with corresponding test environments.

[0003] During the testing process, the display chips are usually fixed on a jig, and the conventional fixing method needs to exert an external force on the display chips during fixing and dismounting, which can easily cause damage to the display chips. In addition, when the display chips are fixed by an adhesive, impurities in the adhesive can adversely affect the normal operation of the display chips.

[0004] Therefore, there is a need to develop a new jig. CONTENT OF THE UTILITY MODEL

[0005] To ensure the reliability of the display chip fixation and avoid the risk of damage to the display chip during fixation and dismounting, the present disclosure provides a jig for installing a chip module for optical testing, the chip module comprising a display chip and a driving connection part, the jig comprising: a stage comprising a loading surface and a carrier, the loading surface comprising a planar part for placing the display chip; the carrier is formed with a first gas channel and penetrates the loading surface, so as to fix the display chip on the stage by vacuum adsorption force.

[0006] In some embodiments, the loading surface of the stage further comprises a limiting structure protruding from the planar part, so as to define the placement position of the display chip.

[0007] In some embodiments, the jig further comprises: a heat-conducting pad adapted to be placed between the display chip and the planar part, the heat-conducting pad being provided with a through hole, the position of the through hole corresponding to the position of the first gas channel penetrating the loading surface.

[0008] In some embodiments, the jig further comprises: a connector for interfacing with an optical testing device to place the display chip in the optical testing device, the connector comprising a connector body and an internal channel in the connector body, the connector body comprising two end portions and a side portion, one of the end portions being connected to the stage; the internal channel comprises: a second gas channel and a first extension channel, the second gas channel being in communication with the first gas channel, the first extension channel being adapted to accommodate the driving connection part of the chip module, the first extension channel and the second gas channel being in communication with each other.

[0009] In some embodiments, the other end of the joint body is formed with a blocking portion for defining a position for entering the optical testing device, and the second gas channel and the first extension channel pass through the blocking portion.

[0010] In some embodiments, the blocking portion protrudes from the side of the joint body.

[0011] In some embodiments, the blocking portion is formed with a limiting portion adapted to cooperate with the optical testing device to prevent the joint from rotating.

[0012] In some embodiments, the joint is integrally formed with the carrier.

[0013] In some embodiments, the joint is made of copper or copper alloy, and the carrier is made of copper or copper alloy.

[0014] In some embodiments, the jig further comprises an extension connected to the blocking portion, and the extension is formed with a third gas channel and a second extension channel inside and not in communication with each other, the third gas channel is in communication with the second gas channel and a vacuum system at two ends respectively, the second extension channel is in communication with the first extension channel and adapted to jointly accommodate an extension driving assembly, the extension driving assembly is adapted to electrically connect with a driving connection portion of the chip module, and the extension driving assembly is movable in the second extension channel and the first extension channel.

[0015] In some embodiments, the extension comprises a first portion and a second portion arranged oppositely, and the first portion and / or the second portion is provided with a groove to form the second extension channel.

[0016] In some embodiments, the first portion and the second portion of the extension are detachably connected to each other.

[0017] In some embodiments, a surface of the first portion facing the second portion is provided with a first fixed magnet, a surface of the second portion facing the first portion is provided with a second fixed magnet, the first fixed magnet and the second fixed magnet are correspondingly arranged, and the first fixed magnet and the second fixed magnet are adapted to be attracted to each other to fix the first portion and the second portion to each other.

[0018] In some embodiments, the blocking portion and the joint are fixed by a fastener.

[0019] The embodiments of the present disclosure further provide a testing device for optically testing a chip module, the testing device comprising: any of the jigs; and an optical testing device for testing optical performance of a display chip, and the jig is adapted to be connected with the optical testing device to fix the display chip in the optical testing device.

[0020] In some embodiments, the optical testing device comprises an entrance, and the joint of the jig is adapted to enter the optical testing device through the entrance.

[0021] In some embodiments, the testing apparatus further comprises a fixing structure arranged on the surface of the testing device and located near the entrance, and the fixing structure is adapted to cooperate with the limiting part on the blocking part of the jig to prevent the joint of the jig from rotating after entering the optical testing device.

[0022] In some embodiments, the optical testing device is an integrating sphere testing device.

[0023] Compared with the prior art, the technical scheme of the embodiments of the present disclosure has the following beneficial effects:

[0024] The carrier of the platform of the jig of the embodiments of the present disclosure is formed with a first gas channel and the first gas channel penetrates the loading surface, and the planar part of the loading surface is used for placing the display chip, so that the display chip can be fixed on the platform by vacuum adsorption force, so as to perform optical testing on the display chip; by fixing the display chip by vacuum adsorption force, the display chip is only required to be controlled by the size of vacuum negative pressure for fixing and dismounting, without the need of applying additional force, thereby avoiding the risk of damaging the display chip due to the application of external force.

[0025] Further, the jig further comprises a heat-conducting pad adapted to be placed between the display chip and the planar part of the loading surface, which is beneficial to conduct the heat generated by the display chip when emitting light; the heat-conducting pad is provided with a through hole, and the position of the through hole corresponds to the position of the first gas channel penetrating the loading surface, so that the display chip is fixed by vacuum adsorption force at the same time, and the air flow around the display chip caused by the vacuum adsorption force carries away the heat generated during the testing of the display chip, and the heat-conducting pad and the air flow are beneficial to faster conducting or dissipating the heat generated by the display chip, thereby avoiding the accumulation of heat to cause temperature rise and affect the testing or damage the display chip.

[0026] Further, the loading surface of the platform further comprises a limiting structure protruding from the planar part, which is used for limiting the placement position of the display chip, and by the limiting structure, the display chip can be limited to the same position in multiple tests, so that the light emitting direction of the display chip is the same, so as to ensure the accuracy, consistency and reproducibility of the testing.

[0027] The test equipment of the embodiment of the present disclosure comprises an optical testing device for testing the optical performance of a display chip and a jig of the embodiment of the present disclosure, the jig is adapted to be connected with the optical testing device to fix the display chip in the optical testing device for testing, and the jig fixes the display chip by vacuum adsorption force, and only the vacuum negative pressure size needs to be controlled for fixing and dismounting the display chip, without exerting additional force, thereby avoiding the risk of damaging the display chip due to exerting external force.

[0028] Further, the test equipment comprises a fixing structure arranged on the surface of the optical testing device, the fixing structure is adapted to cooperate with the limiting part on the blocking part of the jig to prevent the joint of the jig from rotating after entering the optical testing device, so that the relative position of the jig and the optical testing device is fixed, so that the display chip emits light at the same position and angle in the optical testing device when the display chip is tested, thereby improving the accuracy of the test and ensuring the consistency and reproducibility of the test. BRIEF DESCRIPTION OF DRAWINGS

[0029] Other features and advantages of the present disclosure will be better understood through the following detailed description of the optional embodiments with reference to the accompanying drawings, wherein the same reference signs represent the same or similar components, and wherein:

[0030] Figure 1 A side view structural schematic diagram of a jig according to an embodiment of the present disclosure is shown.

[0031] Figure 2 A top view structural schematic diagram of a jig according to an embodiment of the present disclosure is shown.

[0032] Figure 3 A side view structural schematic diagram of a test equipment according to an embodiment of the present disclosure is shown.

[0033] Figure 4 A schematic diagram of the connection between the jig of a test equipment and an optical testing device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0034] The embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the drawings, the same or similar reference signs represent the same or similar elements or elements having the same or similar functions. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present disclosure, and cannot be understood as a limitation of the present disclosure.

[0035] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning to those of a person skilled in the art to which this disclosure belongs. In the description of this disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this disclosure and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting this disclosure.

[0036] To ensure the reliability of the display chip fixation and avoid damage to the display chip caused by additional force during fixation and disassembly, the embodiment of the present disclosure provides a jig for mounting a chip module for optical testing, the chip module comprising a display chip and a driving connection part, the jig comprising: a carrier comprising a carrier surface and a carrier body extending from the carrier surface, the carrier surface comprising a flat part for placing the display chip; a first gas channel is formed in the carrier body and penetrates the carrier surface, so as to fix the display chip on the carrier by vacuum adsorption force.

[0037] The embodiment of the present disclosure will be described in detail below in conjunction with the drawings.

[0038] Figure 1 A cross-sectional structure schematic diagram of a jig according to an embodiment of the present disclosure is shown, Figure 2 A top view cross-sectional structure schematic diagram of a jig according to an embodiment of the present disclosure is shown. Reference Figure 1 and Figure 2 The jig 1 of the embodiment of the present disclosure is used for mounting a chip module 2 for optical testing, and the jig 1 comprises a carrier 11, the carrier 11 comprising a carrier surface 111 and a carrier body 112 extending from the carrier surface 111, the carrier surface 111 comprising a flat part for smoothly placing the chip module 2. In order to clearly show the purpose of the jig 1 of the present disclosure, the chip module 2 is shown in the diagram, which should not be overly limited to the protection scope of the present disclosure.

[0039] Generally, the chip module 2 comprises a display chip 21 and a driving connection part 22, the display chip 21 is electrically connected with the driving connection part 22, and the driving connection part 22 is electrically connected with an external power supply, so that a driving signal can be transmitted to the display chip 21 through the driving connection part 22 to drive it to emit light. The embodiment of the present disclosure places the display chip 21 on the flat part of the carrier surface 11 and then fixes it on the carrier 11 by vacuum adsorption force, so as not to cause damage to the display chip 21.

[0040] Continuing to refer to Figure 1 and Figure 2The first gas passage 113 is formed in the carrier 112, penetrates the carrier surface 111, and is adapted to communicate with a vacuum system. By opening the vacuum system, the display chip 21 is fixed on the carrier 11 by virtue of vacuum adsorption force, thereby completing the installation of the display chip 21. When the vacuum system is closed, the vacuum adsorption force disappears, and the display chip 21 is easily separated from the plane of the carrier surface 111. No additional force is needed, and damage to the display chip 21 by external force is avoided.

[0041] In some embodiments, the carrier surface 111 of the carrier 11 further comprises a limiting structure (not shown in the figure) protruding from the plane portion, so as to define the placement position of the display chip 21.

[0042] In some embodiments, one or more limiting structures for placing the display chip 21 are formed on the plane portion of the carrier surface 111. The sizes of different placement positions can be different, so that display chips 21 of different sizes can be placed in the corresponding size placement position, and the installation and testing of display chips 21 of various sizes are suitable.

[0043] In some embodiments, the limiting structure is protrudingly arranged at the edge of the carrier surface 111, and the display chip 21 is placed by abutting against the limiting structure and is fixed by vacuum adsorption force.

[0044] In some optical tests, it is necessary to keep the position of the display chip 21 fixed and the light-emitting direction fixed. By limiting the placement position of the display chip 21 by the limiting structure, the display chip 21 can be limited to the same position in multiple tests, and the light-emitting direction of the display chip 21 is the same, so as to ensure the accuracy, consistency and reproducibility of the test.

[0045] With reference to Figure 1 and Figure 2 The jig 1 further comprises a heat-conducting pad 12 arranged on the plane portion of the carrier surface 111, adapted to be placed between the display chip 21 and the plane portion, and is conducive to the heat generated by the display chip 21 when emitting light being conducted out.

[0046] In some embodiments, the heat-conducting pad 12 is provided with a through hole, the position of the through hole corresponds to the position of the first gas passage 113 penetrating the carrier surface 111, and the display chip 21 covers the position of the through hole, so that the display chip 21 can be fixed by vacuum adsorption force. The vacuum adsorption force causes the air around the display chip 21 to flow and thus take away the heat generated by the display chip 21 during testing. The heat-conducting pad 12 and the air flow are conducive to the heat generated by the display chip 21 being conducted out or dissipated more quickly, avoiding the accumulation of heat to cause temperature rise and affect the test or damage the display chip 21.

[0047] In some embodiments, the material of the heat-conducting pad 12 is heat-conducting silica gel.

[0048] In some embodiments, the chip module 2 further comprises a back plate arranged on the back of the display chip 21, i.e. the back plate is arranged on the non-light-emitting side of the display chip 21, and the back plate is placed on the corresponding position of the through hole of the heat-conducting pad 12, so that the vacuum suction force acts on the back plate. The arrangement of the back plate helps to prevent adverse effects on the register read-write function, display function, current delivery function, etc. of the display chip 21 when the vacuum suction force is too large.

[0049] With reference to Figure 1 and Figure 2 , the jig 1 further comprises a connector 13 for interfacing with an optical testing device to place the display chip 21 in the optical testing device for testing. The connector 13 comprises a connector body 131 and an internal passage in the connector body 131. The connector body 131 comprises two end portions and a side portion, and one of the end portions of the connector body 131 is connected to the stage 11. The internal passage comprises a second gas passage 132 and a first extension passage 133. The second gas passage 132 is in communication with the first gas passage 113, and the first extension passage 133 is adapted to accommodate the driving connection portion 22 of the chip module 2. The first extension passage 133 is not in communication with the second gas passage 132, so as to avoid affecting the size of the vacuum suction force acting on the display chip 21.

[0050] In some embodiments, the connector 13 and the stage 11 are integrally formed; in some embodiments, the cross sections of the first gas passage 113 and the second gas passage 132 are circular or rectangular, and the sizes thereof are determined according to actual conditions.

[0051] In some embodiments, the materials of the connector 13 and the stage 11 are materials with good heat conduction performance. The heat-conducting pad 12, the stage 11 and the connector 13 form a structure that has a heat dissipation effect on the display chip 21 as a whole, so that the heat generated by the display chip 21 during light emission can be conducted to the stage 11 and the connector 13 via the heat-conducting pad 12 and then dissipated.

[0052] In some embodiments, the materials of the connector 13 and the stage 11 are metals; in some embodiments, the materials of the connector 13 and the stage 11 are copper or copper alloy.

[0053] With reference to Figure 1 , the other end of the connector body 131 is formed with a blocking portion 14 for defining the connection position of the jig 1 with the optical testing device, and for specifically defining the position of the connector body 131 entering the optical testing device.

[0054] In some embodiments, the blocking portion 14 protrudes from the side of the joint body 131. In some embodiments, the protruding direction of the blocking portion 14 from the side of the joint body 131 is perpendicular to the direction of the joint body 131 entering the optical testing device. When the jig 1 is connected to the optical testing device, the joint body 131 enters the optical testing device to fix the display chip 21 placed on the plane portion of the loading surface 111 and adsorbed by the vacuum adsorption force in the optical testing device. The blocking portion 14 abuts against the optical testing device and is adapted to be fixed with the optical testing device, thereby defining the connection position of the jig 1 and the optical testing device.

[0055] Referring to Figure 2 In some embodiments, a limiting portion 141 is formed on the blocking portion 14 and is adapted to cooperate with a corresponding fixing structure on the optical testing device to prevent the joint 13 from rotating, thereby fixing the light emitting direction of the display chip 21 in the optical testing device.

[0056] Referring to Figure 1 In some embodiments, the second gas passage 132 penetrates through the blocking portion 14, and the first extension passage 133 penetrates through the blocking portion 14 and does not communicate with the second gas passage 132, so as to ensure the air tightness of the second gas passage 132.

[0057] In some embodiments, the blocking portion 14 and the joint 13 are fixed by fasteners; in some embodiments, the blocking portion 14 and the joint 13 are connected by an adhesive.

[0058] In some embodiments, a sealing structure such as a sealing ring, a sealing gasket or the like is arranged at the connection between the blocking portion 14 and the joint 13, so as to prevent air from entering the second gas passage 132 through the gap at the connection during vacuum adsorption, thereby affecting the size of the vacuum adsorption force on the display chip 21.

[0059] In some embodiments, the jig 1 further comprises an extension driving assembly 16, the first extension passage 133 of the joint 13 is adapted to accommodate the extension driving assembly 16, one end of the extension driving assembly 16 is used for electrical connection with the driving connection portion 22 of the chip module 2, and the other end is electrically connected with an external power supply or a control circuit board, so that the driving signal is transmitted from the extension driving assembly 16 to the display chip 21 via the driving connection portion 22 to drive the display chip 21 to emit light.

[0060] In some embodiments, the driving connection portion 22 of the chip module 2 is a flexible printed circuit (FPC), and the extension driving assembly 16 is also a flexible printed circuit (FPC). The flexible design provides higher freedom for the transmission and electrical connection of the driving signal of the display chip 21, which is beneficial to increase the space utilization and reduce the overall volume of the jig 1.

[0061] With reference to the foregoing Figure 1 And Figure 2 In some embodiments, the jig 1 further comprises an extension part 15, which is connected with the blocking part 14.

[0062] In some embodiments, the extension part 15 is internally formed with a third gas channel 151 and a second extension channel, which are not in communication with each other. The third gas channel 151 is in communication with the second gas channel 132 and the vacuum system, respectively. In some embodiments, the second extension channel is in communication with the first extension channel 133 and is adapted to jointly accommodate the extension driving assembly 16, which is capable of moving within the second extension channel and the first extension channel 133, thereby making it more convenient to mount the chip module 2 with the jig 1.

[0063] With reference to the foregoing Figure 2 In some embodiments, the extension part 15 comprises two component parts; in some embodiments, the extension part 15 comprises a first part 152 and a second part 153, which are oppositely arranged and adapted to be connected with each other to accommodate the extension driving assembly 16 and provide protection and support for the extension driving assembly 16. The extension part 15 is beneficial to prevent the extension driving assembly 16 from being eroded by external liquid such as water, and to prevent the extension driving assembly 16 from being damaged due to lack of support force when the extension driving assembly 16 is relatively long in size. For the sake of clarity in showing the structure and connection relationship between the first part 152 and the second part 153, Figure 2 In some embodiments, the first part 152 and the second part 153 are in a non-connected state for the sake of illustration.

[0064] In some embodiments, a recess is provided in the first part 152 and / or the second part 153, which constitutes the second extension channel to accommodate the extension driving assembly 16; in some embodiments, a recess 155 is provided on the surface of the second part 153 facing the first part 152; in some embodiments, a recess 154 is provided on the surface of the first part 152 facing the second part 153; in some embodiments, recesses are provided on the opposite surfaces of the first part 152 and the second part 153, which are respectively the recess 154 and the recess 155, and the positions of the recess 154 and the recess 155 correspond to each other. When the first part 152 and the second part 153 are fixedly connected with each other, the recess 154 and the recess 155 jointly form the second extension channel.

[0065] In some embodiments, the first part 152 and the second part 153 can be fixed by various ways, such as fastener fixing, buckle fitting, etc.

[0066] In some embodiments, the first part 152 and the second part 153 are fixed by magnetic attraction. For example, the surfaces of the first part 152 and the second part 153 are provided with a plurality of magnets. In some embodiments, the surface of the first part 152 facing the second part 153 is provided with a first fixing magnet 1522, and the surface of the second part 153 facing the first part 152 is provided with a second fixing magnet 1532. The first fixing magnet 1522 and the second fixing magnet 1532 correspond to each other in position and are suitable for mutual attraction to fix the first part 152 and the second part 153 to each other. The magnetic fixing makes the connection and disconnection between the first part 152 and the second part 153 more convenient.

[0067] In some embodiments, the surface of the second part 153 facing the first part 152 is provided with a positioning hole 1521, and the surface of the second part 153 facing the first part 152 is provided with a positioning column 1531. The positioning hole 1521 and the positioning column 1531 correspond to each other in position, and the positioning column 1531 is suitable for entering the positioning hole 1521 to limit the mutual position of the first part 152 and the second part 153 when they are connected.

[0068] In some embodiments, the third gas channel 151 is formed in the first part 152 or the second part 153 of the extension part 15.

[0069] In some embodiments, the jig 1 further comprises a fourth gas channel 17. The fourth gas channel 17 is an extension of the third gas channel 151 and is in communication with the vacuum system.

[0070] In some embodiments, the fourth gas channel 17 is an independent pipeline, and the fourth gas channel 17 and the third gas channel 151 are connected by a vacuum connector 18. The vacuum connector 18 ensures the sealing of the connection between the fourth gas channel 17 and the third gas channel 151. In some embodiments, the vacuum connector 18 is a flange connector, an airtight connector, a magnetic fluid sealing connector, etc. In some embodiments, the vacuum connector 18 is arranged at a port of the third gas channel 151 passing through the extension part 15.

[0071] In some embodiments, in order to control the size of the vacuum suction force, a sealing vacuum valve 19 is arranged on the fourth gas channel 17 to adjust the gas flow through each gas channel and thus adjust the size of the vacuum suction force on the display chip 21.

[0072] In some embodiments, the first gas channel 113, the second gas channel 132, and the third gas channel 151 can all be independent pipelines, or part of them can be independent pipelines.

[0073] In some embodiments, the first gas passage 113 is integrated with the carrier 11, the second gas passage 132 is integrated with the connector 13, and the blocking part 14 is integrated respectively, and the third gas passage 151 is integrated with the extension part 15.

[0074] In some embodiments, the port of one end of the first gas passage 113 is located on the planar part of the carrier surface 111 of the carrier 11, the other end of the first gas passage 113 is connected with the second gas passage 132, the two ends of the second gas passage 132 are connected with the first gas passage 113 and the third gas passage 151 respectively, and the first gas passage 113, the second gas passage 132, and the third gas passage 151 are sequentially connected to form a gas passage in communication with a vacuum system, so that a vacuum adsorption force can be generated by the vacuum system and transmitted to the display chip 21 through the gas passage to fix the display chip 21.

[0075] In some embodiments, the extension direction of the first gas passage 113, the second gas passage 132, and the third gas passage 151 can be set according to actual conditions. In some embodiments, the first gas passage 113 includes a first segment and a second segment connected with each other, the first segment extends along a first direction and passes through the planar part of the carrier surface 111, the first direction is substantially perpendicular to the planar part of the carrier 11, the second segment of the first gas passage 113 extends along a second direction, the second direction is perpendicular to the first direction, the second segment is connected with the second gas passage 132, and the second gas passage 132 and the third gas passage 151 extend along the second direction.

[0076] The embodiments of the present disclosure also provide a test device for optical testing of a chip module, the test device comprising the jig of any of the above embodiments.

[0077] Figure 3 FIG. 2 shows a side view structural schematic diagram of a test device according to an embodiment of the present disclosure, Figure 4 FIG. 3 shows a connection schematic diagram of a jig and an optical testing device of a test device according to an embodiment of the present disclosure. The following will be described in combination with Figures 3-4 The test device of the embodiments of the present disclosure will be described in detail.

[0078] Reference Figure 3 The test device comprises an optical testing device 3 for testing the optical performance of a display chip and a jig 1 adapted to be connected with the optical testing device 3 to fix the display chip in the optical testing device 3.

[0079] In some embodiments, the connector 13 and the carrier 11 of the jig 1 enter the optical testing device 3, the jig 1 is connected with the optical testing device 3, so that the position of the display chip 21 placed on the carrier 11 and fixed by the vacuum adsorption force is fixed in the optical testing device 3.

[0080] Reference Figure 3 and Figure 4 In some embodiments, the optical testing device 3 comprises an entrance 311, the joint 13 of the fixture 1 is adapted to enter the optical testing device 3 through the entrance 311.

[0081] In some embodiments, the size and shape of the joint 13 of the fixture 1 match the size and shape of the entrance 311; in some embodiments, the entrance 311 is circular and the joint 13 is cylindrical with a corresponding outer diameter.

[0082] Reference Figure 4 In some embodiments, the testing apparatus further comprises a fixing structure 4 disposed on the surface 31 of the optical testing device 3 and located near the entrance 311, which is adapted to cooperate with the limiting part 141 on the blocking part 14 of the fixture 1, thereby preventing the joint 13 of the fixture 1 from rotating after entering the optical testing device 3. The blocking part 14 defines the connection position of the fixture 1 and the optical testing device 3, specifically limits the depth of the display chip 21 entering the optical testing device 3; the limiting part 141 on the blocking part 14 cooperates with the fixing structure 4 to fix the light-emitting direction of the display chip 21; therefore, when the display chip 21 is tested, the display chip 21 emits light at the same position and angle in the optical testing device 3, which improves the accuracy of the test and ensures the consistency and reproducibility of the test.

[0083] In some embodiments, the fixing structure 4 is multiple, and the limiting part 141 on the blocking part 14 can cooperate with different fixing structures 4 to make the display chip 21 in the optical testing device 3 emit light in different directions, so as to meet the optical testing requirements related to the light-emitting direction.

[0084] In some embodiments, the multiple fixing structures 4 are arranged around the entrance 311.

[0085] In some embodiments, the angle of the joint 13 of the fixture 1 entering the optical testing device 3 is adjusted so that the loading surface of the loading platform 11 is placed horizontally, the display chip 21 is placed on the loading platform 11 with the light-emitting direction upward, and the fixing structure 4 cooperating with the limiting part 141 of the blocking part 14 is arranged above the entrance 311, so that after the fixture 1 is connected and fixed with the optical testing device 3, the light-emitting direction of the display chip 21 is upward; in addition, the gravity is conducive to the position fixation of the horizontally placed display chip 21.

[0086] In some embodiments, the testing apparatus further comprises a vacuum system 5, which is used to provide vacuum negative pressure adsorption force, and by adjusting the negative pressure size and sealing the vacuum valve 19, the size of the vacuum adsorption force on the display chip 21 is controlled.

[0087] In some embodiments, the optical testing device 3 is an integrating sphere testing device, which can be used to test a plurality of optical parameters of the display chip 21, such as luminous intensity, luminous flux, peak wavelength and dominant wavelength, half-width, optical power, and the like.

[0088] Preferably, the display chip 21 provided by the present application is a micro display chip, and the size of each micro light emitting diode chip is not more than 1 cm, preferably not more than 20 microns. The micro light emitting diode structure is formed in an array in the micro light emitting diode chip, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro light emitting diode structure is in the nanometer level, for example, 20 nm to 100 nm.

[0089] In some embodiments, the micro light emitting diode array can include a single layer of micro light emitting diode structures. In some embodiments, the pitch of the micro light emitting diode array, i.e., the minimum center-to-center distance between the micro light emitting diodes, can be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on the micro light emitting diode chip can be between several thousand and several million.

[0090] In some embodiments, the micro light emitting diodes can be arranged in a regular or irregular manner on the driving backplane as pixel points of the micro light emitting diode chip.

[0091] In some embodiments, the driving backplane can be electrically connected to each micro light emitting diode in the micro light emitting diode array through a separate metal interconnection. In some embodiments, each micro light emitting diode can be individually electrically controlled by the driving backplane. In some embodiments, the driving backplane can be electrically connected to the electrodes of the micro light emitting diode chip through a metal interconnection. In some embodiments, the driving backplane is an IC backplane.

[0092] In some embodiments, the driving backplane includes a substrate, a panel integrated circuit, and a driving electrode. The panel integrated circuit is located in the substrate and controls the lighting of the micro light emitting diodes; the driving electrode is located in the substrate and at least the upper surface is exposed, and the driving electrode is electrically connected to the panel integrated circuit. Each micro light emitting diode corresponds to a driving electrode, and the micro light emitting diode is located on the driving electrode and is electrically connected to the driving electrode.

[0093] In some embodiments, the material of the drive electrode is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au. In some embodiments, the substrate is a Si substrate. In other embodiments, the substrate is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is about 700 microns thick. A panel integrated circuit forms individual pixel drivers to control the operation of individual single pixel LED devices. The panel integrated circuit includes, for example, complementary metal oxide semiconductor (CMOS) devices or TFT devices, etc. In some embodiments, a dielectric layer can be formed in the gap between the micro-LEDs. In some embodiments, a dielectric layer can also be formed in the gap between the interconnects.

[0094] The micro-LEDs are driven, for example, in a passive matrix (PM) drive, in which the cathodes of all the micro-LEDs of each array are connected together to a cathode line NL, and the same numbered micro-LEDs of each array are connected to a respective anode line PL. The on-off and luminance of each micro-LED can thus be individually controlled by controlling the voltage on the respective cathode and anode lines.

[0095] In some embodiments, the micro-LEDs can be bonded to the surface of the drive backplane through a bonding layer. The drive electrode is electrically connected to the bonding layer, which includes a first metal layer and a second metal layer. In some embodiments, the material of the first metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the second metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn.

[0096] In some embodiments, the micro-LEDs include an epitaxial layer, an ohmic contact layer, a passivation isolation layer, and a top conductive layer.

[0097] For convenience, "upward" is used to mean away from the drive backplane, "downward" to mean toward the drive backplane, and other directional terms such as top, bottom, above, below, directly below, underneath, etc. are interpreted accordingly.

[0098] In some embodiments, the micro-LEDs include an epitaxial layer, an ohmic contact layer, a top conductive layer, and a passivation isolation layer. The ohmic contact layer is on and electrically connected to the bonding layer. The epitaxial layer is disposed on the ohmic contact layer. The passivation isolation layer at least partially coats the side of the epitaxial layer, and the passivation isolation layer is between the epitaxial layer and the top conductive layer. The top conductive layer is on the side and top of the epitaxial layer.

[0099] In some embodiments, the material of the passivation barrier layer is, for example, a solid inorganic material or a plastic material. In some embodiments, the solid inorganic material includes SiO2, Al2O3, Si3N4, SiCN, HfO2, Ta2O5, TiO2, ZrO2, La2O3, MgO, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or any combination thereof. In some embodiments, the plastic material includes a polymer such as SU-8, PermiNex, benzocyclobutene (BCB), or a transparent plastic (resin) including spin-on glass (SOG), or bonding adhesive microresist BCL-1200, or any combination thereof. The passivation barrier layer is transparent to light emitted by the epitaxial layer.

[0100] In some embodiments, the first metal layer of the bonding layer is in direct contact with the ohmic contact layer at the bottom of the epitaxial layer, and the second metal layer is at the bottom of the bonding layer, away from the epitaxial layer, wherein the profile of the first metal layer is smaller than the profile of the second metal layer.

[0101] In some embodiments, the bottom lateral dimension of the epitaxial layer is larger than the top lateral dimension. In some embodiments, the light mesa is stepped or trapezoidal.

[0102] In some embodiments, the epitaxial layer is trapezoidal, not limited to a right trapezoid or an inverted trapezoid. In some embodiments, the inclination angle of the sidewall of the epitaxial layer ranges from 60° to 85°. In one embodiment, the lateral dimension of the bonding layer is larger than the bottom lateral dimension of the epitaxial layer.

[0103] In some embodiments, the epitaxial layer includes a first type epitaxial layer, a second type epitaxial layer, and a light emitting layer therebetween. The first type epitaxial layer is above the light emitting layer, away from the driving backplane, and the second type epitaxial layer is below the light emitting layer, close to the driving backplane.

[0104] In some embodiments, the light emitting layer is formed by a plurality of stacked quantum well layers, in particular, superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include a plurality of pairs of quantum well layers stacked with quantum barrier layers.

[0105] In one embodiment, the light emitting layer includes a multi-quantum well layer, and an electron blocking layer, the multi-quantum well layer being an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In another embodiment, the first type epitaxial layer can also be a P-type GaN layer or a P-type AlGaN layer, and the second type epitaxial layer is an N-type GaN layer or an N-type AlGaN layer.

[0106] In some embodiments, the first type epitaxial layer is a semiconductor material having a first type and includes a plurality of semiconductor layers. The main body material of the first type epitaxial layer can be, but is not limited to, composed of at least two elements from Ga, N, As, P, In, and Al. In addition, the first type epitaxial layer can include, but is not limited to, a confinement layer and a waveguide layer from top to bottom; in addition, in some embodiments, an ohmic contact layer can be formed on the confinement layer.

[0107] In some embodiments, the second type epitaxial layer is a semiconductor material having a second type and includes a plurality of semiconductor layers. The main body material of the second type epitaxial layer can be, but is not limited to, composed of Ga, N, As, P, In, or Al, etc. In addition, the second type epitaxial layer can include, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer from top to bottom; in addition, an ohmic contact layer can be formed below the window layer.

[0108] In some embodiments, the first type epitaxial layer is an N-type GaN layer or an N-type AlGaN layer, and the second type epitaxial layer is a P-type GaN layer or a P-type AlGaN layer, i.e., the material of the second type epitaxial layer can be a material layer of the second type composed of at least two elements from Ga, N, As, Al, In, and P, and the material of the first type epitaxial layer can be a material layer of the first type composed of at least two or more elements from Ga, N, As, Al, In, and P.

[0109] In some embodiments, the light emitting layer includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, wherein x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the light emitting layer is a multiple quantum well (MQW).

[0110] In some embodiments, one of the first type epitaxial layer and the second type epitaxial layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer. The N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, wherein x ranges from 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm, for example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17cm -3 to 1e 18 cm -3 In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer formed on the doped N-type contact layer. The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e 18 cm -3 to 1e 19 cm -3 In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example, 65 nm. In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light emitting layer and the doped P-type contact layer is formed on the P-type cladding layer.

[0111] In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, where x is 0.3 to 0.5, for example, x is 0.5. In such embodiments, the thickness of the P-type cladding layer is no more than 380 nm, for example, the thickness of the P-type cladding layer is 360 nm.

[0112] In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example, 20 nm.

[0113] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example, 65 nm.

[0114] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-y P, where x ranges from 0.1 to 0.3 and y ranges from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times x. In some embodiments, the first doped P-type transition layer has a thickness of 20 nm to 40 nm, for example 30 nm.

[0115] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, where x ranges from 0.5 to 0.9, for example x is 0.6. In some embodiments, the second doped P-type transition layer has a thickness of 10 nm to 30 nm, for example 20 nm.

[0116] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times the doping concentration of the second doped P-type transition layer.

[0117] In some embodiments, the doping concentration of the doped P-type contact layer is greater than the doping concentration of the second doped P-type transition layer. Further, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times the doping concentration of the first doped P-type transition layer.

[0118] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 , the doping density of the second doped P-type transition layer is in the range of 2e 18 cm -3 -4e 18 cm -3 , and the doping density of the doped P-type contact layer is greater than 5e 18 cm -3In some embodiments, the electrode polarity of the ohmic contact layer is opposite to the electrode polarity of the top conductive layer, for example, the ohmic contact layer can be a P-electrode or an anode electrode, and the top conductive layer is an electrode opposite to the polarity of the ohmic contact layer, for example, an N-electrode or a cathode electrode. In one embodiment, the ohmic contact layer, the top conductive layer and their connecting components can be one or more combinations of, for example, graphene or Indium Tin Oxide (ITO) or Antimony doped Zinc Oxide (AZO) or Fluorine doped Tin Oxide (FTO) or other Transparent Conductive Oxide (TCO).

[0119] In one embodiment, adjacent top conductive layers are connected, and all the top conductive layers are connected as a whole. In some embodiments, the top conductive layer can be shared by all the micro light emitting diodes in the micro light emitting diode array.

[0120] In some embodiments, the electrode polarity of the ohmic contact layer is opposite to the electrode polarity of the top conductive layer, for example, the ohmic contact layer can be a P-electrode or an anode electrode, and the top conductive layer is an electrode opposite to the polarity of the ohmic contact layer, for example, an N-electrode or a cathode electrode. In one embodiment, the ohmic contact layer, the top conductive layer and their connecting components can be one or more combinations of, for example, graphene or Indium Tin Oxide (ITO) or Antimony doped Zinc Oxide (AZO) or Fluorine doped Tin Oxide (FTO) or other Transparent Conductive Oxide (TCO).

[0121] In some embodiments, adjacent passivation isolation layers are connected, and all the passivation isolation layers are connected as a whole. In one embodiment, the material of the passivation isolation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, silicon nitride.

[0122] In some embodiments, the micro light emitting diode chip further comprises a current spreading structure between the micro light emitting diodes, wherein the current spreading structure is arranged to surround the micro light emitting diodes, and the current spreading structure is configured to electrically contact the micro light emitting diodes and at least partially reflect light emitted by the micro light emitting diodes.

[0123] The current spreading structure surrounds the micro light emitting diodes, and the current spreading structure is electrically connected to the micro light emitting diodes.

[0124] The current spreading structure has light reflecting capability towards the surface of the micro light emitting diode, for example, it is made of metal, so that the current spreading structure can at least partially reflect the light emitted by the light emitting diode. The reflection process is that the light emitted from the light emitting layer of the light emitting diode passes through the transparent layer (for example, the top conductive layer) above it, then a first part of the light (whose exit angle is small enough not to hit the side current spreading structure, within the preset light exit angle, such as within plus or minus 20°) directly exits, a second part of the light (whose exit angle is large enough to hit the side current spreading structure) hits the current spreading structure and exits after reflection, changing the light path direction, becoming within the preset light exit angle, thereby effectively improving the light exit rate. Preferably, the proportion of the light reflected by the current spreading structure to the light emitted by the light emitting diode can be, for example, 10% to 60%. By arranging the current spreading structure with light reflecting capability, the amount of light absorbed by the side wall can be significantly reduced, thereby significantly increasing the total light exit amount. At the same time, the current spreading structure can also isolate light and prevent light crosstalk between adjacent light emitting diodes.

[0125] By arranging the current spreading structure to surround the top conductive layer of the micro light emitting diode in electrical contact, the electrical contact area of the current spreading structure with the micro light emitting diode can be significantly increased, so that the active layer (light emitting layer) of the micro light emitting diode can emit light more uniformly, effectively avoiding the situation that only the electrical contact part or its vicinity emits light or the situation that the light emitting brightness of the electrical contact part or its vicinity is high.

[0126] The size of the bottom of the current spreading structure is larger than the size of the top. Since the bottoms of adjacent current spreading structures are connected, the longitudinal section of the two adjacent current spreading structures presents a shape of bifurcated peaks.

[0127] The bottoms of adjacent current spreading structures are connected, and all the current spreading structures are connected into a whole. For the micro light emitting diode with a circular top view shape (i.e., cross-sectional shape), the top view shape of the whole current spreading structure is a grid shape remaining after the circular shape is removed. In other embodiments, the top view shape of the micro light emitting diode can also be other appropriate shapes, such as a rectangular shape, a square shape, or a regular polygonal shape, etc. The top view shape of the whole current spreading structure can also be a shape remaining after other appropriate shapes are removed, such as a grid shape remaining after a rectangular shape, a square shape, or a polygonal shape is removed.

[0128] In embodiments of the present disclosure, the bottom of the current spreading structure is lower than the epitaxial layer of the micro light emitting diode.

[0129] In embodiments of the present disclosure, the top of the current spreading structure can be higher than the top of the epitaxial layer; the top of the current spreading structure can also be flush with the top of the epitaxial layer; the top of the current spreading structure can also be lower than the top of the epitaxial layer (for example, 0-1 microns lower than the top of the epitaxial layer). In one chip, the above 1, 2 or 3 cases can exist at the same time.

[0130] Preferably, the top of the current spreading structure is higher than the top of the epitaxial layer of the micro light emitting diode. By the height of the top of the current spreading structure being greater than the height of the top plane of the epitaxial layer of the micro light emitting diode, a higher current spreading structure can be obtained, further improving the opportunity for light reflection and increasing the light extraction efficiency.

[0131] In other embodiments, the number of current spreading structures can also be 1 / 4 or 1 / 9 of the number of micro light emitting diodes, each current spreading structure surrounding 4 micro light emitting diodes or 9 micro light emitting diodes, without limitation.

[0132] The current spreading structure can increase the current spreading between adjacent micro light emitting diodes, reduce the resistance between adjacent micro light emitting diodes, and reduce the loss. The current spreading structure can make the current spread quickly and uniformly to all micro light emitting diodes.

[0133] In embodiments of the present disclosure, the current spreading structure can be a multi-layer structure, and the current spreading structure includes one or more main metal layers. In embodiments of the present disclosure, the material of the main metal layer can be one or more of Pt, Au, Al, and Ag.

[0134] In some embodiments, the current spreading structure can further include: an isolation layer corresponding to each layer of main metal layer; wherein the isolation layer and the main metal layer are arranged alternately, and each layer of main metal layer is located on the corresponding isolation layer.

[0135] By adopting the isolation layer corresponding to each layer of main metal layer, and the isolation layer and the main metal layer are arranged alternately, and each layer of main metal layer is located on the corresponding isolation layer, the influence of electromigration in the current spreading structure can be effectively suppressed by setting the isolation layer. Especially in the case of high density of micro light emitting diodes in the micro light emitting diode display chip, the possibility of increasing the height of the current spreading structure can be obtained by setting the isolation layer, and the light extraction efficiency can be further improved by the higher current spreading structure. Further, the isolation layer can include a titanium (Ti) metal layer. It should be noted that the material of the isolation layer can also include other appropriate materials, such as titanium nitride (TiN).

[0136] In some embodiments, the current spreading structure can further include an adhesion layer at the bottom of the current spreading structure, and the isolation layer and the main metal layer are located on the adhesion layer. The adhesion layer is formed between the micro light emitting diodes, and the isolation layer and the main metal layer are located on the adhesion layer. The adhesion of the adhesion layer can effectively improve the stability of the bottom of the current spreading structure. In particular, in the case of a large density of micro light emitting diodes in the micro light emitting diode display chip, the adhesion layer can increase the height of the current spreading structure, and further improve the light extraction efficiency through the higher current spreading structure. Further, the adhesion layer can include a chromium (Cr) metal layer. It should be noted that the material of the adhesion layer can also include other appropriate materials, such as one or more of the following: titanium (Ti), titanium nitride (TiN), tungsten (W).

[0137] In embodiments of the present disclosure, the current spreading structure can further include an anti-diffusion layer corresponding to each isolation layer, and each isolation layer is located on the corresponding anti-diffusion layer. By forming an anti-diffusion layer corresponding to each isolation layer, and each isolation layer is located on the corresponding anti-diffusion layer, the high hardness and good corrosion resistance of the anti-diffusion layer can improve the stability of the current spreading structure. In particular, in the case of a large density of micro light emitting diodes in the micro light emitting diode display chip, the anti-diffusion layer can increase the height of the current spreading structure, and further improve the light extraction efficiency through the higher current spreading structure. The anti-diffusion layer can include a platinum (Pt) metal layer and a nickel (Ni) metal layer. It should be noted that the anti-diffusion layer can be a single platinum metal layer, a single nickel metal layer, or a stack of a single platinum metal layer and a single nickel metal layer.

[0138] In some embodiments, the micro light emitting diode chip further includes a microlens array. The microlens array is disposed above the micro light emitting diode array, wherein at least one microlens is disposed on the surface of the conductive layer at the top of the micro light emitting diode, and the horizontal profile of the microlens is greater than the maximum horizontal profile of the micro light emitting diode. The microlens is mainly used to converge and / or collimate light, for example, by adjusting the thickness, curvature, etc. of the microlens, the focal point of the microlens can be located in the epitaxial layer of the micro light emitting diode. In some embodiments, the microlens of the microlens array corresponds to the epitaxial layer one by one. In some embodiments, examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses.

[0139] In embodiments of the present disclosure, there is a gap between adjacent microlenses. In embodiments of the present disclosure, the bottom of the gap is higher than the top of the epitaxial layer. In yet another embodiment of the present disclosure, the bottom of the gap is lower than the top of the epitaxial layer and higher than the bottom of the epitaxial layer. In another embodiment of the present disclosure, the bottom of the gap is above the current spreading structure. Specifically, the gap is between two adjacent current spreading structures (i.e. between the bifurcated peaks).

[0140] In addition, the microlenses can also have air gaps inside. There can be multiple air gaps in each lens, and the size, length of each air gap can be the same or different. Meanwhile, in the same chip, the number of air gaps, and / or the position and / or size of the air gaps of different microlenses can be the same or different. In some embodiments of the present disclosure, the air gap is located at the edge of the microlens, specifically, for example, it can be located on both sides of the epitaxial layer, preferably, it is located between the epitaxial layer and the current spreading structure. Meanwhile, in some embodiments, the top of the air gap is higher than the top of the epitaxial layer, and the bottom of the air gap can be higher than the top of the epitaxial layer, or lower than the top of the epitaxial layer. In some embodiments, the bottom of the air gap is higher than the top of the current spreading structure. In yet another embodiment, the bottom of the air gap is lower than the top of the current spreading structure. It should be noted that in other embodiments of the present disclosure, the microlenses can also have no air gap inside.

[0141] In some embodiments, the micro light emitting diode chip includes a light emitting region and a non-light emitting region, and the micro light emitting diode, the current spreading structure and the microlens array are located in the light emitting region. The non-light emitting region surrounds the light emitting region.

[0142] In some embodiments, the non-light emitting region of the micro light emitting diode chip has a wire bonding electrode, and the wire bonding electrode is electrically connected to the driving backplane. The wire bonding electrode is used to electrically connect to the circuit board outside the chip.

[0143] The above description is only for exemplary embodiments used to illustrate the principles of the present disclosure, and is not intended to limit the protection scope of the present disclosure. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also within the protection scope of the present disclosure.

Claims

1. A chip module optical testing fixture, characterized by, The jig comprises: a carrier, comprising a carrier surface and a carrier body, the carrier surface comprising a planar portion for placing a display chip; a first gas channel is formed in the carrier body and penetrates the carrier surface, and the first gas channel is connected with a vacuum system.

2. The jig of claim 1, wherein The carrier surface of the carrier further comprises a limiting structure protruding from the planar portion.

3. The jig of claim 1, wherein Further comprising: a heat-conducting pad placed on the planar portion, the heat-conducting pad being provided with a through hole, the position of the through hole corresponding to the position of the first gas channel penetrating the carrier surface.

4. The tool of claim 1, wherein Further comprising: a connector, the connector comprising a connector body and an internal channel in the connector body, the connector body comprising two end portions and a side portion, one end portion being connected with the carrier; the internal channel comprises a second gas channel and a first extension channel, the second gas channel being in communication with the first gas channel, and the first extension channel being in non-communication with the second gas channel.

5. The jig of claim 4, wherein The other end portion of the connector body is formed with a blocking portion, and the second gas channel and the first extension channel penetrate the blocking portion.

6. The jig of claim 5, wherein, The blocking portion protrudes from the side portion of the connector body.

7. The tool of claim 6, wherein The blocking portion is formed with a limiting portion.

8. The jig of any one of claims 4 to 7, wherein, The connector is integrally formed with the carrier.

9. The jig of any one of claims 4-7, wherein, The material of the connector is copper or copper alloy, and the material of the carrier is copper or copper alloy.

10. The jig of any one of claims 5-7, wherein, Further comprising: an extension portion connected with the blocking portion, the extension portion being internally formed with a third gas channel and a second extension channel in non-communication, the two ends of the third gas channel being in communication with the second gas channel and the vacuum system respectively, the second extension channel being in communication with the first extension channel and being adapted to jointly accommodate an extension driving assembly, the extension driving assembly being capable of moving in the second extension channel and the first extension channel.

11. The tool of claim 10, wherein, The extension portion comprises: oppositely arranged first and second portions, and a groove is arranged in the first and / or second portion to form the second extension channel.

12. The tool of claim 11, wherein, The first and second portions of the extension portion are detachably connected with each other.

13. The tool of claim 12, wherein, A first fixed magnet is arranged on the surface of the first portion facing the second portion, and a second fixed magnet is arranged on the surface of the second portion facing the first portion, the positions of the first and second fixed magnets corresponding to each other, and the first and second fixed magnets being adapted to be attracted to each other to fix the first and second portions to each other.

14. The tool of any one of claims 5-7, wherein, The blocking portion and the connector are fixed by fasteners.

15. A testing device for performing optical testing on a chip module, characterized in that, comprises: the jig according to any one of claims 1 to 14; and an optical testing device for testing the optical performance of a display chip, the jig being adapted to be connected with the optical testing device to fix a display chip in the optical testing device.

16. The test apparatus of claim 15, wherein, The optical testing device comprises an inlet, and the connector of the jig is adapted to enter the optical testing device through the inlet.

17. The test apparatus of claim 16, wherein, The testing device further comprises a fixing structure arranged on the surface of the testing device and located near the inlet, the fixing structure being adapted to cooperate with the limiting portion on the blocking portion of the jig to prevent the connector of the jig from rotating after entering the optical testing device.

18. The test apparatus of any one of claims 15 to 17, wherein, The optical testing device is an integrating sphere testing device.

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