Multifunctional digital responder
By designing a priority encoder cascade circuit and logic circuit module, the problem of determining the order of answering in traditional answer buzzers when multiple contestants are answering is solved, realizing accurate priority judgment of answering in a multi-functional digital answer buzzer, and improving the fairness and accuracy of the competition.
Patent Information
- Application Number
- CN202423212128.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2034-12-25
AI Technical Summary
Existing buzzer systems lack a precise priority determination mechanism when multiple contestants participate in the buzzer-in, making it difficult to guarantee the fairness and accuracy of the competition. Especially when the buzzer-in time is short, traditional mechanical or electronic circuit designs cannot accurately distinguish the order in which contestants answer.
By employing a cascaded circuit design using priority encoders (such as 74LS148), combined with logic circuit modules, latch modules, and a microcontroller minimum system, priority judgment of the answer-grabbing signal is achieved. Real-time feedback is provided through sound output modules and display modules to ensure the fairness and transparency of the answer-grabbing process.
It can accurately determine the priority of the 32 contestants in answering, which improves the fairness and accuracy of the competition, simplifies the operation process, reduces human intervention, and ensures the accuracy and efficiency of the answering process.
Smart Images
Figure CN223679716U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to digital responder technical field especially relates to a convenient to use multifunctional digital responder. BACKGROUND
[0002] With the increasing demand of knowledge competition and intelligence competition in various fields of society, the traditional competition mode gradually exposes some deficiencies, especially in the answering link, the traditional artificial judgment mode is easily affected by the subjective factors of the host, leading to the fairness and accuracy in the competition process cannot be fully guaranteed. For example, the answering time of two groups of players in the competition can be very close, and it is difficult to judge the answering order by naked eyes, thereby affecting the fairness of the competition. This problem is particularly prominent in multi-player and multi-link competition. At present, the intelligent control system based on single-chip microcomputer has been widely used in industry, agriculture, power, electronics and intelligent building and many other fields, especially in embedded systems and electronic control systems, the single-chip microcomputer becomes the core component of many intelligent products with its low power consumption, high reliability and flexible programmability. In the field of building automation and smart home, the single-chip microcomputer technology has gradually become the basis of control system design. In the field of knowledge competition, the intelligent answering system developed by means of single-chip microcomputer technology has become an indispensable part of modern competition activities. Although the existing answering system can realize the basic answering timing and display function, it often lacks accurate priority judgment mechanism when dealing with the answering situation of multiple players participating at the same time. Some traditional answering device designs use mechanical switches or simple electronic circuits for priority judgment, which cannot accurately distinguish which player answers the question first in a short time, especially in the case of very short answering time, it is difficult to ensure the fairness of the competition. CONTENT OF THE UTILITY MODEL
[0003] The technical problem to be solved by the utility model is how to provide a more intelligent and automatic solution for knowledge competition and various answering activities, and improve the fairness and accuracy of the multifunctional digital answering device.
[0004] To solve the above technical problems, the utility model adopts the technical scheme: a multifunctional digital answer grabber, including a plurality of answer grab key modules for inducting answer grab signals, the output end of a plurality of answer grab key modules is connected with the input end of priority encoder, the priority encoder is used for judging the priority of answer grab signal, the signal output end of priority encoder is connected with the input end of logic circuit module, the logic circuit module is used for carrying out logic processing to the input priority signal, the input end of latch module is connected with the output end of one way of logic circuit module, the latch module is used for latching the first pressed answer grab signal, the input end of sound output module is connected with the other way of output end of logic circuit module, sound output module is used for sending sound prompt when the contestant answers, the output end of latch module is connected with one input end of singlechip minimum system, the first answer grab signal of latching is input to singlechip minimum system and handles, the display module is connected with one output end of singlechip minimum system, the display module is used for displaying various information in the answer grab process after the singlechip minimum system handles, the serial communication module is connected with the singlechip minimum system in both directions, is used for connecting the debugging equipment and is debugging the answer grabber, the input end of control switch module is connected with singlechip minimum system, is used for inputting control signal.
[0005] The beneficial effects of the above technical scheme are that: the answer grabber can realize 32 contestants participating in answer grab at the same time, and can accurately judge the priority of contestant answer grab, solve the error problem caused by traditional manual judgment. In addition, the system also realizes the functions of latching, display, sound prompt and countdown of answer grab information through other circuit structures, ensures the fairness and transparency of the competition. The answer grabber can provide more intelligent and automatic solution for knowledge competition and various answering activities, and improves the fairness and accuracy of the competition. BRIEF DESCRIPTION OF DRAWINGS
[0006] The utility model will be explained further in detail in combination with the drawings and specific embodiment.
[0007] Figure 1 It is the principle block diagram of the answer grabber of the utility model embodiment;
[0008] Figure 2 It is the circuit principle diagram of the answer grabber of the utility model embodiment;
[0009] Figure 3 It is the principle diagram of part answer grab key module, part priority encoder and part logic circuit module in the answer grabber of the utility model embodiment;
[0010] Figure 4is the principle diagram of the part of the partial answer button module, the part of the priority encoder and the part of the logic circuit module in the answerer according to the embodiment of the utility model;
[0011] Figure 5 is the principle diagram of the sound output module and the part of the logic circuit module in the answerer according to the embodiment of the utility model;
[0012] Figure 6 is the circuit principle diagram of the latch module and the single-chip microcomputer in the answerer according to the embodiment of the utility model;
[0013] Figure 7 is the part of the principle diagram of the minimum system of the single-chip microcomputer in the answerer according to the embodiment of the utility model;
[0014] Figure 8 is the principle diagram of the display module in the answerer according to the embodiment of the utility model. DETAILED DESCRIPTION
[0015] The technical solutions in the embodiments of the utility model will be described clearly and completely below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all the other embodiments obtained by the person skilled in the art without creative labor belong to the protection scope of the utility model.
[0016] In the following description, many specific details are set forth in order to provide a thorough understanding of the utility model, but the utility model can also be implemented in other ways different from the description, and the person skilled in the art can make similar generalization without violating the connotation of the utility model, therefore the utility model is not limited by the following disclosed specific embodiments.
[0017] As Figure 1The utility model discloses a multifunctional digital answerer, including a plurality of for inductive answer signal's answer key module, a plurality of answer key module's output and the input of priority encoder are connected, the priority encoder is used to judge the priority of answer signal, the signal output of priority encoder and the input of logic circuit module are connected, the logic circuit module is used to carry out logic processing to the priority signal of input, the input of one way output of logic circuit module and latch module are connected, the latch module is used to latch the first press answer signal, the other way output of output of logic circuit module and the input of sound output module are connected, the sound output module is used to send out sound prompt when contestant answers, the output of latch module and one input of singlechip minimum system are connected, and the first answer signal of latching is input to the singlechip minimum system and handles, the display module is connected with one output of singlechip minimum system, and the display module is used to show various information in the answer process after the singlechip minimum system handles, and serial communication module and singlechip minimum system are connected bidirectionally, are used for connecting debugging equipment and are used for debugging the answerer, and the input of control switch module and singlechip minimum system are connected, are used for input control signal.
[0018] Further, as Figures 2-8 The utility model discloses a multifunctional digital answerer, including a plurality of for inductive answer signal's answer key module, a plurality of answer key module's output and the input of priority encoder are connected, the priority encoder is used to judge the priority of answer signal, the signal output of priority encoder and the input of logic circuit module are connected, the logic circuit module is used to carry out logic processing to the priority signal of input, the input of one way output of logic circuit module and latch module are connected, the latch module is used to latch the first press answer signal, the other way output of output of logic circuit module and the input of sound output module are connected, the sound output module is used to send out sound prompt when contestant answers, the output of latch module and one input of singlechip minimum system are connected, and the first answer signal of latching is input to the singlechip minimum system and handles, the display module is connected with one output of singlechip minimum system, and the display module is used to show various information in the answer process after the singlechip minimum system handles, and serial communication module and singlechip minimum system are connected bidirectionally, are used for connecting debugging equipment and are used for debugging the answerer, and the input of control switch module and singlechip minimum system are connected, are used for input control signal.
[0019] Further, the logic circuit module includes three 74HC20 type double 4 input NAND gate chips, two 74LS00 type four 2 input NAND gate chips, one 74LS08 type four 2 input NAND gate chip and one 74LS32 type four channel OR gate chip, the 9 pins of the four 74LS148 type chips are respectively connected with the four input ends of the first 74HC20 type chip, the 7 pins of the four 74LS148 type chips are respectively connected with the four input ends of the second 74HC20 type chip, the 6 pins of the four 74LS148 type chips are respectively connected with the four input ends of the third 74HC20 type chip, the four 74LS148 type chips are connected with the 3 pins of the 74HC74 type chip after cascading, and the output end of the 74LS08 type chip is connected with one output end of the 74LS32 type chip.
[0020] Further, the latch module includes a 74HC74 type double D flip-flop chip and a 74LS373 type latch chip, the output end of the three 74HC20 type chips and the output end of the two 74LS00 type chips and the output end of the 74HC74 type double D flip-flop chip are connected with the input end of the 74LS373 type latch chip.
[0021] Further, as shown in Figure 5 the sound output module includes a resistor R45, one end of the resistor R45 is connected with the output end of the 74LS32 type chip, the other end of the resistor R45 is divided into two paths, the first path is connected with the ground through a resistor R46, the second path is connected with the base of a transistor Q1, the emitter of the transistor Q1 is connected with the ground, the collector of the transistor Q1 is connected with the power supply through a buzzer.
[0022] Further, as shown in Figures 6-7 the single-chip microcomputer minimum system includes an AT89C51 type single-chip microcomputer U7. As shown in Figures 7-8 the display module includes two nixie tubes, the 21 pin of the U7 is connected with the base of a transistor Q2, the emitter of the transistor Q2 is connected with the ground through a resistor R42, the collector of the transistor Q2 is connected with the 1 pin of the first nixie tube; the 22 pin of the U7 is connected with the base of a transistor Q3, the emitter of the transistor Q3 is connected with the ground through a resistor R48, the collector of the transistor Q3 is connected with the 2 pin of the first nixie tube; the 23 pin of the U7 is connected with the base of a transistor Q4, the emitter of the transistor Q4 is connected with the ground through a resistor R52, the collector of the transistor Q4 is connected with the 1 pin of the second nixie tube; the 24 pin of the U7 is connected with the base of a transistor Q5, the emitter of the transistor Q5 is connected with the ground through a resistor R53, the collector of the transistor Q5 is connected with the 2 pin of the second nixie tube;
[0023] The 39th pin of U7 is divided into three ways, the first way connects power supply VCC through resistor R38, the second way connects the A pin of the first nixie tube, and the third way connects the A pin of the second nixie tube; the 38th pin of U7 is divided into three ways, the first way connects power supply VCC through resistor R39, the second way connects the B pin of the first nixie tube, and the third way connects the B pin of the second nixie tube; the 37th pin of U7 is divided into three ways, the first way connects power supply VCC through resistor R40, the second way connects the C pin of the first nixie tube, and the third way connects the C pin of the second nixie tube; the 36th pin of U7 is divided into three ways, the first way connects power supply VCC through resistor R41, the second way connects the D pin of the first nixie tube, and the third way connects the D pin of the second nixie tube; the 35th pin of U7 is divided into three ways, the first way connects power supply VCC through resistor R47, the second way connects the E pin of the first nixie tube, and the third way connects the E pin of the second nixie tube; the 34th pin of U7 is divided into three ways, the first way connects power supply VCC through resistor R43, the second way connects the F pin of the first nixie tube, and the third way connects the F pin of the second nixie tube; the 33rd pin of U7 is divided into three ways, the first way connects power supply VCC through resistor R44, the second way connects the G pin of the first nixie tube, and the third way connects the G pin of the second nixie tube.
[0024] The priority encoder and cascade circuit adopts the priority encoder 74LS148 cascade circuit to realize the priority judgment of the 32 contestants' answer signals. Since the 74LS148 encoder supports a maximum of 8 inputs, four encoders are cascaded, and a logic circuit is used to ensure the correct identification of the priority signal; a system clearing button and a responder control switch are designed, and the host can start or clear the system through the switch to control the start or reset of the countdown. After pressing the clear button, the system returns to the initial state, and all latched information, score data and timer settings will be cleared; the answer function and latched display, after each contestant presses the answer button, the system will latch the contestant's number, the buzzer and LED light (sound output module and display module) will give sound and visual prompts, and the display will show the number of the contestant who answers and the remaining answer time. The number of the priority answerer will remain until the host clears the system.
[0025] The countdown time is set, after the host closes the answer switch, the contestants start to answer, when a contestant presses the answerer, the nixie tube displays the contestant's number and locks the countdown time, if there is no contestant answering within the time, the buzzer will alarm; if the contestant answers correctly, the host will give him one point, otherwise, deduct one point; then the host presses the countdown zero key to prepare for the next answer. At any time, if the host closes the score checking switch, it will enter the score checking mode, first display the score of the first contestant, and each time the score checking key is pressed, the nixie tube will display the score of the next contestant.
[0026] The key situation of the contestant can be latched by 74LS148 priority decoder cascaded through 74LS373 latch. In addition, the system clear and responder control switch is designed, which is controlled by the host. The P3.3 port is externally connected to the key as the system clear key, and the high EI port of the cascaded 74LS148 priority decoder is externally connected to the switch as the responder control switch. The responder uses D flip-flop and 74LS373 to realize latching, and uses P0 port and P2.0-P2.3 of AT89C51 single-chip microcomputer to realize display function by selecting four-digit LED. When the contestant presses the responder button, the corresponding number is latched, the speaker emits sound prompt, and the contestant number is displayed on the display. The priority latching of the contestant's response is realized by the latching function of the latch, and the number of the priority responder is kept until the system is cleared by the host, that is, the system is cleared when the host presses the button of P3.3 port. The responder has timing function by using T0 timer combined with external crystal oscillator circuit, and the time of one response is set by the host through subsequent program design. When the host presses the button of T1 port in a specific situation, the countdown time is lengthened, and the countdown time adjustment range is 30-60s. When the countdown time is 60s, the host still presses the time adjustment button, and the countdown time becomes 0s. When the host turns off the switch control key, the timer starts to count down. The contestant responds within the set time, the response is valid, and the timer stops working. If the time is up and no one responds, the response is invalid, the system alarms and prohibits response, and the display shows 00. The two conditions of the buzzer working are controlled by the specific pin of the single-chip microcomputer or the contestant responding. When the contestant responds normally, if the answer is correct, the judge presses the button of P2.5, and one point is added to the corresponding position of the array according to the number of the responder; if the answer is incorrect, the button of P2.6 is pressed, and one point is subtracted. When the judge turns on the switch of P2.7, the single-chip microcomputer enters the score checking mode, and the score of each contestant can be checked by pressing the button of P3.5. The serial communication function can check the score of the specified student through the upper PC.
[0027] In summary, the responder ensures that after the first button is pressed, other button signals will not affect the existing response state; simplifies the operation, improves the fairness, can automatically realize response latching, display, countdown and priority judgment, reduces manual intervention, ensures the fairness of the competition, ensures the accuracy and efficiency of the response process; the host can set the response time according to the needs, the time range is flexible (30 seconds to 60 seconds), which can meet the needs of different competitions. At the same time, the timer function ensures the standardization and orderliness of the response process.
Claims
1. A multi-functional digital buzzer, characterized by: The application relates to a response button module for a response button device, which comprises a plurality of response button modules for sensing response signals, the output ends of the plurality of response button modules are connected with the input ends of a priority encoder, the priority encoder is used for judging the priority of the response signals, the signal output end of the priority encoder is connected with the input end of a logic circuit module, the logic circuit module is used for logically processing the input priority signals, one output end of the logic circuit module is connected with the input end of a latch module, the latch module is used for latching the first pressed response signal, the other output end of the output end of the logic circuit module is connected with the input end of a sound output module, and the sound output module is used for sounding a prompt sound when a player responds. The output end of the latch module is connected with one input end of a single-chip microcomputer minimum system, and the latched first response signal is input into the single-chip microcomputer minimum system for processing. A display module is connected with one output end of the single-chip microcomputer minimum system, and the display module is used for displaying various information in the response process after the single-chip microcomputer minimum system processing. A serial communication module is bidirectionally connected with the single-chip microcomputer minimum system and is used for connecting a debugging device to debug the response button device.
2. The multi-functional digital beeper as claimed in claim 1, wherein: The response button module is provided with four groups, each group is provided with eight response button modules, each response button module comprises a button, one end of the button is grounded, and the other end of the button is connected with one input end of a priority encoder.
3. The multi-functional digital beeper of claim 2, wherein: The priority encoder uses 74LS148 type chips, is provided with four chips, one priority encoder corresponds to each group of response button modules, one end of the button in each group is grounded, and the other end of the eight buttons in each group is connected with eight input ends of the 74LS148 type chips.
4. The multi-functional digital beeper of claim 3, wherein: The logic circuit module comprises three 74HC20 type double-4-input NAND gate chips, two 74LS00 type four-group 2-input NAND gate chips, one 74LS08 type four-way 2-input NAND gate chip and one 74LS32 type four-channel OR gate chip, the nine pins of the four 74LS148 type chips are respectively connected with four input ends of the first 74HC20 type double-4-input NAND gate chip, the seven pins of the four 74LS148 type chips are respectively connected with four input ends of the second 74HC20 type double-4-input NAND gate chip, the six pins of the four 74LS148 type chips are respectively connected with four input ends of the third 74HC20 type double-4-input NAND gate chip, the four 74LS148 type chips are connected with the three pins of a 74HC74 type double-D flip-flop chip in cascade, and the output end of the 74LS08 type four-way 2-input NAND gate chip is connected with one output end of the 74LS32 type four-channel OR gate chip.
5. The multi-functional digital beeper of claim 4, wherein: The latch module comprises a 74HC74 type double D flip-flop chip, a 74LS373 type latch chip, outputs of three 74HC20 type double 4-input NAND gate chips, outputs of two 74LS00 type four-group 2-input NAND gate chips, and an output of the 74HC74 type double D flip-flop chip connected with inputs of the 74LS373 type latch chip.
6. The multi-functional digital beeper of claim 4, wherein: The sound output module comprises a resistor R45, one end of the resistor R45 connected with an output of the 74LS32 type four-channel OR gate chip, the other end of the resistor R45 divided into two paths, the first path grounded through a resistor R46, and the second path connected with a base of a transistor Q1, an emitter of the transistor Q1 grounded, and a collector of the transistor Q1 connected with a power supply through a buzzer.
7. The multi-functional digital beeper of claim 4, wherein: The single-chip microcomputer minimum system comprises an AT89C51 type single-chip microcomputer U7.
8. The multi-functional digital beeper of claim 7, wherein: The display module comprises two NMD-1712 type digital tubes, a 21th pin of the U7 connected with a base of a transistor Q2, an emitter of the transistor Q2 grounded through a resistor R42, and a collector of the transistor Q2 connected with a 1st pin of a first digital tube, a 22th pin of the U7 connected with a base of a transistor Q3, an emitter of the transistor Q3 grounded through a resistor R48, and a collector of the transistor Q3 connected with a 2nd pin of the first digital tube, a 23th pin of the U7 connected with a base of a transistor Q4, an emitter of the transistor Q4 grounded through a resistor R52, and a collector of the transistor Q4 connected with a 1st pin of a second digital tube, and a 24th pin of the U7 connected with a base of a transistor Q5, an emitter of the transistor Q5 grounded through a resistor R53, and a collector of the transistor Q5 connected with a 2nd pin of the second digital tube. The 39th pin of the U7 is divided into three paths, the first path connected with a power supply VCC through a resistor R38, the second path connected with an A pin of the first digital tube, and the third path connected with an A pin of the second digital tube, the 38th pin of the U7 divided into three paths, the first path connected with the power supply VCC through a resistor R39, the second path connected with a B pin of the first digital tube, and the third path connected with a B pin of the second digital tube, the 37th pin of the U7 divided into three paths, the first path connected with the power supply VCC through a resistor R40, the second path connected with a C pin of the first digital tube, and the third path connected with a C pin of the second digital tube, the 36th pin of the U7 divided into three paths, the first path connected with the power supply VCC through a resistor R41, the second path connected with a D pin of the first digital tube, and the third path connected with a D pin of the second digital tube, the 35th pin of the U7 divided into three paths, the first path connected with the power supply VCC through a resistor R47, the second path connected with an E pin of the first digital tube, and the third path connected with an E pin of the second digital tube, the 34th pin of the U7 divided into three paths, the first path connected with the power supply VCC through a resistor R43, the second path connected with an F pin of the first digital tube, and the third path connected with an F pin of the second digital tube, and the 33th pin of the U7 divided into three paths, the first path connected with the power supply VCC through a resistor R44, the second path connected with a G pin of the first digital tube, and the third path connected with a G pin of the second digital tube.