Delay power-off circuit of mainboard, mainboard and electronic equipment

Abstract

The embodiment of the utility model provides a time-delay power-off circuit of a mainboard, the mainboard and electronic equipment, and relates to the technical field of electronic circuits, when a time-delay module receives a power-off signal of a main control chip of the mainboard, a first level sent to a control module is changed into a second level, and after a preset duration, the second level is changed into the first level; and when the received second level is changed into the first level, the control module outputs a control signal to control the mainboard to be powered off. In the process, the power-off duration of the mainboard is delayed to ensure that the operating system is in a closed state before the mainboard is powered off, so that the situation that related system files of the operating system are damaged due to the fact that the mainboard is powered off in advance under the condition that the operating system is not closed is avoided.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic circuit technical field especially, and it is a kind of mainboard delay power-off circuit, mainboard and electronic equipment. BACKGROUND

[0002] When shutting down electronic equipment, the mainboard of the electronic equipment inevitably needs to be powered off. However, the electronic equipment usually has an operating system, such as a Linux operating system, and the shutdown process of the operating system also needs to consume a certain amount of time. If the mainboard is powered off before the operating system is closed, the system files of the operating system may be damaged. SUMMARY

[0003] The utility model provides a kind of mainboard delay power-off circuit, mainboard and electronic equipment to at least solve the problem of system file damage of operating system caused by the mainboard being powered off before operating system is closed in the related art.

[0004] In the first aspect, the utility model embodiment provides a kind of mainboard delay power-off circuit, comprising: delay module and control module;

[0005] The delay module is electrically connected with the control module and the main control chip of the mainboard respectively, for when receiving the shutdown signal of the main control chip, the first level sent to the control module is changed to the second level, and after the preset time length, the second level is changed to the first level;

[0006] The control module is electrically connected with the external power supply switch module of the mainboard, for when the received second level is changed to the first level, output control signal, control the mainboard power off.

[0007] Optionally, the delay module includes a first switch submodule and a delay submodule;The first switch submodule is electrically connected with the delay submodule, the first switch submodule is electrically connected with the main control chip, and is turned on under the condition of receiving the shutdown signal;The delay submodule is electrically connected with the control module, for under the condition that the first switch submodule is turned on, the first level output is changed to the second level, and after the preset time length, the second level is changed to the first level.

[0008] Optionally, the first switch sub-module comprises a first switch device, a first resistor and a second resistor; a first end of the first resistor is electrically connected with the external power supply, and a second end of the first resistor is electrically connected with the delay sub-module and a first end of the first switch device respectively; a first end of the second resistor is electrically connected with the master control chip and a control end of the first switch device respectively, and a second end of the second resistor is grounded; a first end of the first switch device is electrically connected with the delay sub-module, a control end of the first switch device is electrically connected with the master control chip, and a second end of the first switch device is grounded.

[0009] Optionally, the first switch sub-module comprises a second switch device, a third resistor and a fourth resistor; a first end of the third resistor is electrically connected with the external power supply, and a second end of the third resistor is electrically connected with the delay sub-module and a first end of the second switch device respectively; a first end of the fourth resistor is electrically connected with the external power supply, and a second end of the fourth resistor is electrically connected with the master control chip and a control end of the second switch device respectively; a first end of the second switch device is electrically connected with the delay sub-module, a control end of the second switch device is electrically connected with the master control chip, and a second end of the second switch device is grounded.

[0010] Optionally, the delay sub-module comprises a timer chip; a trigger end of the timer chip is electrically connected with an output end of the first switch sub-module, and an output end of the timer chip is electrically connected with the control module.

[0011] Optionally, the control module comprises a second switch sub-module and a control sub-module; the second switch sub-module is electrically connected with the delay module and the control sub-module respectively, and is used for controlling the second switch sub-module to change from being turned on to being turned off in the case that the second level becomes the first level; the control sub-module is electrically connected with the external power supply switch module, and outputs the control signal to the external power supply switch module in the case that the second switch sub-module changes from being turned on to being turned off.

[0012] Optionally, the second switch sub-module comprises a third switch device, a fifth resistor and a sixth resistor; a first end of the fifth resistor is electrically connected with the external power supply, and a second end of the fifth resistor is electrically connected with an input end of the control sub-module and a first end of the third switch device respectively; a first end of the sixth resistor is electrically connected with the external power supply, and a second end of the sixth resistor is electrically connected with the delay module and a control end of the third switch device respectively; a first end of the third switch device is electrically connected with the input end of the control sub-module, a control end of the third switch device is electrically connected with the delay module, and a second end of the third switch device is grounded.

[0013] Optionally, the control submodule comprises a D flip-flop chip, a seventh resistor and an eighth resistor; a first end of the seventh resistor is electrically connected with an output end of the second switch submodule, and a second end of the seventh resistor is electrically connected with a clock input end of the D flip-flop chip; a first end of the eighth resistor is electrically connected with an output end of the D flip-flop chip, and a second end of the eighth resistor is electrically connected with the external power supply switch module.

[0014] In the second aspect, the utility model embodiment further provides a mainboard, comprising the delay power-off circuit of the first aspect.

[0015] In the third aspect, the utility model embodiment further provides an electronic device, comprising the delay power-off circuit of the first aspect or the mainboard of the second aspect.

[0016] In the utility model embodiment, when receiving the shutdown signal of the master control chip, the delay module changes the first level of the control module into the second level, and changes the second level into the first level after the preset time length, and then the control module outputs the control signal when receiving the second level changing into the first level, and controls the mainboard power-off. In this process, by delaying the power-off time of the mainboard, it is ensured that the operating system is in the closed state before the mainboard power-off, so as to avoid the damage of the related system files of the operating system caused by the power-off of the mainboard in advance under the condition that the operating system is not closed. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical scheme of the utility model embodiment, the following will briefly introduce the drawings needed to be used in the description of the utility model embodiment. Obviously, the drawings in the following description are only some embodiments of the utility model, and other drawings can be obtained according to these drawings without creative labor for those skilled in the art.

[0018] Figure 1 is a structural schematic view of the delay power-off circuit of the mainboard provided by the utility model embodiment;

[0019] Figure 2 is a specific structural schematic view of the delay power-off circuit of the mainboard provided by the utility model embodiment;

[0020] Figure 3 is another specific structural schematic view of the delay power-off circuit of the mainboard provided by the utility model embodiment.

[0021] Reference signs:

[0022] 10-delay module; 11-first switch sub-module; 12-delay sub-module; 20-control module; 21-second switch sub-module; 22-control sub-module; 30-mainboard; 31-main control chip; 32-external power switch module; U1-timer chip; U2-D flip-flop chip; R1-first resistor; R2-second resistor; R3-third resistor; R4-fourth resistor; R5-fifth resistor; R6-sixth resistor; R7-seventh resistor; R8-eighth resistor; R9-ninth resistor; R10-tenth resistor; R11-eleventh resistor; R12-twelfth resistor; R13-thirteenth resistor; Q1-first switch device; Q2-second switch device; Q3-third switch device; C1-first capacitor; C2-second capacitor; C3-third capacitor. DETAILED DESCRIPTION

[0023] In order to make the above-mentioned purpose, features and advantages of the utility model more apparent, obvious and easy to understand, the utility model will be further explained in detail below with the help of the drawings and specific embodiments.

[0024] Reference Figure 1 The utility model embodiment provides a kind of mainboard delay power-off circuit, comprising: delay module 10 and control module 20;The delay module 10 is electrically connected with the control module 20, the main control chip 31 of the mainboard 30 respectively, for when receiving the shutdown signal of the main control chip 31, it will send output signal to the control module 20, and the first level of output signal is changed into second level, and after preset time length, the second level is changed into the first level again;The control module 20 is electrically connected with the external power switch module 32 of the mainboard, for when the second level in the received output signal is changed into the first level, control signal is output to external power switch module 32, so that external power switch module 32 controls the mainboard 30 power off according to control signal.

[0025] It needs to be explained that the mainboard 30 is the circuit board of electronic equipment, in the case where the shutdown trigger signal is received to electronic equipment, the main control chip 31 of mainboard 30 generates shutdown signal, and the closing process of the operating system of electronic equipment starts;In the case where shutdown operation is executed to electronic equipment, after the delay of delay module 10, control external power switch module 32 is disconnected, so that the mainboard 30 is powered off, so that delay time length is greater than the time length consumed in closing process of operating system, guarantee the safe closing of electronic equipment.

[0026] The first level is opposite to the second level, for example, the first level is low level, and the second level is high level.

[0027] In some embodiments, the control signal is high level.

[0028] The main control chip 31 can be a processor (CPU, Central Processing Unit), a microcontroller unit (MCU, Microcontroller Unit) or other types of chips.

[0029] The external power switch module 32 can be an advanced technology extended (ATX, Advanced Technology eXtended) power supply, a switch type chip or other switch type circuits; the external power switch module 32 is disconnected under the condition of obtaining the control signal, so that the mainboard 30 is powered off.

[0030] In the embodiment of the utility model, when receiving the shutdown signal of the main control chip, the first level of the output signal sent to the control module is changed to the second level by the delay module, and after the preset time length, the second level is changed to the first level, then the control module outputs the control signal when receiving the second level changes to the first level, and controls the mainboard to be powered off. In this process, the power-off time of the mainboard is delayed to ensure that the operating system is closed before the mainboard is powered off, thereby avoiding the damage of the system file of the operating system caused by the power-off of the mainboard before the operating system is closed.

[0031] Optionally, referring to Figure 2 In some embodiments, the delay module 10 includes a first switch submodule 11 and a delay submodule 12; the output signal is the signal output by the delay submodule 12; the first switch submodule 11 is electrically connected with the delay submodule 12 and the main control chip 31 respectively, and is used for conducting under the condition of receiving the shutdown signal; the delay submodule 12 is electrically connected with the control module 20, and is used for changing the output signal from the first level to the second level under the condition that the first switch submodule 11 is conducting, and changing the second level to the first level after the preset time length.

[0032] It should be noted that in the case where the shutdown operation is not performed on the electronic device, the first switch submodule 11 is disconnected.

[0033] In the embodiment of the utility model, the first switch submodule 11 is conducting under the condition of receiving the shutdown signal sent by the main control chip 31, then the output signal is changed from the first level to the second level and sent to the control module 20 by the delay submodule 12 under the condition that the first switch submodule 11 is conducting, and after the preset time length, the output signal is changed from the second level to the first level and sent to the control module 20, then the control module 20 sends the control signal to the external power switch module 32 under the condition that the output signal received by the control module 20 is changed from the second level to the first level, and the external power switch module 32 is disconnected after receiving the control signal, so as to realize the power-off of the mainboard 30.

[0034] Optionally, in some embodiments, the first switch sub-module 11 comprises a first switch device Q1, a first resistor R1 and a second resistor R2; a first end of the first resistor R1 is electrically connected with an external power supply, a second end of the first resistor R1 is electrically connected with an input end of the delay sub-module 12 and a first end of the first switch device Q1 respectively; a first end of the second resistor R2 is electrically connected with an output end of the master control chip 31 and a control end of the first switch device Q1 respectively, and a second end of the second resistor R2 is grounded; the first end of the first switch device Q1 is electrically connected with the input end of the delay sub-module 12, the control end of the first switch device Q1 is electrically connected with the output end of the master control chip 31, and the second end of the first switch device Q1 is grounded.

[0035] Specifically, in some embodiments, the first switch device Q1 is an NMOS tube (Negative channel-Metal-Oxide-Semiconductor); in other embodiments, the first switch device Q1 is an NPN type triode, which is composed of three semiconductor blocks, including two N (Negative Electricity) type semiconductors (electron type semiconductors) and one P (Positive Electricity) type semiconductor (hole type semiconductor), with the P type semiconductor in the middle and the two N type semiconductors on both sides.

[0036] In some embodiments, the shutdown signal is a high level.

[0037] In the embodiment of the utility model, the first resistor R1 is a pull-up resistor, the second resistor R2 is a pull-down resistor, when the shutdown signal sent by the master control chip 31 is not received, the control end of the first switch device Q1 is pulled down by the second resistor R2, and the first switch device Q1 is disconnected; the first switch device Q1 is turned on when the shutdown signal is acquired, and then the output signal sent by the delay sub-module 12 is changed from the first level to the second level according to the shutdown signal, and after a preset time, the output signal sent is changed from the second level to the first level, then the control module 20 sends a control signal to the external power supply switch module 32 when the received output signal is changed from the second level to the first level, and the external power supply switch module 32 is disconnected after receiving the control signal, so as to realize the power-off of the mainboard 30.

[0038] Optionally, referring to Figure 3In some embodiments, the first switch sub-module 11 comprises a second switch device Q2, a third resistor R3 and a fourth resistor R4; the first end of the third resistor R3 is electrically connected with an external power supply, the second end of the third resistor R3 is electrically connected with the input end of the delay sub-module 12 and the first end of the second switch device Q2 respectively; the first end of the fourth resistor R4 is electrically connected with the external power supply, the second end of the fourth resistor R4 is electrically connected with the output end of the main control chip 31 and the control end of the second switch device Q2 respectively; the first end of the second switch device Q2 is electrically connected with the input end of the delay sub-module 12, the control end of the second switch device Q2 is electrically connected with the output end of the main control chip 31, and the second end of the second switch device Q2 is grounded.

[0039] It should be noted that in the case of performing the power-on operation on the electronic device, the external power supply supplies power to the delay module 10 and the control module 20.

[0040] Specifically, in some embodiments, the second switch device Q2 is a PMOS tube (positive channel Metal Oxide Semiconductor, PMOS tube); in other embodiments, the second switch device Q2 is a PNP type triode, which is composed of three semiconductor blocks, including one N-type semiconductor and two P-type semiconductors, with the N-type semiconductor in the middle and the two P-type semiconductors on both sides.

[0041] In some embodiments, the shutdown signal is a low level.

[0042] In the embodiments of the utility model, the third resistor R3 and the fourth resistor R4 are both pull-up resistors, when no shutdown signal sent by the main control chip 31 is received, the control end of the second switch device Q2 is pulled up by the fourth resistor R4, and the second switch device Q2 is disconnected; through the first switch device Q1, when the shutdown signal is obtained, the first switch device Q1 is turned on, and then in the case that the first switch device Q1 is turned on, the delay sub-module 12 changes the output signal sent by the first level to the second level according to the shutdown signal, and after a preset time, changes the output signal sent by the second level to the first level, and then the control module 20 sends a control signal to the external power supply switch module 32 in the case that the output signal received by the control module 20 changes from the second level to the first level, and the external power supply switch module 32 is disconnected after receiving the control signal, so as to realize the power-off of the mainboard 30.

[0043] Optionally, in some embodiments, the delay sub-module 12 comprises a timer chip U1; the trigger end U1a of the timer chip U1 is electrically connected with the output end of the first switch sub-module 11, and the output end U1b of the timer chip U1 is electrically connected with the input end of the control module 20.

[0044] It should be noted that the output signal of the delay module 10, that is, the signal output by the delay submodule 12, that is, the signal output by the timer chip U1.

[0045] In some embodiments, the timer chip U1 is a 555 timer chip U1.

[0046] In some embodiments, the delay submodule 12 further comprises a ninth resistor R9, a first capacitor C1 and a second capacitor C2. The first end of the ninth resistor R9 is electrically connected with an external power supply, the second end of the ninth resistor R9 is electrically connected with the first end of the first capacitor C1, the discharge end U1c of the timer chip U1 and the threshold end U1d of the timer chip U1 respectively; the first end of the first capacitor C1 is electrically connected with the discharge end U1c of the timer chip U1 and the threshold end U1d of the timer chip U1 respectively, and the second end of the first capacitor C1 is grounded; the first end of the second capacitor C2 is electrically connected with the control end U1f of the timer chip U1, and the second end of the second capacitor C2 is grounded; the ground end U1e of the timer chip U1 is grounded, and the power supply end U1h and the reset end U1g of the timer chip U1 are electrically connected with the external power supply respectively.

[0047] In the embodiment of the utility model, under the condition that the first switch submodule 11 is turned on, the output signal sent by the timer chip U1 to the control module 20 changes from the first level to the second level by the shutdown signal sent by the main control chip 31 trigger, and after the preset time, the output signal sent by the timer chip U1 to the control module 20 changes from the second level to the first level, and then the control module 20 sends the control signal to the external power supply switch module 32 under the condition that the output signal received by the timer chip U1 changes from the second level to the first level, so that the external power supply switch module 32 is disconnected after receiving the control signal, to realize the power-off of the mainboard 30.

[0048] Optionally, in some embodiments, the control module 20 comprises a second switch submodule 21 and a control submodule 22; the second switch submodule 21 is electrically connected with the delay module 10 and the control submodule 22 respectively, and the switch state of the second switch submodule 21 changes from on to off under the condition that the output signal changes from the second level to the first level; the control submodule 22 is electrically connected with the external power supply switch module 32 and the second switch submodule 21 respectively, and outputs the control signal to the external power supply switch module 32 under the condition that the second switch submodule 21 changes from on to off.

[0049] It should be noted that, in the case that the output signal of the delay module 10 is the second level, the switch state of the second switch sub-module 21 is turned on; in the case that the output signal of the delay module 10 is the first level, the switch state of the second switch sub-module 21 is turned off.

[0050] In the embodiment of the utility model, in the case that the output signal of the delay module 10 is changed from the second level to the first level, the second switch sub-module 21 is changed from being turned on to being turned off, and sends the corresponding trigger signal to the control sub-module 22, and in the case that the second switch sub-module 21 is changed from being turned on to being turned off, the control sub-module 22 sends the control signal to the external power supply switch module 32, and the external power supply switch module 32 is turned off after receiving the control signal, so as to realize the power-off of the mainboard 30.

[0051] Optionally, in some embodiments, the second switch sub-module 21 comprises a third switch device Q3, a fifth resistor R5 and a sixth resistor R6; the first end of the fifth resistor R5 is electrically connected with the external power supply, the second end of the fifth resistor R5 is electrically connected with the input end of the control sub-module 22 and the first end of the third switch device Q3 respectively; the first end of the sixth resistor R6 is electrically connected with the external power supply, the second end of the sixth resistor R6 is electrically connected with the output end of the delay module 10 and the control end of the third switch device Q3 respectively; the first end of the third switch device Q3 is electrically connected with the input end of the control sub-module 22, the control end of the third switch device Q3 is electrically connected with the output end of the delay module 10, and the second end of the third switch device Q3 is grounded.

[0052] Specifically, in some embodiments, the third switch device Q3 is an NMOS tube; in other embodiments, the third switch device Q3 is an NPN triode.

[0053] In the embodiment of the utility model, the fifth resistor R5 and the sixth resistor R6 are pull-up resistors; in the case that the received output signal of the delay module 10 is low level, the control end of the third switch device Q3 is pulled low by the output end of the delay module 10, and the third switch device Q3 is turned off; in the case that the received output signal of the delay module 10 is high level, the control end of the third switch device Q3 is high level; in the case that the output signal of the delay module 10 is changed from the second level to the first level, the third switch device Q3 is changed from being turned on to being turned off according to the received output signal, and then sends the corresponding trigger signal to the control sub-module 22, and in the case that the third switch device Q3 is changed from being turned on to being turned off, the control sub-module 22 sends the control signal to the external power supply switch module 32 according to the trigger signal, and the external power supply switch module 32 is turned off after receiving the control signal, so as to realize the power-off of the mainboard 30.

[0054] Optionally, in some embodiments, the control submodule 22 comprises a D flip-flop chip U2, a seventh resistor R7 and an eighth resistor R8; a first end of the seventh resistor R7 is electrically connected with an output end of the second switch submodule 21, and a second end of the seventh resistor R7 is electrically connected with a clock input end U2a of the D flip-flop chip U2; a first end of the eighth resistor R8 is electrically connected with an output end U2b of the D flip-flop chip U2, and a second end of the eighth resistor R8 is electrically connected with a control end of the external power supply switch module 32.

[0055] In some embodiments, the control submodule 22 further comprises a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13 and a third capacitor C3; a first end of the tenth resistor R10 is electrically connected with an external power supply, and a second end of the tenth resistor R10 is electrically connected with an asynchronous set input end U2c of a first D flip-flop in the D flip-flop chip U2 and a first end of the third capacitor C3, respectively; a second end of the third capacitor C3 is grounded; a first end of the eleventh resistor R11 is electrically connected with an external power supply, and a second end of the eleventh resistor R11 is electrically connected with an asynchronous clear input end U2d of the first D flip-flop in the D flip-flop chip U2; a first end of the twelfth resistor R12 is electrically connected with a second end of the seventh resistor R7, and a second end of the twelfth resistor R12 is grounded; a first end of the thirteenth resistor R13 is electrically connected with a clock input end U2g, a data input end U2f, an asynchronous clear input end U2e and an asynchronous set input end U2h of a second D flip-flop in the D flip-flop chip U2, respectively, and a second end of the thirteenth resistor R13 is grounded; a clock input end U2a of the D flip-flop chip U2 is a clock input end of the first D flip-flop in the D flip-flop chip U2, an output end U2b of the D flip-flop chip U2 is an output end of the first D flip-flop in the D flip-flop chip U2, an inverted output end U2i of the first D flip-flop in the D flip-flop chip U2 is electrically connected with a data input end U2j of the first D flip-flop in the D flip-flop chip U2, a grounding end U2k of the D flip-flop chip U2 is grounded, and a power supply end U2l of the D flip-flop chip U2 is electrically connected with an external power supply.

[0056] Wherein, the tenth resistor R10 and the eleventh resistor R11 are current limiting resistors, the twelfth resistor R12 is a voltage dividing resistor, the thirteenth resistor R13 is a pull-down resistor, and the third capacitor C3 is a filter capacitor.

[0057] In the embodiments of the utility model, the seventh resistor R7 and the eighth resistor R8 are current limiting resistors; the D flip-flop chip U2 sends a control signal to the external power supply switch module 32 when the second switch submodule 21 changes from being turned on to being disconnected, and the external power supply switch module 32 is disconnected after receiving the control signal, so as to realize the power-off of the mainboard 30.

[0058] Specifically, in some embodiments, the delay power-off circuit of the mainboard comprises a delay module 10 and a control module 20; the delay module 10 comprises a first switch submodule 11 and a delay submodule 12; the first switch submodule 11 comprises a first switch device Q1, a first resistor R1 and a second resistor R2; the delay submodule 12 comprises a timer chip U1; the control module 20 comprises a second switch submodule 21 and a control submodule 22; the second switch submodule 21 comprises a third switch device Q3, a fifth resistor R5 and a sixth resistor R6; the control submodule 22 comprises a D flip-flop chip U2, a seventh resistor R7 and an eighth resistor R8;

[0059] The first end of the first resistor R1 is electrically connected with an external power supply, the second end of the first resistor R1 is electrically connected with the trigger end U1a of the timer chip U1 and the first end of the first switch device Q1 respectively; the first end of the second resistor R2 is electrically connected with the output end of the main control chip 31, the control end of the first switch device Q1 is electrically connected with the output end of the main control chip 31, and the second end of the second resistor R2 is grounded; the first end of the first switch device Q1 is electrically connected with the trigger end U1a of the timer chip U1, the control end of the first switch device Q1 is electrically connected with the output end of the main control chip 31, and the second end of the first switch device Q1 is grounded; the output end U1b of the timer chip U1 is electrically connected with the second end of the sixth resistor R6 and the control end of the third switch device Q3 respectively;

[0060] The first end of the fifth resistor R5 is electrically connected with an external power supply, the second end of the fifth resistor R5 is electrically connected with the first end of the seventh resistor R7 and the first end of the third switch device Q3 respectively; the first end of the sixth resistor R6 is electrically connected with an external power supply, and the second end of the sixth resistor R6 is electrically connected with the control end of the third switch device Q3; the first end of the third switch device Q3 is electrically connected with the first end of the seventh resistor R7, and the second end of the third switch device Q3 is grounded;

[0061] The second end of the seventh resistor R7 is electrically connected with the clock input end U2a of the D flip-flop chip U2; the first end of the eighth resistor R8 is electrically connected with the output end U2b of the D flip-flop chip U2, and the second end of the eighth resistor R8 is electrically connected with the control end of the external power supply switch module 32.

[0062] In the embodiment of the utility model, the output end U2b of D flip-flop chip U2 is low by default, and the inverted output end U2i of the first D flip-flop in D flip-flop chip U2 is high, because the inverted output end U2i of the first D flip-flop in D flip-flop chip U2 is electrically connected with the data input end U2j of the first D flip-flop in D flip-flop chip U2, so the data input end U2j of the first D flip-flop in D flip-flop chip U2 is high;

[0063] In the case of performing the power-on operation on the electronic device, the delay module 10 and the control module 20 are powered on, the control end of the third switch device Q3 is pulled high by the sixth resistor R6, the third switch device Q3 is turned on, the clock input end U2a of the D flip-flop chip U2 is pulled low through the third switch device Q3, at the same time, the control end of the first switch device Q1 is pulled low by the second resistor R2, the first switch device Q1 is turned off, the trigger end U1a of the timer chip U1 is pulled high by the first resistor R1, the output end U1b of the timer chip U1 outputs a low-level signal, the control end of the third switch device Q3 is pulled low, the third switch device Q3 is turned off, the clock input end U2a of the D flip-flop chip U2 is pulled high through the fifth resistor R5 and the seventh resistor R7, that is, the clock input end U2a of the D flip-flop chip U2 changes from low level to high level, at this time, the signal output by the output end U2b of the D flip-flop chip U2 is the same as the data input end U2j of the first D flip-flop in the D flip-flop chip U2, that is, the output end U2b of the D flip-flop chip U2 changes to high level, that is, a control signal is formed to make the external power supply switch module 32 conductive, in the case that the external power supply switch module 32 is conductive, the mainboard 30 is powered on, and the inverting output end U2i of the first D flip-flop in the D flip-flop chip U2 changes to low level, the data input end U2j of the first D flip-flop in the D flip-flop chip U2 is low level.

[0064] In the case of performing the power-on operation on the electronic device, the delay module 10 and the control module 20 are powered on, the control end of the third switch device Q3 is pulled high by the sixth resistor R6, the third switch device Q3 is turned on, the clock input end U2a of the D flip-flop chip U2 is pulled low through the third switch device Q3, at the same time, the control end of the first switch device Q1 is pulled low by the second resistor R2, the first switch device Q1 is turned off, the trigger end U1a of the timer chip U1 is pulled high by the first resistor R1, the output end U1b of the timer chip U1 outputs a low-level signal, the control end of the third switch device Q3 is pulled low, the third switch device Q3 is turned off, the clock input end U2a of the D flip-flop chip U2 is pulled high through the fifth resistor R5 and the seventh resistor R7, that is, the clock input end U2a of the D flip-flop chip U2 changes from low level to high level, at this time, the signal output by the output end U2b of the D flip-flop chip U2 is the same as the data input end U2j of the first D flip-flop in the D flip-flop chip U2, that is, the output end U2b of the D flip-flop chip U2 changes to high level, that is, a control signal is formed to make the external power supply switch module 32 conductive, in the case that the external power supply switch module 32 is conductive, the mainboard 30 is powered on, and the inverting output end U2i of the first D flip-flop in the D flip-flop chip U2 changes to low level, the data input end U2j of the first D flip-flop in the D flip-flop chip U2 is low level.

[0065] In other embodiments, the delay power-off circuit of the mainboard comprises a delay module 10 and a control module 20; the delay module 10 comprises a first switch submodule 11 and a delay submodule 12; the first switch submodule 11 comprises a second switch device Q2, a third resistor R3 and a fourth resistor R4; the delay submodule 12 comprises a timer chip U1; the control module 20 comprises a second switch submodule 21 and a control submodule 22; the second switch submodule 21 comprises a third switch device Q3, a fifth resistor R5 and a sixth resistor R6; the control submodule 22 comprises a D flip-flop chip U2, a seventh resistor R7 and an eighth resistor R8;

[0066] The first end of the third resistor R3 is electrically connected with an external power supply, the second end of the third resistor R3 is electrically connected with the trigger end U1a of the timer chip U1 and the first end of the second switch device Q2 respectively; the first end of the fourth resistor R4 is electrically connected with the external power supply, the second end of the fourth resistor R4 is electrically connected with the output end of the main control chip 31, and the second end of the fourth resistor R4 is electrically connected with the control end of the second switch device Q2; the first end of the second switch device Q2 is electrically connected with the trigger end U1a of the timer chip U1, the control end of the second switch device Q2 is electrically connected with the output end of the main control chip 31, and the second end of the second switch device Q2 is grounded; the output end U1b of the timer chip U1 is electrically connected with the second end of the sixth resistor R6 and the control end of the third switch device Q3 respectively;

[0067] The first end of the fifth resistor R5 is electrically connected with an external power supply, the second end of the fifth resistor R5 is electrically connected with the first end of the seventh resistor R7 and the first end of the third switch device Q3 respectively; the first end of the sixth resistor R6 is electrically connected with an external power supply, and the second end of the sixth resistor R6 is electrically connected with the control end of the third switch device Q3; the first end of the third switch device Q3 is electrically connected with the first end of the seventh resistor R7, and the second end of the third switch device Q3 is grounded;

[0068] The second end of the seventh resistor R7 is electrically connected with the clock input end U2a of the D flip-flop chip U2; the first end of the eighth resistor R8 is electrically connected with the output end U2b of the D flip-flop chip U2, and the second end of the eighth resistor R8 is electrically connected with the control end of the external power supply switch module 32.

[0069] In the embodiment of the utility model, the output end U2b of D flip-flop chip U2 is low by default, then the inverse output end U2i of the first D flip-flop in D flip-flop chip U2 is high, because the inverse output end U2i of the first D flip-flop in D flip-flop chip U2 is electrically connected with the data input end U2j of the first D flip-flop in D flip-flop chip U2, then the data input end U2j of the first D flip-flop in D flip-flop chip U2 is high;

[0070] In the case of performing the power-on operation on the electronic device, the delay module 10 and the control module 20 are powered on, the control end of the third switch device Q3 is pulled high by the sixth resistor R6, the third switch device Q3 is turned on, the clock input end U2a of the D flip-flop chip U2 is pulled low through the third switch device Q3, at the same time, the control end of the second switch device Q2 is pulled high by the fourth resistor R4, the second switch device Q2 is turned off, the trigger end U1a of the timer chip U1 is pulled high by the third resistor R3, the output end U1b of the timer chip U1 outputs a low-level signal, the control end of the third switch device Q3 is pulled low, the third switch device Q3 is turned off, the clock input end U2a of the D flip-flop chip U2 is pulled high through the fifth resistor R5 and the seventh resistor R7, that is, the clock input end U2a of the D flip-flop chip U2 changes from low level to high level, at this time, the signal output by the output end U2b of the D flip-flop chip U2 is the same as the data input end U2j of the first D flip-flop in the D flip-flop chip U2, that is, the output end U2b of the D flip-flop chip U2 changes to high level, that is, a control signal is formed to make the external power supply switch module 32 conductive, in the case that the external power supply switch module 32 is conductive, the mainboard 30 is powered on, and the inverting output end U2i of the first D flip-flop in the D flip-flop chip U2 changes to low level, the data input end U2j of the first D flip-flop in the D flip-flop chip U2 is low level.

[0071] In the case of performing the power-on operation on the electronic device, the delay module 10 and the control module 20 are powered on, the control end of the third switch device Q3 is pulled high by the sixth resistor R6, the third switch device Q3 is turned on, the clock input end U2a of the D flip-flop chip U2 is pulled low through the third switch device Q3, at the same time, the control end of the second switch device Q2 is pulled high by the fourth resistor R4, the second switch device Q2 is turned off, the trigger end U1a of the timer chip U1 is pulled high by the third resistor R3, the output end U1b of the timer chip U1 outputs a low-level signal, the control end of the third switch device Q3 is pulled low, the third switch device Q3 is turned off, the clock input end U2a of the D flip-flop chip U2 is pulled high through the fifth resistor R5 and the seventh resistor R7, that is, the clock input end U2a of the D flip-flop chip U2 changes from low level to high level, at this time, the signal output by the output end U2b of the D flip-flop chip U2 is the same as the data input end U2j of the first D flip-flop in the D flip-flop chip U2, that is, the output end U2b of the D flip-flop chip U2 changes to high level, that is, a control signal is formed to make the external power supply switch module 32 conductive, in the case that the external power supply switch module 32 is conductive, the mainboard 30 is powered on, and the inverting output end U2i of the first D flip-flop in the D flip-flop chip U2 changes to low level, the data input end U2j of the first D flip-flop in the D flip-flop chip U2 is low level.

[0072] The utility model embodiment further provides a mainboard, including the delay power off circuit as described in the first aspect.

[0073] The implementation mode of the delay power off circuit in the mainboard is similar to the implementation mode of the delay power off circuit described above, and will not be repeated here.

[0074] The utility model embodiment further provides an electronic device, including the delay power off circuit as described in the first aspect, or the mainboard as described in the second aspect.

[0075] The implementation mode of the delay power off circuit in the electronic device is similar to the implementation mode of the delay power off circuit described above, and will not be repeated here.

[0076] In the related art, the Advanced Configuration and Power Interface (ACPI) standard is used to perform shutdown to avoid the problem of system file damage of the operating system caused by the power-off of the mainboard when the operating system is not closed, however, the ACPI standard needs to be supported by the electronic device, and the ACPI circuit is relatively complex and requires more power reset timing.

[0077] In the utility model embodiment, when the delay module 10 obtains the shutdown signal of the main control chip 31, the output signal of the delay module 10 changes from the first level to the second level, and after a preset time, the output signal changes from the second level to the first level, then the control module 20 outputs the control signal of the second level when the output signal changes from the second level to the first level, so that the external power switch module 32 is disconnected, to realize the power-off of the mainboard 30, the utility model embodiment is suitable for various types of electronic devices, and the circuit is simpler.

[0078] In the utility model embodiment, when the delay module 10 obtains the shutdown signal of the main control chip 31, the output signal of the delay module 10 changes from the first level to the second level, and after a preset time, the output signal changes from the second level to the first level, then the control module 20 outputs the control signal of the second level when the output signal changes from the second level to the first level, so that the external power switch module 32 is disconnected, to realize the power-off of the mainboard 30, in the process, the mainboard 30 is powered off to ensure that the operating system is closed before the mainboard 30 is powered off, to avoid the problem of system file damage of the operating system caused by the power-off of the mainboard 30 when the operating system is not closed.

[0079] The above merely describes preferred embodiments of the present application and is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0080] The above merely describes preferred embodiments of the present application and is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. The above merely describes preferred embodiments of the present application and is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A delay power-off circuit of a main board, characterized by, The application relates to a power-off delay module for a mainboard. The power-off delay module comprises a delay module and a control module; The delay module is electrically connected with the control module and a main control chip of the mainboard, and is used for changing a first level of a signal sent to the control module into a second level when receiving a power-off signal of the main control chip, and changing the second level into the first level after a preset time length; The control module is electrically connected with an external power supply switch module of the mainboard, and is used for outputting a control signal to control the mainboard to be powered off when the second level changes into the first level.

2. The time delay power off circuit of claim 1, wherein, The delay module comprises a first switch sub-module and a delay sub-module; The first switch sub-module is electrically connected with the delay sub-module, and is electrically connected with the main control chip and turned on when receiving the power-off signal; The delay sub-module is electrically connected with the control module, and is used for changing the first level into the second level when the first switch sub-module is turned on, and changing the second level into the first level after the preset time length.

3. The time delay power off circuit of claim 2, wherein, The first switch sub-module comprises a first switch device, a first resistor and a second resistor; A first end of the first resistor is electrically connected with an external power supply, and a second end of the first resistor is electrically connected with the delay sub-module and a first end of the first switch device respectively; A first end of the second resistor is electrically connected with the main control chip and a control end of the first switch device, and a second end of the second resistor is grounded; A first end of the first switch device is electrically connected with the delay sub-module, a control end of the first switch device is electrically connected with the main control chip, and a second end of the first switch device is grounded.

4. The time delay power off circuit of claim 2, wherein, The first switch sub-module comprises a second switch device, a third resistor and a fourth resistor; A first end of the third resistor is electrically connected with an external power supply, and a second end of the third resistor is electrically connected with the delay sub-module and a first end of the second switch device respectively; A first end of the fourth resistor is electrically connected with the external power supply, and a second end of the fourth resistor is electrically connected with the main control chip and a control end of the second switch device; A first end of the second switch device is electrically connected with the delay sub-module, a control end of the second switch device is electrically connected with the main control chip, and a second end of the second switch device is grounded.

5. A time delay tripping circuit according to any one of claims 2 to 4, wherein The delay sub-module comprises a timer chip; A trigger end of the timer chip is electrically connected with an output end of the first switch sub-module, and an output end of the timer chip is electrically connected with the control module.

6. The time delay power off circuit of claim 1, wherein, The control module comprises a second switch sub-module and a control sub-module; The second switch sub-module is electrically connected with the delay module and the control sub-module, and is used for controlling the second switch sub-module to change from being turned on to being turned off when the second level changes into the first level; The control sub-module is electrically connected with the external power supply switch module, and outputs the control signal to the external power supply switch module when the second switch sub-module changes from being turned on to being turned off.

7. The time delay power off circuit of claim 6, wherein, The second switch sub-module comprises a third switch device, a fifth resistor and a sixth resistor; The first end of the fifth resistor is electrically connected with the external power supply, and the second end of the fifth resistor is electrically connected with the input end of the control submodule and the first end of the third switch device respectively; The first end of the sixth resistor is electrically connected with the external power supply, and the second end of the sixth resistor is electrically connected with the delay module and the control end of the third switch device respectively; The first end of the third switch device is electrically connected with the input end of the control submodule, the control end of the third switch device is electrically connected with the delay module, and the second end of the third switch device is grounded.

8. The time delay power off circuit of claim 6, wherein, The control submodule comprises a D flip-flop chip, a seventh resistor and an eighth resistor; The first end of the seventh resistor is electrically connected with the output end of the second switch submodule, and the second end of the seventh resistor is electrically connected with the clock input end of the D flip-flop chip; The first end of the eighth resistor is electrically connected with the output end of the D flip-flop chip, and the second end of the eighth resistor is electrically connected with the external power supply switch module.

9. A main board, characterized by, The delay power-off circuit comprises the delay power-off circuit according to any one of claims 1 to 8.

10. An electronic device, comprising: The mainboard comprises the delay power-off circuit according to any one of claims 1 to 8 or the mainboard according to claim 9.

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