Vehicle-mounted display control system applied to FPGA platform

Abstract

The utility model provides a vehicle-mounted display control system applied to an FPGA (Field Programmable Gate Array) platform, which belongs to the technical field of automobile display and comprises a control module, a deserializer, an FPGA programmable logic chip and a display module, the output end of the control module is connected with the input end of the deserializer, the output end of the deserializer is connected with the input end of the FPGA programmable logic chip, and the output end of the FPGA programmable logic chip is connected with the display module. The output end of the FPGA programmable logic chip is connected with the input end of the deserializer, the output end of the FPGA programmable logic chip is connected with the input end of the display module, and the output end of the display module is connected with the input end of the FPGA programmable logic chip. By means of strong self-definition and efficiency of the FPGA programmable logic chip, high-efficiency communication at any rate can be realized, and the processing delay is as low as nanosecond level.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the automobile display technical field, specifically, the utility model relates to a kind of vehicle-mounted display control system applied to FPGA platform. BACKGROUND

[0002] With the development of modern technology and the improvement of people's living standards, the vehicle display platform puts forward higher and higher requirements on functional safety, response time, picture enhancement and other technical parameters, and the requirements on automobile display system are higher and higher.

[0003] Chinese patent 204712995U provides a kind of full virtual automobile instrument system suitable for quick start and the automobile of applying the system, the full virtual automobile instrument system includes: the main processor module of built-in operating system, for providing the graphical interface of automobile virtual instrument and automobile state data to image module, to display by display module;Auxiliary MCU module is connected with image module, it is used to send automobile state data to image module for display module to display when main processor module starts;And when main processor module starts to complete, the image module stops receiving automobile state data from single-chip microcomputer, to receive automobile state data from main processor module.

[0004] The prior art has low processing efficiency for display information, which cannot meet the needs of users. UTILITY MODEL CONTENT

[0005] The utility model aims at providing a kind of vehicle-mounted display control system applied to FPGA platform, to reach the technical purpose of improving system display information processing efficiency.

[0006] In order to achieve the above-mentioned purpose, the technical scheme adopted by the utility model is:

[0007] The utility model provides a kind of vehicle-mounted display control system applied to FPGA platform, including control module, deserializer, FPGA programmable logic chip and display module, the output of control module is connected the input of deserializer, the output of deserializer is connected the input of FPGA programmable logic chip, the output of FPGA programmable logic chip is connected the input of deserializer, the output of FPGA programmable logic chip is connected the input of display module, the output of display module is connected the input of FPGA programmable logic chip.

[0008] The control module inputs display information to deserializer, the deserializer outputs converted display information to FPGA programmable logic chip, the FPGA programmable logic chip inputs feedback signal to deserializer, the FPGA programmable logic chip outputs processed display information to display module, and the display module inputs feedback instruction to FPGA programmable logic chip.

[0009] The control module adopts a cabin domain controller.

[0010] The display module adopts a vehicle-mounted display screen.

[0011] The deserializer is connected with the FPGA programmable logic chip through a serial communication bus.

[0012] The FPGA programmable logic chip is connected with the vehicle-mounted display screen through a serial communication bus.

[0013] The technical effect of the utility model is:

[0014] (1) The utility model discloses a FPGA programmable logic chip's powerful self-defined nature and efficiency can realize arbitrary rate efficient communication, and processing delay is as low as nanosecond level.

[0015] (2) The deserializer of the utility model converts the serial data of the control module input into parallel data, and improves the processing speed of the FPGA programmable logic chip to data.

[0016] (3) The display information of the FPGA programmable logic chip input in the utility model has been enhanced, and better experience can be provided for users. BRIEF DESCRIPTION OF DRAWINGS

[0017] The present specification includes the following drawings, and the shown contents are respectively:

[0018] Figure 1 It is a logic structure block diagram of the utility model one kind application in FPGA platform's vehicle-mounted display control system;

[0019] Figure 1 The middle mark is: 1, control module;2, deserializer;3, FPGA programmable logic chip;4, display module. DETAILED DESCRIPTION

[0020] The specific embodiments of the utility model are further explained in detail by comparing the drawings and the description of the embodiments, the purpose is to help the skilled in the art to have more complete, accurate and thorough understanding to the utility model concept, technical scheme of the utility model, and help its implementation.

[0021] The utility model provides a kind of vehicle-mounted display control system applied to FPGA platform, including control module 1, deserializer 2, FPGA programmable logic chip 3 and display module 4, the input end of deserializer 2 is connected to the output end of control module 1, the input end of FPGA programmable logic chip 3 is connected to the output end of deserializer 2, the input end of display module 4 is connected to the output end of FPGA programmable logic chip 3, the input end of FPGA programmable logic chip 3 is connected to the output end of display module 4.

[0022] Control module 1 inputs display information to deserializer 2, deserializer 2 outputs converted display information to FPGA programmable logic chip 3, FPGA programmable logic chip 3 inputs feedback signal to deserializer 2, FPGA programmable logic chip 3 outputs processed display information to display module 4, and display module 4 inputs feedback instruction to FPGA programmable logic chip 3.

[0023] Control module 1 adopts cabin domain controller. Display module 4 adopts vehicle-mounted display screen. Deserializer 2 is connected to FPGA programmable logic chip 3 through serial communication bus. FPGA programmable logic chip 3 is connected to vehicle-mounted display screen through serial communication bus.

[0024] The utility model provides a kind of vehicle-mounted display control system applied to FPGA platform, including control module 1, deserializer 2, FPGA programmable logic chip 3 and display module 4, wherein control module 1 adopts cabin domain controller, for input display information, after the processing of deserializer 2 and FPGA programmable logic chip 3, display on display module 4.

[0025] Deserializer 2 is used to convert the serial data input by control module 1 into parallel data, improving the processing speed of FPGA programmable logic chip 3 on data.

[0026] FPGA programmable logic chip 3 is used to process the data input by deserializer 2 and output to display module 4. Unlike conventional microcontrollers, FPGA programmable logic chip 3 has faster processing speed and lower power consumption.

[0027] Display module 4 adopts vehicle-mounted display screen, for displaying the signal input by FPGA programmable logic chip 3. In the utility model, the display information input by FPGA programmable logic chip 3 has been image-enhanced, providing better experience for users.

[0028] The output of the cockpit domain controller is connected to the input of deserializer 2. The output of deserializer 2 is connected to the input of FPGA programmable logic chip 3. The output of FPGA programmable logic chip 3 is connected to the input of deserializer 2. The output of FPGA programmable logic chip 3 is connected to the input of the vehicle display screen. The output of the vehicle display screen is connected to the input of FPGA programmable logic chip 3.

[0029] The following details the input / output ports of FPGA programmable logic chip 3. Port `sys_clk` controls the system clock; port `sys_rst` controls the system reset; port `i2c_start_enable_in` initiates a start signal in idle state or after transmission completion (active high); port `i2c_write_enable_in` is the read / write selection signal for FPGA programmable logic chip 3, sampled before transmission to determine the data transmission direction (active high); port `i2c_stop_enable_in` initiates a stop signal after transmission completion (active high); port `i2c_transform_state_out` initiates an interrupt after ACK transmission completion to notify the top-level module to process data; port `i2c_data_in` latches external data into an internal register after start or data transmission completion, automatically resetting to 0 after transmission completion; port `i2c_ack_out` outputs the ACK status after data read, latched into an internal register only after data transmission completion, used to output the ACK status after I2C data read completion; port `i2c_ac_out` outputs the ACK status after data read, latched into an internal register only after data transmission completion.

[0030] The i2c_data_out port is used to receive data from the slave device; the i2c_ack_in port is used to input the write data ACK status, and outputs the corresponding ACK only after the data reception is completed; all of the above ports are connected to the deserializer.

[0031] The output port `i2c_port_scl_out` controls the SCL output of FPGA programmable logic chip 3; the output port `i2c_port_sda_out` controls the SDA output of FPGA programmable logic chip 3; the output port `i2c_port_sda_out_enable` enables the SDA output of FPGA programmable logic chip 3; and the input port `i2c_port_sda_in` controls the SDA input of FPGA programmable logic chip 3. These ports are connected to the display module.

[0032] The FPGA programmable logic chip 3 comprises a clock frequency division module, a logic switching module, an input and output control module 1 and an input and output module, wherein the clock frequency division module divides the frequency of the input system clock, reduces the high-speed clock to a specified frequency, and the parameter is adjustable. The logic switching module adopts a two-section Moore state machine to complete the logic output and state transition in the corresponding state. The input and output control module 1 can sample the control signal, complete the switching of the state, and output the logic level. The input and output module is a combination of a tristate gate and a register, which converts the SDA port of the controller logic part into an input and output port, registers a clock level, and is used for preventing the input and output signal from entering the metastable state and enhancing the anti-interference ability.

[0033] The FPGA programmable logic chip 3 has strong customizability and efficiency, and can realize efficient communication at an arbitrary rate, and the processing delay is as low as nanoseconds.

[0034] The above is an exemplary description of the utility model with reference to the drawings. Apparently, the specific implementation of the utility model is not limited by the above mode. As long as various non-essential improvements are made by adopting the method concept and technical scheme of the utility model; or the above concept and technical scheme of the utility model are directly applied to other occasions without improvement, all are within the protection scope of the utility model.

Claims

1. A vehicle display control system applied to an FPGA platform, characterized in that: The application relates to a display module for a vehicle, which comprises a control module, a deserializer, an FPGA programmable logic chip and a display module, wherein the output end of the control module is connected with the input end of the deserializer, the output end of the deserializer is connected with the input end of the FPGA programmable logic chip, the output end of the FPGA programmable logic chip is connected with the input end of the deserializer, the output end of the FPGA programmable logic chip is connected with the input end of the display module, and the output end of the display module is connected with the input end of the FPGA programmable logic chip.

2. The vehicle display control system applied to the FPGA platform according to claim 1, characterized in that: The control module inputs display information to the deserializer, the deserializer outputs converted display information to the FPGA programmable logic chip, the FPGA programmable logic chip inputs feedback signals to the deserializer, the FPGA programmable logic chip outputs processed display information to the display module, and the display module inputs feedback instructions to the FPGA programmable logic chip.

3. The vehicle display control system applied to the FPGA platform according to claim 1, characterized in that: The control module adopts a cabin domain controller.

4. The vehicle display control system applied to the FPGA platform according to claim 1, characterized in that: The display module adopts a vehicle-mounted display screen.

5. The vehicle display control system applied to the FPGA platform according to claim 1, characterized in that: The deserializer is connected with the FPGA programmable logic chip through a serial communication bus.

6. The vehicle display control system applied to the FPGA platform according to claim 1 or 4, characterized in that: The FPGA programmable logic chip is connected with the vehicle-mounted display screen through a serial communication bus.

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