High-power PIN tube single-pole double-throw switch circuit

Abstract

The utility model discloses a high-power PIN tube single-pole double-throw switch circuit, relates to the technical field of high-power PIN tube switches, aims to optimize the existing high-power PIN tube switch circuit, and comprises a PIN tube driving circuit and a switch radio frequency circuit, the input end of the PIN tube driving circuit is connected to the TTL through a NOR gate and a NOT gate OR, two kinds of gating signals are output and provided for the first branch and the second branch of the PIN tube driving circuit built by the PNP and the NPN respectively, and through switching conversion of the PNP and the NPN, one path is gated to output + 5V voltage, and the other path is gated to output-100V voltage. The two different bias voltages are loaded to the first PIN tube assembly and the second PIN tube assembly through the CT1 and the CT2, switching of the switch channels is completed, and the high-power PIN tube switch has the advantages of being high in adjustability, simple in circuit, easy to achieve, high in stability and low in cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic communication technology, in particular to a kind of single-pole double-throw switch circuit applied to high-power PIN tube. BACKGROUND

[0002] In recent years, with the rapid development of wireless communication technology and the increasing requirement of people for the flexibility of communication system, the radio frequency switch with signal switching, selection and other functions has been widely used. In the existing engineering design, the high-power PIN tube radio frequency switch generally adopts the way of combining resistance and NPN transistor for driving circuit design. At present, low-power PIN tube radio frequency switch can be relatively easily realized, but the system requires higher and faster switching time. Considering the influence of discrete component parasitic capacitance and inductance, this traditional driving circuit cannot realize the fast switching of PIN tube radio frequency switch, and it is difficult to realize the high negative voltage power supply required for ensuring the off of high-power switch, and the traditional switch radio frequency circuit has low power resistance. It has important theoretical and engineering significance to study the high-power PIN tube switch. SUMMARY

[0003] In view of the above defects or improvement needs of the prior art, the present application provides a PIN tube driving circuit and radio frequency circuit of high-power PIN tube single-pole double-throw switch, which aims to solve the technical problems of slow level conversion speed and low reliability of the existing high-power PIN radio frequency switch PIN tube driving circuit.

[0004] To achieve the above-mentioned purpose, the present application provides a high-power PIN tube single-pole double-throw switch circuit, which comprises a PIN tube driving circuit and a switch radio frequency circuit. The PIN tube driving circuit uses NOR gate and OR gate, and connects the input end to TTL. Two kinds of gating signals are output, which are provided to the first branch and the second branch of the PIN tube driving circuit built by PNP and NPN. Through the switching conversion of PNP and NPN, one road of gating output +5V voltage, and the other road of gating output-100V voltage. Two different bias voltages are loaded to the first and second PIN tube assemblies through CT1 and CT2, to complete the switching of switch channel, which specifically includes:

[0005] The PIN diode driving circuit includes a first branch and a second branch. The first and second branches share two voltage input terminals, two voltage output terminals, and a control terminal TTL. The first voltage input terminal is connected in series with fuse RB2 and then connected to node A1 of the first branch and node B1 of the second branch via two bypass capacitors. The second voltage input terminal is connected to node A2 of the first branch and node B2 of the second branch via parallel bypass capacitors. The control terminal signal is connected in series with a current-limiting resistor and then connected to the control terminals of the first and second branches via parallel voltage-dividing resistors. The first voltage output terminal is connected to the output terminal of the first branch via a series fuse, and the second voltage output terminal is connected to the output terminal of the second branch via a series fuse.

[0006] The switching radio frequency circuit includes a radio frequency input terminal and a first radio frequency branch and a second radio frequency branch connected to the radio frequency input terminal; the first radio frequency branch is connected to the first branch through a first voltage output terminal, and the second radio frequency branch is connected to the second branch through a second voltage output terminal.

[0007] The first branch includes: a NOR gate, a first push-pull circuit (P-type on top, N-type on bottom) and a second push-pull circuit (N-type on top, P-type on bottom) and a capacitor and resistor for biasing.

[0008] The base of the PNP transistor in the first push-pull circuit is connected to the output of a voltage divider circuit and an OR gate.

[0009] In the first push-pull circuit, a pull-down resistor is connected in parallel to the base of the NPN transistor to the A2 node, and then connected to the NOR output terminal through a series charging capacitor.

[0010] The emitters of the PNP and NPN transistors in the first push-pull circuit are connected to nodes A1 and A2, respectively.

[0011] A pull-down resistor is connected in series between the output of the first push-pull circuit and the input of the second push-pull circuit to node A2.

[0012] A capacitor to ground is connected in parallel to the emitter of the PNP transistor in the first push-pull circuit to the A1 node.

[0013] In the second push-pull circuit, the collectors of the PNP and NPN transistors are connected to nodes A1 and A2, respectively.

[0014] The emitters of the PNP and NPN transistors in the second push-pull circuit are connected to the output terminal of the first branch.

[0015] The second branch includes: a NOT gate, a third push-pull circuit (P-type on top, N-type on bottom) and a fourth push-pull circuit (N-type on top, P-type on bottom), as well as a capacitor and resistor for biasing.

[0016] The base of the PNP type transistor in the third push-pull circuit is connected to the output terminal of the voltage divider circuit and the NOR gate;

[0017] The base of the NPN transistor in the third push-pull circuit is connected in parallel with a pull-down resistor to the B2 node and is connected to the NOR output terminal through a series charging capacitor;

[0018] The emitter of the PNP type transistor and the emitter of the NPN type transistor in the third push-pull circuit are connected to the B1 node and the B2 node respectively;

[0019] A pull-down resistor is connected in series between the output terminal of the third push-pull circuit and the input terminal of the second push-pull circuit to the B2 node;

[0020] The emitter of the PNP type transistor in the third push-pull circuit is connected in parallel with a capacitor to the ground to the B1 node;

[0021] The collector of the PNP type transistor and the collector of the NPN type transistor in the second push-pull circuit are connected to the B1 node and the B2 node respectively;

[0022] The emitter of the PNP type transistor and the emitter of the NPN type transistor in the second push-pull circuit are connected to the output terminal of the second branch.

[0023] In the switch radio frequency circuit:

[0024] The radio frequency input terminal is connected in series with a first direct current blocking capacitor, a node O, a second direct current blocking capacitor, a first filter circuit and a first radio frequency output terminal in the first radio frequency branch in sequence;

[0025] The node O is further connected in parallel with a first direct current bias circuit and a first PIN tube assembly;

[0026] The radio frequency input terminal is connected in series with a third direct current blocking capacitor, a node P, a fourth direct current blocking capacitor, a second filter circuit and a second radio frequency output terminal in the second radio frequency branch in sequence;

[0027] The node P is further connected in parallel with a second direct current bias circuit and a second PIN tube assembly.

[0028] The first PIN tube assembly and the second PIN tube assembly comprise four PIN tube chips, the anode of each PIN tube chip is connected to a choke coil, the cathode is grounded, and CT1 and CT2 of the PIN tube driving circuit provide bias voltage for the first PIN tube assembly and the second PIN tube assembly through the choke coils L3 and L4 respectively.

[0029] The switching principle is as follows: when the first radio frequency branch works, the first PIN tube assembly is added with +5V voltage through CT1, and the second PIN tube assembly of the second radio frequency branch is added with -100V voltage through CT2, at this time, the first radio frequency branch works and the second radio frequency branch does not work. When the second radio frequency branch works, the first PIN tube assembly of the first radio frequency branch is added with -100V voltage, and the second PIN tube assembly of the second radio frequency branch is added with +5V voltage, at this time, the first radio frequency branch does not work and the second radio frequency branch works. The conversion of the communication system channel is completed by using this method.

[0030] The high-power PIN tube switch disclosed by the application has the advantages of high adjustability, simple circuit, easy realization, high stability and low cost. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a circuit schematic diagram of the PIN tube driving circuit of the embodiment.

[0032] Figure 2 is a circuit schematic diagram of the switch radio frequency circuit of the embodiment.

[0033] Figure 3 is a switch voltage switching diagram of the embodiment. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical scheme and advantages of the application more clear, the patent is further described in detail below in combination with the drawings.

[0035] The switch circuit of the application is a single-pole double-throw switch, and a PIN tube driving circuit is needed to select the switch channel. Since the PIN tube has the characteristics of signal conduction when positively biased and signal isolation when reversely biased, the transmission of the control signal is realized in the PIN tube switch circuit by loading positive and reverse bias on both ends of the two PIN tubes, so as to ensure that the PIN tube can be completely turned on or turned off under a high-power signal. The key to driving the high-power PIN tube is to provide a fast positive bias and a high reverse bias. The PIN tube also needs to have a low equivalent series resistance and a high reverse breakdown voltage.

[0036] As shown in Figure 1 and 2 , a high-power PIN tube single-pole double-throw switch provided by the application includes a PIN tube driving circuit and a switch radio frequency circuit.

[0037] The PIN tube driving circuit comprises a first branch and a second branch, the first branch and the second branch share two voltage input ends +5V and -100V, two voltage output ends CT1 and CT2 and a control end TTL, the first voltage input end +5V is connected with a fuse RB2 in series, and is connected with a node A1 of the first branch and a node B1 of the second branch through two bypass capacitors C16 and C17 respectively; the second voltage input end -100V is connected with a node A2 of the first branch and a node B2 of the second branch through bypass capacitors C022, C22, C023, C23, C024, C24, C025 and C25 in parallel; the control end signal is connected with a current-limiting resistor R8 in series, and is connected with a control end NORI of the first branch and a control end ORI of the second branch through parallel voltage dividing resistors R9 respectively; the first voltage output end CT1 is connected with an output end AO of the first branch through a fuse RB3 in series, and the second voltage output end CT2 is connected with an output end BO of the second branch through a fuse RB4 in series.

[0038] The switch radio frequency circuit comprises a radio frequency input end Pin and a first radio frequency branch and a second radio frequency branch connected with the radio frequency input end Pin; the first radio frequency branch is connected with the first branch through a first voltage output end CT1, and the second radio frequency branch is connected with the second branch through a second voltage output end CT2.

[0039] The first branch comprises an NOR gate, a first push-pull circuit (upper P and lower N type) and a second push-pull circuit (upper N and lower P type) and a capacitor resistor for biasing;

[0040] A base B of a PNP type transistor Q2 in the first push-pull circuit is connected with an output end 4 of an NOR gate through a voltage dividing circuit R10, R12 and C18;

[0041] A base B of an NPN transistor Q6 in the first push-pull circuit is connected with a node A2 through a pull-down resistor R14 in parallel, and is connected with an output end 4 of the NOR gate through a charging capacitor C20 in series;

[0042] Emitting electrodes E of the PNP type transistor Q2 and the NPN type transistor Q6 in the first push-pull circuit are connected with nodes A1 and A2 respectively;

[0043] A pull-down resistor R16 is connected with the node A2 in series between an output end 3 of the first push-pull circuit and an input end 1 of the second push-pull circuit;

[0044] An emitting electrode E of the PNP type transistor Q2 in the first push-pull circuit is connected with a node A1 through a ground capacitor C26 in parallel;

[0045] Collecting electrodes C of the PNP type transistor Q4 and the NPN type transistor Q7 in the second push-pull circuit are connected with nodes A1 and A2 respectively.

[0046] The emitter E of the PNP type transistor Q4 and the NPN type transistor Q7 in the second push-pull circuit is connected with the output end AO of the first branch.

[0047] The second branch comprises a NOR gate, a third push-pull circuit (upper P and lower N type) and a fourth push-pull circuit (upper N and lower P type) and a capacitor resistor for biasing;

[0048] The base B of the PNP type transistor Q3 in the third push-pull circuit is connected with the output end 4 of the NOR gate through a voltage dividing circuit R11, R13, C19;

[0049] The base B of the NPN transistor Q8 in the third push-pull circuit is connected with the B2 node through a pull-down resistor R15 in parallel, and is connected to the NOR output end 4 through a charging capacitor C21 in series;

[0050] The emitter E of the PNP type transistor Q3 and the NPN type transistor Q8 in the third push-pull circuit is connected with the B1 and B2 nodes respectively;

[0051] A pull-down resistor R17 is connected in series between the output end 3 of the third push-pull circuit and the input end 1 of the second push-pull circuit to the B2 node;

[0052] The emitter E of the PNP type transistor Q3 in the third push-pull circuit is connected with the B1 node through a capacitor C27 to the ground;

[0053] The collector C of the PNP type transistor Q5 and the NPN type transistor Q9 in the second push-pull circuit is connected with the B1 and B2 nodes respectively;

[0054] The emitter E of the PNP type transistor Q4 and the NPN type transistor Q7 in the second push-pull circuit is connected with the output end BO of the second branch.

[0055] The radio frequency input end Pin is connected in series with a first direct current blocking capacitor C32, a node O, a second direct current blocking capacitor C34, a first filter circuit and a first radio frequency output end Pout1 in the first radio frequency branch in turn;

[0056] The node O is also connected in parallel with a first direct current biasing circuit and a first PIN tube assembly;

[0057] The radio frequency input end Pin is connected in series with a third direct current blocking capacitor C33, a node P, a fourth direct current blocking capacitor C35, a second filter circuit and a second radio frequency output end Pout2 in the second radio frequency branch in turn;

[0058] The node P is also connected in parallel with a second direct current biasing circuit and a second PIN tube assembly.

[0059] The first PIN diode assembly and the second PIN diode assembly include four PIN diode chips. The positive terminal of each PIN diode chip is connected to a choke, and the negative terminal is grounded. CT1 and CT2 of the PIN diode drive circuit provide bias voltage to the first PIN diode assembly and the second PIN diode assembly through chokes L3 and L4, respectively, to control the conduction of the PIN diodes and thus realize the switching of the switching channel.

[0060] Preferably, the transistor in the PIN diode driving circuit is a high-voltage resistant transistor.

[0061] Preferably, the capacitor in the switching radio frequency circuit is a high-voltage capacitor.

[0062] Preferably, the inductors (L5-L8) of the first and second filter circuits are enameled wire wound inductors.

[0063] The PIN diode driver circuit uses external TTL high-low level conversion to enable its two outputs CT1 and CT2 to output positive bias (+5V) and reverse bias (-100V) respectively to supply the PIN diodes of the two channels, so that they are turned on and off respectively, thus completing the channel switching.

[0064] Both logic gates have their inputs connected to TTL, and are powered by an external +5V supply. When the TTL provides a high / low level, the first branch output CT1 of the driver circuit outputs +5V / -100V, and the second branch output CT2 outputs -100V / +5V. The bias voltage is applied to the positive terminals of the first and second PIN diodes of the switching RF circuit through chokes, respectively, causing the first PIN diode to turn on / off and the second PIN diode to turn off / on, thereby turning the first RF branch off / on and the second RF branch on / off.

[0065] The power handling capability of the switching RF circuit in this circuit mainly depends on the power dissipation and reverse breakdown voltage of the PIN diode chip. The selected PIN diode chip should have a small series resistance Rs and a high reverse breakdown voltage VB. In this embodiment, V1, V2, V3, and V4 are preferably WPX0038HB type PIN diode chips. DC blocking capacitors are placed before and after the PIN diodes to avoid DC signal interference to the RF path. In addition, a low-pass filter is connected before each output port to filter out harmonics in the circuit.

[0066] like Figure 3 The figure shown is the simulation result of the PIN diode driving circuit - the output voltage curve of the driving power supply. The switching time between +5V and -100V is 500ns. It can be seen from the result that the driving power supply achieves fast switching under high power and high voltage.

[0067] The above merely describes the preferred embodiments of the present application, and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, and improvement within the spirit and principle of the present application shall be included in the protection scope of the claims of the present application.

Claims

1. A high power PIN diode single pole double throw switch circuit, characterized by: The PIN tube driving circuit and the switch radio frequency circuit are included; The PIN tube driving circuit includes a first branch and a second branch, the first branch and the second branch share two voltage input ends (+5V and -100V), two voltage output ends (CT1 and CT2) and a control end (TTL), the first voltage input end (+5V) is connected with a fuse (RB2) in series, and is connected with A1 node of the first branch and B1 node of the second branch through two bypass capacitors (C16 and C17) respectively; the second voltage input end (-100V) is connected with A2 node of the first branch and B2 node of the second branch through bypass capacitors (C022, C22, C023, C23, C024, C24, C025 and C25) in parallel; the control end signal is connected with a current-limiting resistor (R8) in series, and is connected with the control end (NORI) of the first branch and the control end (ORI) of the second branch through parallel voltage dividing resistors (R9) respectively; the first voltage output end (CT1) is connected with the output end (AO) of the first branch through a fuse (RB3) in series, and the second voltage output end (CT2) is connected with the output end (BO) of the second branch through a fuse (RB4) in series. The switch radio frequency circuit includes a radio frequency input end (Pin) and a first radio frequency branch and a second radio frequency branch connected with the radio frequency input end (Pin); the first radio frequency branch is connected with the first branch through the first voltage output end (CT1), and the second radio frequency branch is connected with the second branch through the second voltage output end (CT2).

2. The single-knife double-throw switch circuit of the high-power PIN tube according to claim 1, characterized in that: The first branch includes an NOR gate (NOR), a first push-pull circuit (upper P and lower N type) and a second push-pull circuit (upper N and lower P type) and a capacitor resistor for biasing; The base (B) of the PNP type transistor (Q2) in the first push-pull circuit is connected with the output end (4) of the NOR gate through a voltage dividing circuit (R10, R12 and C18); The base (B) of the NPN transistor (Q6) in the first push-pull circuit is connected with the A2 node through a pull-down resistor (R14) in parallel, and is connected with the output end (4) of the NOR gate through a charging capacitor (C20) in series; The emitter (E) of the PNP type transistor (Q2) and the emitter (E) of the NPN type transistor (Q6) in the first push-pull circuit are connected with the A1 node and the A2 node respectively; A pull-down resistor (R16) is connected between the output end (3) of the first push-pull circuit and the input end (1) of the second push-pull circuit to the A2 node in series; The emitter (E) of the PNP type transistor (Q2) in the first push-pull circuit is connected with the A1 node through a ground capacitor (C26) in parallel; The collector (C) of the PNP type transistor (Q4) and the collector (C) of the NPN type transistor (Q7) in the second push-pull circuit are connected with the A1 node and the A2 node respectively; The emitter (E) of the PNP type transistor (Q4) and the emitter (E) of the NPN type transistor (Q7) in the second push-pull circuit are connected with the output end (AO) of the first branch.

3. The single-pole double-throw switch circuit of claim 1, wherein: the second branch comprises an OR gate, a third push-pull circuit (upper P and lower N) and a fourth push-pull circuit (upper N and lower P) and a capacitor resistor for biasing; a base (B) of a PNP transistor (Q3) in the third push-pull circuit is connected to an output (4) of the OR gate through a voltage dividing circuit (R11, R13, C19); a base (B) of an NPN transistor (Q8) in the third push-pull circuit is connected to a B2 node through a pull-down resistor (R15) in parallel and to the output (4) of the OR gate through a charging capacitor (C21) in series; emitters (E) of the PNP transistor (Q3) and the NPN transistor (Q8) in the third push-pull circuit are connected to B1 and B2 nodes, respectively; a pull-down resistor (R17) is connected to the B2 node in series between an output (3) of the third push-pull circuit and an input (1) of the second push-pull circuit; an emitter (E) of the PNP transistor (Q3) in the third push-pull circuit is connected to the B1 node through a ground capacitor (C27) in parallel; collectors (C) of a PNP transistor (Q5) and an NPN transistor (Q9) in the second push-pull circuit are connected to B1 and B2 nodes, respectively; and emitters (E) of the PNP transistor (Q4) and the NPN transistor (Q7) in the second push-pull circuit are connected to an output (BO) of the second branch. In the switch radio frequency circuit, the radio frequency input (Pin) is connected in series to a first direct current blocking capacitor (C32), a node O, a second direct current blocking capacitor (C34), a first filter circuit and a first radio frequency output (Pout1) in the first radio frequency branch; the node O is further connected in parallel to a first direct current biasing circuit and a first PIN tube assembly; the radio frequency input (Pin) is connected in series to a third direct current blocking capacitor (C33), a node P, a fourth direct current blocking capacitor (C35), a second filter circuit and a second radio frequency output (Pout2) in the second radio frequency branch; and the node P is further connected in parallel to a second direct current biasing circuit and a second PIN tube assembly. The first PIN tube assembly and the second PIN tube assembly comprise four PIN tube chips, each of which has a positive electrode connected to a choke coil and a negative electrode grounded, and a CT1 and a CT2 of a PIN tube driving circuit provide biasing voltage for the first PIN tube assembly and the second PIN tube assembly through the choke coils L3 and L4, respectively. The transistors in the PIN tube driving circuit are high-voltage transistors. The capacitors in the switch radio frequency circuit are high-voltage capacitors. The inductors (L5-L8) of the first filter circuit and the second filter circuit are enameled wire wound inductors. The PIN tube chips are WPX0038HB type PIN diode chips. ​ ​ 4. A high power PIN diode single pole double throw switch circuit according to claim 1, wherein ​ ​ ​ ​ ​ 5. A high power PIN diode single pole double throw switch circuit according to claim 4, characterised in that: ​ 6. A high power PIN diode single pole double throw switch circuit according to claim 2, wherein: ​ 7. A high power PIN diode single pole double throw switch circuit according to claim 1, wherein: ​ 8. A high power PIN diode single pole double throw switch circuit as claimed in claim 4, wherein: ​ 9. A high power PIN diode single pole double throw switch circuit as claimed in claim 5, wherein: ​

Images