Image scanning circuit, mainboard and electronic equipment

Abstract

The embodiment of the utility model provides an image scanning circuit, mainboard and electronic equipment, and relates to the technical field of image scanning, a first signal set output by a first controller in a system-on-chip is converted into a plurality of second signal sets through a preprocessing module, and scanning heads corresponding to the second signal sets are driven to work through the second signal sets. Image analog signals output by the scanning head corresponding to the analog-to-digital conversion module are converted into image digital signals through the analog-to-digital conversion module, and all the image digital signals are combined into a total image digital signal through the output module, so that a second controller forwards the total image digital signal to a processor in the system-on-chip for processing; therefore, each piece of image data is obtained, so that the system-on-chip can drive a plurality of scanning heads, and the adaptability of the system-on-chip to a multi-scanning-head driving scene is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to image scanning technical field especially, it relates to an image scanning circuit, mainboard and electronic equipment. BACKGROUND

[0002] The scanning device is one of the office essential equipment which can convert paper files, paper pictures and other scanning objects into digital format.

[0003] In the scanning device, a scanning head is driven by a system on chip (SoC) to perform image scanning.

[0004] In order to improve the image scanning efficiency, multiple scanning heads need to be driven to work, and the system on chip has poor adaptability to the multiple scanning head driving scene, resulting in failure of the system on chip to drive multiple scanning heads. UTILITY MODEL CONTENT

[0005] The utility model provides a kind of image scanning circuit, mainboard and electronic equipment to at least solve the problem of failure of the system on chip to drive multiple scanning heads due to poor adaptability of the system on chip to the multiple scanning head driving scene in prior art.

[0006] In the first aspect, the utility model embodiment provides an image scanning circuit, comprising: a preprocessing module, a plurality of analog-digital conversion modules, an output module, a system on chip and a plurality of scanning heads;

[0007] The preprocessing module is electrically connected to a first controller in the system on chip and the plurality of scanning heads respectively, converts a first signal set output by the first controller into a plurality of second signal sets, and the second signal set corresponds to the scanning head one by one;The second signal set is used to drive the scanning head corresponding to the second signal set to work;

[0008] The analog-digital conversion module corresponds to the scanning head one by one, and the analog-digital conversion module is electrically connected to the scanning head corresponding to the analog-digital conversion module, converts an image analog signal output by the scanning head corresponding to the analog-digital conversion module into an image digital signal;The image analog signal is an analog signal of image data collected by the scanning head;

[0009] The output module is electrically connected to each analog-digital conversion module, and the output module is electrically connected to a second controller in the system on chip, each image digital signal is combined into a total image digital signal, so that the second controller forwards the total image digital signal to a processor in the system on chip for processing, so as to obtain each image data.

[0010] Optionally, the preprocessing module comprises a first clock buffer, a second clock buffer and a signal amplification sub-module; the first signal set comprises a first clock signal, a first row trigger signal and a first driving signal group; the second signal set comprises a second clock signal, a second row trigger signal and a second driving signal group; the first clock buffer is electrically connected with the first controller and each of the scanning heads respectively, and copies the first clock signal into a plurality of the second clock signals; the second clock buffer is electrically connected with the first controller and each of the scanning heads respectively, and copies the first row trigger signal into a plurality of the second row trigger signals; the signal amplification sub-module is electrically connected with the first controller and each of the scanning heads respectively, and copies and signal-amplifies the first driving signal group to generate a plurality of the second driving signal groups.

[0011] Optionally, the first controller comprises a first output end, a second output end and n third output ends; the number of the scanning heads is m, each of the scanning heads comprises a first input end, a second input end and n third input ends; n and m are positive integers greater than 1; the preprocessing module comprises a first clock buffer, a second clock buffer and a signal amplification sub-module; the first clock buffer comprises a fourth input end and m fourth output ends; the second clock buffer comprises a fifth input end and m fifth output ends; the signal amplification sub-module comprises u sixth input ends and u sixth output ends; the fourth output ends correspond to the first input ends one by one; the fifth output ends correspond to the second input ends one by one; the third output ends have corresponding m sixth input ends; the third input ends have corresponding sixth output ends; u is the product of n and m; the fourth input end is electrically connected with the first output end, and the fourth output end is electrically connected with the first input end corresponding to the fourth output end; the fifth input end is electrically connected with the second output end, and the fifth output end is electrically connected with the second input end corresponding to the fifth output end; the third output end is electrically connected with each of the sixth input ends corresponding to the third output end, and the third input end is electrically connected with the sixth output end corresponding to the third input end.

[0012] Optionally, the signal amplification sub-module is a Darlington tube chip.

[0013] Optionally, the number of scanning heads is m, and each scanning head includes v seventh output terminals; the analog-to-digital conversion module includes v seventh input terminals and w eighth output terminals; the output module includes r eighth input terminals and r ninth output terminals; the second controller includes r ninth input terminals; m, v, and w are all positive integers greater than 1, and r is the product of w and m; each seventh output terminal corresponds one-to-one with each seventh input terminal; each eighth output terminal corresponds one-to-one with each eighth input terminal; each ninth output terminal corresponds one-to-one with each ninth input terminal; each seventh input terminal is electrically connected to its corresponding seventh output terminal; each eighth output terminal is electrically connected to its corresponding eighth input terminal; and each ninth output terminal is electrically connected to its corresponding ninth input terminal.

[0014] Optionally, each of the scanning heads includes a light source device and an image sensor; the preprocessing module is electrically connected to each of the light source devices and each of the image sensors; in the scanning head, the image sensor is electrically connected to the analog-to-digital conversion module corresponding to the scanning head.

[0015] Optionally, the light source device includes a plurality of light-emitting diodes; the preprocessing module is electrically connected to each of the light-emitting diodes.

[0016] Optionally, the analog-to-digital conversion module is an analog front-end device; the output module is a latch.

[0017] Secondly, embodiments of the present invention also provide a motherboard, including the image scanning circuit as described in the first aspect.

[0018] Thirdly, embodiments of the present invention also provide an electronic device, including the image scanning circuit as described in the first aspect, or the motherboard as described in the second aspect.

[0019] In this embodiment of the invention, a preprocessing module converts the first signal set output by the first controller in the system-on-a-chip into multiple second signal sets, thereby driving the scanning head corresponding to the second signal set. Then, an analog-to-digital conversion module converts the image analog signal output by the scanning head corresponding to the analog-to-digital conversion module into an image digital signal. Finally, an output module combines each image digital signal into a total image digital signal, which is then forwarded by the second controller to the processor in the system-on-a-chip for processing, thereby acquiring each image data. This enables the system-on-a-chip to drive multiple scanning heads, improving the adaptability of the system-on-a-chip to multi-scanning-head driving scenarios. Attached Figure Description

[0020] In order to more clearly illustrate the technical scheme of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0021] Figure 1 is a structural schematic diagram of an image scanning circuit provided by the embodiments of the present application;

[0022] Figure 2 is a specific structural schematic diagram of the image scanning circuit provided by the embodiments of the present application;

[0023] Figure 3 is another specific structural schematic diagram of the image scanning circuit provided by the embodiments of the present application.

[0024] Reference signs:

[0025] 10-preprocessing module; 11-first clock buffer; 111-fourth input end; 112-fourth output end; 12-second clock buffer; 121-fifth input end; 122-fifth output end; 13-signal amplification sub-module; 131-sixth input end; 132-sixth output end; 20-analog-to-digital conversion module; 201-seventh input end; 202-eighth output end; 30-output module; 301-eighth input end; 302-ninth output end; 40-system level chip; 41-first controller; 411-first output end; 412-second output end; 413-third output end; 42-second controller; 421-ninth input end; 43-processor; 50-scanning head; 51-light source device; 52-image sensor; 501-first input end; 502-second input end; 503-third input end; 504-seventh output end. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned purposes, features and advantages of the present application more apparent and easy to understand, the following will further describe the present application in combination with the drawings and specific embodiments.

[0027] Reference Figure 1The utility model discloses an image scanning circuit, comprising: preprocessing module 10, a plurality of analog -to -digital conversion module 20, output module 30, system level chip 40 and a plurality of scanning head 50, preprocessing module 10 respectively with first controller 41 in system level chip 40 and a plurality of scanning head 50 electricity is connected, with first controller 41 output first signal set is converted to a plurality of second signal set, second signal set with scanning head 50 one -to -one correspondence, second signal set is used for driving the second signal set corresponding scanning head 50 work, analog -to -digital conversion module 20 with scanning head 50 one -to -one correspondence, analog -to -digital conversion module 20 with the scanning head 50 of analog -to -digital conversion module 20 electricity is connected, with the scanning head 50 of analog -to -digital conversion module 20 output image analog signal is converted into image digital signal, image analog signal is the analog signal of image data that scanning head 50 gathers, output module 30 with every analog -to -digital conversion module 20 electricity is connected, output module 30 with second controller 42 in system level chip 40 electricity is connected, with every image digital signal combination is total image digital signal, for second controller 42 with total image digital signal is forwarded to the processor 43 of system level chip 40 handles to every image data is obtained accordingly.

[0028] It needs to be explained that the number of analog -to -digital conversion module 20 is same with the number of scanning head 50, the number of second signal set is same with the number of scanning head 50, the kind and number of signal in second signal set are same with the kind and number of signal in first signal set, image digital signal is the digital signal of image data that scanning head 50 gathers, and the data that total image digital signal represents includes the image data that every scanning head 50 scans.

[0029] Specifically, in some embodiments, the first signal set is generated by the first controller 41, the first signal set is converted into a plurality of second signal sets by the preprocessing module 10, the scanning heads 50 corresponding to the second signal sets are driven by the second signal sets to perform image scanning to obtain image analog signals, the image analog signals output by the scanning heads 50 corresponding to the analog-to-digital conversion modules 20 are converted into image digital signals by the analog-to-digital conversion modules 20, each image digital signal is combined into a total image digital signal by the output module 30, the total image digital signal is converted into a protocol by the second controller 42, and then is forwarded to the processor 43 in the system level chip 40, and each image data is obtained by the processor 43 according to the total image digital signal after the protocol conversion.

[0030] For example, the image scanning circuit comprises a preprocessing module 10, two analog-digital conversion modules 20 and an output module 30; the preprocessing module 10 is electrically connected with a first controller 41 in a system on chip 40 and two scanning heads 50 respectively, converts a first signal set output by the first controller 41 into two second signal sets, wherein one second signal set is used for driving a first scanning head 50 to work, and the other second signal set is used for driving a second scanning head 50 to work; the first scanning head 50 is electrically connected with a first analog-digital conversion module 20, and an image analog signal output by the first scanning head 50 is converted into an image digital signal of the first scanning head 50; the second scanning head 50 is electrically connected with a second analog-digital conversion module 20, and an image analog signal output by the second scanning head 50 is converted into an image digital signal of the second scanning head 50; the output module 30 is electrically connected with each analog-digital conversion module 20, and the output module 30 is also electrically connected with a second controller 42 in the system on chip 40; the output module 30 combines each image digital signal into a total image digital signal, so that the second controller 42 transmits the total image digital signal to a processor 43 in the system on chip 40 for processing, thereby obtaining each image data.

[0031] Specifically, the first scanning head 50 is located above a scanning object (for example, a paper document), and the second scanning head 50 is located below the scanning object, so as to realize double-sided scanning of the scanning object.

[0032] In the embodiment of the utility model, the first signal set output by the first controller 41 in the system on chip 40 is converted into a plurality of second signal sets by the preprocessing module 10, so as to drive the scanning head 50 corresponding to the second signal set to work through the second signal set, then the image analog signal output by the scanning head 50 corresponding to the analog-digital conversion module 20 is converted into an image digital signal by the analog-digital conversion module 20, and then each image digital signal is combined into a total image digital signal by the output module 30, so that the second controller 42 transmits the total image digital signal to the processor 43 in the system on chip 40 for processing, thereby obtaining each image data, so as to realize the driving of the plurality of scanning heads 50 by the system on chip 40, and improve the adaptability of the system on chip 40 to the driving scene of the plurality of scanning heads 50.

[0033] In addition, the first signal set output by the first controller 41 in the system on chip 40 is converted into a plurality of second signal sets by the preprocessing module 10, and the scanning head 50 corresponding to the second signal set is driven to work through the second signal set, so as to realize the simultaneous work of the plurality of scanning heads 50.

[0034] Optionally, referring to Figure 3In some embodiments, the preprocessing module 10 comprises a first clock buffer 11, a second clock buffer 12 and a signal amplification submodule 13; the first signal set comprises a first clock signal, a first row trigger signal and a first driving signal group; the second signal set comprises a second clock signal, a second row trigger signal and a second driving signal group; the first clock buffer 11 is electrically connected with the first controller 41 and each of the scan heads 50 respectively, and copies the first clock signal into a plurality of second clock signals; the second clock buffer 12 is electrically connected with the first controller 41 and each of the scan heads 50 respectively, and copies the first row trigger signal into a plurality of second row trigger signals; the signal amplification submodule 13 is electrically connected with the first controller 41 and each of the scan heads 50 respectively, and copies and amplifies the first driving signal group to generate a plurality of second driving signal groups.

[0035] It should be noted that the first clock buffer 11 and the second clock buffer 12 are both clock buffers (Buffer), which are devices for copying a clock source signal into a plurality of clock signals, and the clock buffer usually has the functions of clock distribution, format conversion and level conversion.

[0036] The first clock signal is the same as each of the second clock signals; the second clock signal corresponds to one of the scan heads 50, and the second clock signal is the clock signal of the scan head 50 corresponding to the second clock signal.

[0037] The first row trigger signal is the same as each of the second row trigger signals; the second row trigger signal corresponds to one of the scan heads 50, and the second row trigger signal is the Line Trigger signal of the scan head 50 corresponding to the second row trigger signal, so that the scan head 50 corresponding to the second row trigger signal acquires the image data of a row of pixels when the second row trigger signal is acquired.

[0038] The first driving signal group is the same as each of the second driving signal groups; the second driving signal group is used for driving the light source device 51 in the scan head 50 to emit light.

[0039] In the embodiment of the utility model, the first clock signal is copied into a plurality of second clock signals by the first clock buffer 11, the first row trigger signal is copied into a plurality of second row trigger signals by the second clock buffer 12, and the first driving signal group is copied and amplified by the signal amplification submodule 13 to generate a plurality of second driving signal groups, so that the first signal set output by the first controller 41 is converted into a plurality of second signal sets.

[0040] Optionally, in some embodiments, the first controller 41 comprises a first output end 411, a second output end 412 and n third output ends 413; the number of the scanning heads 50 is m, each of the scanning heads 50 comprises a first input end 501, a second input end 502 and n third input ends 503; n and m are both positive integers greater than 1; the preprocessing module 10 comprises a first clock buffer 11, a second clock buffer 12 and a signal amplification submodule 13; the first clock buffer 11 comprises a fourth input end 111 and m fourth output ends 112; the second clock buffer 12 comprises a fifth input end 121 and m fifth output ends 122; the signal amplification submodule 13 comprises u sixth input ends 131 and u sixth output ends 132; the fourth output end 112 corresponds to the first input end 501 one by one; the fifth output end 122 corresponds to the second input end 502 one by one; the third output end 413 has corresponding m sixth input ends 131; the third input end 503 has corresponding sixth output ends 132; u is the product of n and m; the fourth input end 111 is electrically connected with the first output end 411, and the fourth output end 112 is electrically connected with the first input end 501 corresponding to the fourth output end 112; the fifth input end 121 is electrically connected with the second output end 412, and the fifth output end 122 is electrically connected with the second input end 502 corresponding to the fifth output end 122; the third output end 413 is electrically connected with each of the sixth input ends 131 corresponding to the third output end 413, and the third input end 503 is electrically connected with the sixth output end 132 corresponding to the third input end 503.

[0041] For example, the first controller 41 comprises a first output end 411, a second output end 412 and 3 third output ends 413; the number of the scanning heads 50 is 2, each of the scanning heads 50 comprises a first input end 501, a second input end 502 and 3 third input ends 503;

[0042] The preprocessing module 10 comprises a first clock buffer 11, a second clock buffer 12 and a signal amplification submodule 13; the first clock buffer 11 comprises a fourth input end 111 and 2 fourth output ends 112; the second clock buffer 12 comprises a fifth input end 121 and 2 fifth output ends 122; the signal amplification submodule 13 comprises 6 sixth input ends 131 and 6 sixth output ends 132; the fourth output end 112 corresponds to the first input end 501 one by one; the fifth output end 122 corresponds to the second input end 502 one by one; the third output end 413 has corresponding 2 sixth input ends 131; the third input end 503 has corresponding sixth output ends 132;

[0043] The fourth input end 111 is electrically connected with the first output end 411, the first fourth output end 112 is electrically connected with the first input end 501 of the first scanning head 50, and the second fourth output end 112 is electrically connected with the first input end 501 of the second scanning head 50; the fifth input end 121 is electrically connected with the second output end 412, the first fifth output end 122 is electrically connected with the second input end 502 of the first scanning head 50, and the second fifth output end 122 is electrically connected with the second input end 502 of the second scanning head 50; the first third output end 413 is electrically connected with the first sixth input end 131 and the fourth sixth input end 131, the second third output end 413 is electrically connected with the second sixth input end 131 and the fifth sixth input end 131, and the third third output end 413 is electrically connected with the third sixth input end 131 and the sixth sixth input end 131; the first sixth output end 132 is electrically connected with the first third input end 503 of the first scanning head 50, the second sixth output end 132 is electrically connected with the second third input end 503 of the first scanning head 50, the third sixth output end 132 is electrically connected with the third third input end 503 of the first scanning head 50, the fourth sixth output end 132 is electrically connected with the first third input end 503 of the second scanning head 50, the fifth sixth output end 132 is electrically connected with the second third input end 503 of the second scanning head 50, and the sixth sixth output end 132 is electrically connected with the third third input end 503 of the second scanning head 50.

[0044] In the embodiment of the utility model, through the fourth input end 111 of first clock buffer 11 receives first clock signal, and through first clock buffer 11 copies first clock signal as a plurality of second clock signals, again through the fourth output end 112 of first clock buffer 11 to the second clock signal corresponding scanning head 50 input second clock signal, so that each scanning head 50 obtains the same clock signal and keeps clock synchronization;Through the fifth input end 121 of second clock buffer 12 receives first row trigger signal, again through second clock buffer 12 copies first row trigger signal as a plurality of second row trigger signals, then through the fifth output end 122 of second clock buffer 12 to the fifth output end 122 corresponding scanning head 50 input second row trigger signal, so that each scanning head 50 obtains the same row trigger signal and realizes the synchronous scanning of a row of pixels, for example each scanning head 50 scans a scanning object, through a plurality of scanning heads 50, the synchronous scanning of the same row of pixels of a plurality of scanning objects can be realized;Through the sixth input end 131 of signal amplification submodule 13 receives and copies m first drive signal groups, and through signal amplification submodule 13 signal amplification is carried out to first drive signal group, generates the second drive signal group corresponding to first drive signal group, then through the sixth output end 132 of signal amplification submodule 13 to the n sixth output end 132 corresponding scanning head 50 input second drive signal group, so that each scanning head 50 obtains the same second drive signal group, thereby realizing the synchronous control of the light emission of light source device 51 in each scanning head 50.

[0045] Optionally, in some embodiments, the signal amplification submodule 13 is a Darlington tube chip.

[0046] In the embodiment of the utility model, since the signal amplification submodule 13 is a Darlington tube chip, the first drive signal group can be copied and signal amplified to generate a plurality of second drive signal groups.

[0047] Optionally, in some embodiments, the number of the scanning heads 50 is m, each of the scanning heads 50 includes v seventh output terminals 504; the analog-to-digital conversion module 20 includes v seventh input terminals 201 and w eighth output terminals 202; the output module 30 includes r eighth input terminals 301 and r ninth output terminals 302; the second controller 42 includes r ninth input terminals 421; m, v and w are positive integers greater than 1, and r is the product of w and m; the seventh output terminals 504 correspond to the seventh input terminals 201 one by one; the eighth output terminals 202 correspond to the eighth input terminals 301 one by one; the ninth output terminals 302 correspond to the ninth input terminals 421 one by one; the seventh input terminals 201 are electrically connected to the seventh output terminals 504 corresponding to the seventh input terminals 201; the eighth input terminals 301 are electrically connected to the eighth output terminals 202 corresponding to the eighth input terminals 301; and the ninth input terminals 421 are electrically connected to the ninth output terminals 302 corresponding to the ninth input terminals 421.

[0048] It should be noted that the number of bits of the image analog signals output by the scanning heads 50 is v, the seventh output terminals 504 correspond to the bits of the image analog signals one by one, and the seventh output terminals 504 output the signals of the bits corresponding to the seventh output terminals 504 in the image analog signals; the number of bits of the image digital signals output by the analog-to-digital conversion module 20 is w, the eighth output terminals 202 correspond to the bits of the image digital signals one by one, and the eighth output terminals 202 output the signals of the bits corresponding to the eighth output terminals 202 in the image digital signals; and the number of bits of the total image digital signals output by the output module 30 is r, the ninth output terminals 302 correspond to the bits of the total image digital signals one by one, and the ninth output terminals 302 output the signals of the bits corresponding to the total image digital signals in the total image digital signals.

[0049] For example, the number of the scanning heads 50 is 2, each of the scanning heads 50 includes 3 seventh output terminals 504; the analog-to-digital conversion module 20 includes 3 seventh input terminals 201 and 8 eighth output terminals 202; the output module 30 includes 16 eighth input terminals 301 and 16 ninth output terminals 302; the second controller 42 includes 16 ninth input terminals 421; the seventh output terminals 504 correspond to the seventh input terminals 201 one by one; the eighth output terminals 202 correspond to the eighth input terminals 301 one by one; and the ninth output terminals 302 correspond to the ninth input terminals 421 one by one;

[0050] The first seventh input end 201 of the first scanning head 50 is electrically connected with the first seventh output end 504 of the first analog-digital conversion module 20, the second seventh input end 201 of the first scanning head 50 is electrically connected with the second seventh output end 504 of the first analog-digital conversion module 20, the third seventh input end 201 of the first scanning head 50 is electrically connected with the third seventh output end 504 of the first analog-digital conversion module 20, the first seventh input end 201 of the second scanning head 50 is electrically connected with the first seventh output end 504 of the second analog-digital conversion module 20, the second seventh input end 201 of the second scanning head 50 is electrically connected with the second seventh output end 504 of the second analog-digital conversion module 20, the third seventh input end 201 of the second scanning head 50 is electrically connected with the third seventh output end 504 of the second analog-digital conversion module 20; the first eighth output end 202 of the first analog-digital conversion module 20 is electrically connected with the first eighth input end 301 of the output module 30, the second eighth output end 202 of the first analog-digital conversion module 20 is electrically connected with the second eighth input end 301 of the output module 30, and so on, the eighth eighth output end 202 of the first analog-digital conversion module 20 is electrically connected with the eighth eighth input end 301 of the output module 30; the first eighth output end 202 of the second analog-digital conversion module 20 is electrically connected with the ninth eighth input end 301 of the output module 30, the second eighth output end 202 of the second analog-digital conversion module 20 is electrically connected with the tenth eighth input end 301 of the output module 30, and so on, the eighth eighth output end 202 of the second analog-digital conversion module 20 is electrically connected with the sixteenth eighth input end 301 of the output module 30;

[0051] The first ninth output end 302 of the output module 30 is electrically connected with the first ninth input end 421 of the second controller 42, the second ninth output end 302 of the output module 30 is electrically connected with the second ninth input end 421 of the second controller 42, and so on, the sixteenth ninth output end 302 of the output module 30 is electrically connected with the sixteenth ninth input end 421 of the second controller 42;

[0052] It should be noted that the three-bit image analog signals are received through the three seventh input ends 201 of the analog-digital conversion module 20, the image analog signals are converted into image digital signals through the analog-digital conversion module 20, then eight-bit image digital signals are output through the eight eighth output ends 202 of the analog-digital conversion module 20, two eight-bit image digital signals are received through the 16 eighth input ends 301 of the output module 30, each image digital signal is combined into a total image digital signal through the output module 30, and sixteen-bit total image digital signals are output through the 16 ninth output ends 302 of the output module 30, so that the second controller 42 receives the sixteen-bit total image digital signals through the 16 ninth input ends 421 of the second controller 42, the sixteen-bit total image digital signals are protocol-converted through the second controller 42, and then forwarded to the processor 43 in the system-on-chip 40 for processing, so that each image data is obtained.

[0053] In the embodiment of the utility model, v-bit image analog signals are received through the v seventh input ends 201 of the analog-digital conversion module 20, the image analog signals are converted into image digital signals through the analog-digital conversion module 20, then w-bit image digital signals are output through the w eighth output ends 202 of the analog-digital conversion module 20, m w-bit image digital signals are received through the r eighth input ends 301 of the output module 30, each image digital signal is combined into a total image digital signal through the output module 30, and r-bit total image digital signals are output through the r ninth output ends 302 of the output module 30, so that the second controller 42 receives the r-bit total image digital signals through the r ninth input ends 421 of the second controller 42, the r-bit total image digital signals are protocol-converted through the second controller 42, and then forwarded to the processor 43 in the system-on-chip 40 for processing, so that each image data is obtained.

[0054] Since the data represented by the total image digital signals includes the clock-synchronized image data scanned by each scanning head 50, the scanning data deviation and disorder are avoided, and the scanning quality is ensured.

[0055] Optionally, referring to Figure 2 In some embodiments, each scanning head 50 includes a light source device 51 and an image sensor 52 (CIS, Contact Image Sensor); the preprocessing module 10 is electrically connected with each light source device 51 and each image sensor 52; in the scanning head 50, the image sensor 52 is electrically connected with the corresponding analog-digital conversion module 20 of the scanning head 50.

[0056] It should be noted that the light source device 51 emits light in the case that the light source device 51 receives the second clock signal, the first row trigger signal and the first driving signal group; the image sensor 52 collects image data in the case that the image sensor 52 receives the second clock signal and the first row trigger signal.

[0057] In the embodiment of the utility model, in the case that the scanning head 50 obtains the second clock signal, the first row trigger signal and the first driving signal group, the light source device 51 in the scanning head 50 emits light, and the image data collected by the image sensor 52 in the scanning head 50 generates image analog signal and outputs to the analog-digital conversion module 20 corresponding to the scanning head 50.

[0058] Optionally, in some embodiments, the light source device 51 includes a plurality of light emitting diodes (LEDs); the preprocessing module 10 is electrically connected with each of the light emitting diodes.

[0059] It should be noted that the first driving signal group includes n first driving signals, the second driving signal group includes n second driving signals, the first driving signal corresponds to the second driving signal one by one, and the first driving signal corresponds to the same second driving signal as the first driving signal; the light source device 51 includes n types of light emitting diodes, the second driving signal corresponds to the type of the light emitting diode in the light source device 51 one by one, and the second driving signal is used to drive the light emitting diode of the type corresponding to the second driving signal to emit light.

[0060] For example, the first controller 41 includes 3 third output ends 413; the number of the scanning head 50 is 2, and each scanning head 50 includes 3 third input ends 503; the signal amplification sub-module 13 includes 6 sixth input ends 131 and 6 sixth output ends 132;

[0061] The light source device 51 includes 3 types of light emitting diodes, which are red (Red) light emitting diodes, green (Green) light emitting diodes and blue (Blue) light emitting diodes, the first driving signal group includes 3 first driving signals, which are first driving signal E1, first driving signal E2 and first driving signal E3; the second driving signal group includes n second driving signals, which are second driving signal F1, second driving signal F2 and second driving signal F3, the first driving signal E1 corresponds to the second driving signal F1, the first driving signal E2 corresponds to the second driving signal F2, and the first driving signal E3 corresponds to the second driving signal F3;

[0062] The first driving signal E1 is output through the first third output end 413 of the first controller 41, and is received by the first sixth input end 131 and the fourth sixth input end 131 of the signal amplification sub-module 13; the first driving signal E2 is output through the second third output end 413 of the first controller 41, and is received by the second sixth input end 131 and the fifth sixth input end 131 of the signal amplification sub-module 13; the first driving signal E3 is output through the third third output end 413 of the first controller 41, and is received by the third sixth input end 131 and the sixth sixth input end 131 of the signal amplification sub-module 13.

[0063] The second driving signal F1 is input to the first third input end 503 of the first scanning head 50 through the first sixth output end 132 of the signal amplification sub-module 13, the second driving signal F2 is input to the second third input end 503 of the first scanning head 50 through the second sixth output end 132 of the signal amplification sub-module 13, and the second driving signal F3 is input to the third third input end 503 of the first scanning head 50 through the third sixth output end 132 of the signal amplification sub-module 13; the second driving signal F1 is input to the first third input end 503 of the second scanning head 50 through the fourth sixth output end 132 of the signal amplification sub-module 13, the second driving signal F2 is input to the second third input end 503 of the second scanning head 50 through the fifth sixth output end 132 of the signal amplification sub-module 13, and the second driving signal F3 is input to the third third input end 503 of the second scanning head 50 through the sixth sixth output end 132 of the signal amplification sub-module 13.

[0064] The second driving signal F1 is used for driving the red light emitting diode to emit light, the second driving signal F2 is used for driving the green light emitting diode to emit light, and the second driving signal F3 is used for driving the blue light emitting diode to emit light.

[0065] In the embodiment of the utility model, in the case that the light source device 51 receives the second clock signal, the first row trigger signal and the first driving signal group, the light emitting diode in the light source device 51 emits light.

[0066] Optionally, in some embodiments, the analog-to-digital conversion module 20 is an analog front end (AFE) device; and the output module 30 is a latch.

[0067] In the embodiment of the utility model, since the analog-to-digital conversion module 20 is an analog front end device, it can convert the image analog signal into an image digital signal; and since the output module 30 is a latch, it can combine each image digital signal into a total image digital signal for output.

[0068] The embodiment of the utility model provides a kind of mainboard, including as described above image scanning circuit.

[0069] The implementation mode of image scanning circuit in mainboard is similar to the implementation mode of the aforementioned image scanning circuit, which will not be repeated here.

[0070] The embodiment of the utility model provides a kind of electronic equipment, including as described above image scanning circuit, or as described above mainboard.

[0071] The implementation mode of image scanning circuit in electronic equipment is similar to the implementation mode of the aforementioned image scanning circuit, which will not be repeated here.

[0072] It should be noted that electronic equipment includes scanner, copy, printer and other scanning equipment, for example, electronic equipment is high-speed double-sided scanner or printer with double-sided copy scanning.

[0073] In the related art, a set of controllers for driving scanning heads is added in the system-on-chip to realize driving of two scanning heads by the system-on-chip, but the system-on-chip with a set of controllers for driving scanning heads has high cost and high power consumption, and when the system-on-chip with a set of controllers for driving scanning heads is applied in a single-sided scanning scenario, the resources of the set of controllers for driving scanning heads in the system-on-chip are wasted.

[0074] In the embodiment of the utility model, the first signal set output by the first controller 41 in the system-on-chip 40 is converted into a plurality of second signal sets by the preprocessing module 10, to drive the corresponding scanning head 50 by the second signal set, then the image analog signal output by the corresponding scanning head 50 of the analog-to-digital conversion module 20 is converted into an image digital signal by the analog-to-digital conversion module 20, and each image digital signal is combined into a total image digital signal by the output module 30, to be forwarded to the processor 43 in the system-on-chip 40 by the second controller 42 for processing, so as to obtain each image data, to realize driving of the plurality of scanning heads 50 by the system-on-chip 40, to realize driving of the plurality of scanning heads 50 by the system-on-chip 40, which reduces cost and power consumption compared with the related art; in addition, the image scanning circuit provided in the embodiment of the utility model can be applied in a double-sided copy or double-sided scanning scenario, and avoids scanning data deviation and disorder; through the embodiment of the utility model, the system-on-chip 40 can be flexibly compatible with single-sided scanning or double-sided scanning scenarios, and the resource waste of the set of controllers for driving scanning heads in the system-on-chip when the system-on-chip with a set of controllers for driving scanning heads is applied in a single-sided scanning scenario is avoided, so that the scanning quality of the electronic equipment and the compatibility of the mainboard of the electronic equipment can be improved through the embodiment of the utility model.

[0075] In summary, in this embodiment of the present invention, the preprocessing module 10 converts the first signal set output by the first controller 41 in the system-on-a-chip 40 into multiple second signal sets, thereby driving the scanning head 50 corresponding to the second signal set to work. Then, the analog-to-digital conversion module 20 converts the image analog signal output by the scanning head 50 corresponding to the analog-to-digital conversion module 20 into an image digital signal. Finally, the output module 30 combines each image digital signal into a total image digital signal, which is then forwarded by the second controller 42 to the processor 43 in the system-on-a-chip 40 for processing, thereby acquiring each image data. This enables the system-on-a-chip 40 to drive multiple scanning heads 50, improving the adaptability of the system-on-a-chip 40 to multi-scanning-head-50 driving scenarios.

[0076] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device.

[0077] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

[0078] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. An image scanning circuit, characterized by comprising: The application relates to a system for scanning and processing images, which comprises a preprocessing module (10), a plurality of analog-digital conversion modules (20), an output module (30), a system-level chip (40) and a plurality of scanning heads (50). The preprocessing module (10) is electrically connected with a first controller (41) in the system-level chip (40) and the plurality of scanning heads (50) respectively, converts a first signal set output by the first controller (41) into a plurality of second signal sets, and the second signal sets correspond to the scanning heads (50) one by one; the second signal sets are used for driving the scanning heads (50) corresponding to the second signal sets to work; The analog-digital conversion module (20) corresponds to the scanning head (50) one by one, the analog-digital conversion module (20) is electrically connected with the scanning head (50) corresponding to the analog-digital conversion module (20), converts an image analog signal output by the scanning head (50) corresponding to the analog-digital conversion module (20) into an image digital signal; the image analog signal is an analog signal of image data collected by the scanning head (50); The output module (30) is electrically connected with each analog-digital conversion module (20), the output module (30) is electrically connected with a second controller (42) in the system-level chip (40), combines each image digital signal into a total image digital signal, so that the second controller (42) transmits the total image digital signal to a processor (43) in the system-level chip (40) for processing, thereby obtaining each image data. The preprocessing module (10) comprises a first clock buffer (11), a second clock buffer (12) and a signal amplification sub-module (13); the first signal set comprises a first clock signal, a first row trigger signal and a first driving signal group; the second signal set comprises a second clock signal, a second row trigger signal and a second driving signal group; 2. The image scanning circuit of claim 1, wherein, The first clock buffer (11) is electrically connected with the first controller (41) and each scanning head (50) respectively, and copies the first clock signal into a plurality of second clock signals; The second clock buffer (12) is electrically connected with the first controller (41) and each scanning head (50) respectively, and copies the first row trigger signal into a plurality of second row trigger signals; The signal amplification sub-module (13) is electrically connected with the first controller (41) and each scanning head (50) respectively, copies and signal-amplifies the first driving signal group to generate a plurality of second driving signal groups. The first controller (41) comprises a first output end (411), a second output end (412) and n third output ends (413); the number of the scanning heads (50) is m, each scanning head (50) comprises a first input end (501), a second input end (502) and n third input ends (503); n and m are positive integers greater than 1.

3. The image scanning circuit of claim 2, wherein, ​ The preprocessing module (10) comprises a first clock buffer (11), a second clock buffer (12) and a signal amplification sub-module (13); the first clock buffer (11) comprises a fourth input end (111) and m fourth output ends (112); the second clock buffer (12) comprises a fifth input end (121) and m fifth output ends (122); the signal amplification sub-module (13) comprises u sixth input ends (131) and u sixth output ends (132); the fourth output end (112) corresponds to the first input end (501) one by one; the fifth output end (122) corresponds to the second input end (502) one by one; the third output end (413) has corresponding m sixth input ends (131); the third input end (503) has a corresponding sixth output end (132); u is the product of n and m; The fourth input end (111) is electrically connected with the first output end (411), and the fourth output end (112) is electrically connected with the first input end (501) corresponding to the fourth output end (112); the fifth input end (121) is electrically connected with the second output end (412), and the fifth output end (122) is electrically connected with the second input end (502) corresponding to the fifth output end (122); the third output end (413) is electrically connected with each sixth input end (131) corresponding to the third output end (413), and the third input end (503) is electrically connected with the sixth output end (132) corresponding to the third input end (503).

4. The image scanning circuit of claim 2, wherein, The signal amplification sub-module (13) is a Darlington tube chip.

5. The image scanning circuit according to any one of claims 1 to 4, characterized by, The number of the scanning heads (50) is m, and each scanning head (50) comprises v seventh output ends (504); the analog-digital conversion module (20) comprises v seventh input ends (201) and w eighth output ends (202); the output module (30) comprises r eighth input ends (301) and r ninth output ends (302); the second controller (42) comprises r ninth input ends (421); m, v and w are all positive integers greater than 1, and r is the product of w and m; The seventh output end (504) corresponds to the seventh input end (201) one by one; the eighth output end (202) corresponds to the eighth input end (301) one by one; the ninth output end (302) corresponds to the ninth input end (421) one by one; The seventh input end (201) is electrically connected with the seventh output end (504) corresponding to the seventh input end (201); the eighth output end (202) is electrically connected with the eighth input end (301) corresponding to the eighth output end (202); The ninth output end (302) is electrically connected with the ninth input end (421) corresponding to the ninth output end (302).

6. The image scanning circuit according to any one of claims 1 to 4, characterized by, Each scanning head (50) comprises a light source device (51) and an image sensor (52); The preprocessing module (10) is electrically connected with each of the light source device (51) and each of the image sensor (52); In the scanning head (50), the image sensor (52) is electrically connected with the analog-digital conversion module (20) corresponding to the scanning head (50).

7. The image scanning circuit of claim 6, wherein, The light source device (51) comprises a plurality of light emitting diodes. The preprocessing module (10) is electrically connected with each of the light emitting diodes.

8. The image scanning circuit according to any one of claims 1 to 4, characterized by, The analog-digital conversion module (20) is an analog front end device; and the output module (30) is a latch.

9. A main board, characterized by, An image scanning circuit comprising any one of the image scanning circuits of claims 1 to 8.

10. An electronic device, comprising: An image scanning circuit comprising any one of the image scanning circuits of claims 1 to 8, or a main board of claim 9.

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