Dynamic testing device of power semiconductor device
By employing a four-terminal output interface and transistor switching circuit design in the semiconductor power device testing device, and fixing the current probe, the problem of inaccurate testing caused by frequent disassembly and reassembly of the current probe is solved, achieving stable acquisition of current data and efficient testing, and adapting to various testing scenarios.
Patent Information
- Application Number
- CN202423238080.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2034-12-26
AI Technical Summary
In current dynamic testing of semiconductor power devices, frequent disassembly and reassembly of current probes lead to inaccurate and unstable test data, affecting the accuracy and stability of parameters such as current and di/dt acquisition, failing to meet mass production requirements and shortening service life.
The design adopts a four-terminal output interface, with the current probe fixedly installed on the output interface of the energy storage unit. A dynamic test circuit is formed by the parallel P and N buses and P_L and N_L buses. The on and off of the test circuit is controlled by a transistor switching circuit to achieve accurate acquisition of the current waveform and avoid frequent disassembly and assembly.
It improves the accuracy and stability of current data acquisition, adapts to routine switch parameter testing and short-circuit testing under extreme conditions, enhances the flexibility and efficiency of the equipment, and reduces signal interference and noise.
Smart Images
Figure CN223711763U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor device testing, in particular to a dynamic testing device for power semiconductor devices. BACKGROUND
[0002] Semiconductor power devices are core components of applications such as new energy, rail transportation, electric vehicles, industrial applications, and household appliances. With the trend of localization of semiconductor power devices and the increase in demand from downstream application fields, China's semiconductor power device industry has enormous development opportunities, especially in the development of new energy (automobiles, photovoltaics, industrial control), new materials, biology, high-end equipment manufacturing, smart grids, rail transportation, wind power, and new-generation information technology, all of which rely on the support of semiconductor power devices.
[0003] While the semiconductor power device industry is rapidly advancing, the semiconductor testing industry has also developed rapidly. Electrical parameter testing is required from the design, research and development, and production stages of semiconductor power devices to the later use stage. In particular, the dynamic parameters of semiconductor power devices reflect the switching performance of the devices, so the accuracy of dynamic parameter testing is particularly important. With the rapid development of third-generation semiconductor-based semiconductor power devices, the precision requirements for switching parameter testing are becoming increasingly high, which puts strict requirements on the accurate use of current probes and differential probes and other testing equipment.
[0004] In different dynamic testing methods, the use methods of current probes and differential probes and other testing equipment are different. For example Figure 1 In the circuit shown in the figure, the current probe is installed on the device end of the DUT (Device Under Test, measured device) board to observe the current. During the replacement of the measured device or the DUT board, the current probe also needs to be disassembled and assembled, which can cause poor consistency of the installation position, seriously affecting the accuracy and stability of current, di / dt, and other parameter data collection. This method is not suitable for mass production requirements of semiconductor power devices, and also has a certain impact on the service life of the current probe. Invention content
[0005] Therefore, the main purpose of the present application is to provide a dynamic testing device for power semiconductor devices, which optimizes the design of the circuit to realize the use of the distal end of the current probe, avoids the problem of inaccurate and unstable test data caused by frequent disassembly and assembly of the current probe, and ensures the accuracy and stability of the test.
[0006] In the first aspect, the present application provides a dynamic testing device for power semiconductor devices, comprising a power supply, an energy storage unit, a measured device unit, and a current collection unit.
[0007] The output interface of the power supply is connected to the charging interface of the energy storage unit, and the output interface of the energy storage unit includes a first positive output end and a second positive output end, a first negative output end and a second negative output end in parallel;
[0008] The measured device unit includes a first measured device and a second measured device, which are connected in series between the first positive output end and the first negative output end. The connection points of the first measured device and the second measured device pass through a load device, and are respectively connected to the second positive output end and the second negative output end of the energy storage unit through the first switch and the second switch, to form a dynamic test loop.
[0009] The current acquisition unit acquires the current waveform of the first positive output end of the energy storage unit through the first current probe, and acquires the current waveform of the first negative output end of the energy storage unit through the second current probe.
[0010] From the above, the dynamic test device for power semiconductor devices provided by the application includes a four-terminal output interface arranged in the energy storage unit, and the measured devices in the measured device unit are connected to the four-terminal output interface to form a dynamic test loop. Two current probes are respectively connected to the positive and negative output ends of the four-terminal output interface, to realize the acquisition of the current waveforms on the two test loops. During dynamic testing, the switches on the test loops can be controlled to switch different test loops, thereby realizing the dynamic testing of each measured device. The current probe is fixedly installed on the output interface of the energy storage unit, which avoids the problem of unstable test data caused by replacing the measured device, ensures the accuracy and stability of current data acquisition, and the test device can adapt to various application scenarios such as conventional switch parameter testing and short circuit testing under extreme conditions, without the need for additional hardware adjustment, thereby improving the flexibility and use efficiency of the equipment.
[0011] Optionally, the energy storage unit includes a capacitor module and a switch module.
[0012] The output interface of the power supply is connected to the charging interface of the capacitor module, and the capacitor module is charged through the charging interface.
[0013] The switch module is connected to the output interface of the capacitor module, and is used to control the on-off of the test loop of the capacitor module and the measured device unit after the capacitor module is fully charged.
[0014] From the above, the energy storage unit is formed by the capacitor module and the switch module, the capacitor module can be charged by the power supply, which ensures that the device under test is provided with continuous and stable current during the test process, and the switch module serves as a bridge between the capacitor module and the device under test unit, which can accurately trigger the discharging process after the capacitor module is fully charged, thereby ensuring the controllability and repeatability of the current waveform.
[0015] Optionally, the output interface of the energy storage unit is connected to the device under test unit by an output busbar, the first positive output end and the second positive output end are arranged on one side of the output busbar, and the first negative output end and the second negative output end are arranged on the other side of the output busbar.
[0016] From the above, the busbar is usually made of a large cross-sectional area of conductive metal, which has low resistance and good conductivity. The output busbar is used as the connection mode between the energy storage unit and the device under test unit, which enhances the current carrying capacity and connection reliability of the system, and by arranging the first positive output end and the second positive output end, the first negative output end and the second negative output end on both sides of the output busbar, it helps to reduce the parasitic inductance and capacitance in the loop, thereby reducing signal interference and noise and improving test accuracy.
[0017] Optionally, the output width occupied by the first positive output end on one side of the output busbar is greater than the output width occupied by the second positive output end on one side of the output busbar.
[0018] The output width occupied by the first negative output end on the other side of the output busbar is greater than the output width occupied by the second negative output end on the other side of the output busbar.
[0019] From the above, since the short-circuit test current value of the power semiconductor device is usually 3-5 times the switch test current value, the first positive output end and the first negative output end occupy a larger output width to carry higher current, while the second positive output end and the second negative output end occupy a smaller output width to be suitable for regular switch parameter testing, which meets the requirements of high-current short-circuit testing and also takes into account the needs of regular switch parameter testing.
[0020] Optionally, the current acquisition unit includes an oscilloscope, the oscilloscope is connected to the first positive output end in a bridge-in manner through the first current probe, and the oscilloscope is connected to the first negative output end in a bridge-in manner through the second current probe.
[0021] From the above, by fixing the current probe in a low-inductance bridge-in manner at a specific position of the output busbar and sending the acquired current waveform to the oscilloscope for display, the physical operation of the current probe is reduced, the frequent disassembly of the current probe is avoided, and the high precision and stability of the current data acquisition are ensured.
[0022] Optionally, the switch module comprises one or multiple parallel transistor switch circuits, and the on-off of the test loop between the capacitor module and the device under test is controlled by driving the on-off of the one or multiple parallel transistor switch circuits.
[0023] According to the above, by arranging transistor switch circuits on the switch module, the switching characteristics of transistors (such as IGBT or MOSFET) are utilized to quickly respond to the change of the driving signal, to ensure the instant on-off of the test loop between the capacitor module and the device under test, and the multiple parallel transistor switch circuits have the effects of strong current-carrying capacity and small parasitic inductance.
[0024] Optionally, the first switch and the second switch are arranged on the two sides of the output busbar respectively, and the on-off of the loop between the second positive output end and the load device is controlled by the first switch, and the on-off of the loop between the second negative output end and the load device is controlled by the second switch.
[0025] According to the above, by arranging the switches on the two sides of the output busbar, the control part of the dynamic test loop is arranged on the power supply side, which facilitates wiring and easy control, and avoids the influence of the test parameters caused by the accidental touch when operating the device under test.
[0026] Optionally, the first device under test and the second device under test comprise IGBT or MOSFET.
[0027] Optionally, the load device comprises a load inductor or a load resistor.
[0028] According to the above, the load device can be a load inductor or a load resistor, when the load device is a load inductor and the test loop is switched from the on state to the off state, the load device can release the stored energy through the freewheeling loop, so as to facilitate the current probe to collect the freewheeling current waveform in the freewheeling loop.
[0029] These and other aspects of the application will become more fully understood from the following description of (several) embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0030] Figure 1 A circuit diagram of a test circuit;
[0031] Figure 2 A module diagram of a dynamic test device for a power semiconductor device according to an embodiment of the application;
[0032] Figure 3 A circuit diagram of a first dynamic test device for a power semiconductor device according to an embodiment of the application;
[0033] Figure 4A first P bus current probe mounting structure schematic diagram provided by the embodiment of the application is shown in the figure;
[0034] Figure 5 A first N bus current probe mounting structure schematic diagram provided by the embodiment of the application is shown in the figure;
[0035] Figure 6 A first power semiconductor device dynamic testing device mounting structure schematic diagram provided by the embodiment of the application is shown in the figure;
[0036] Figure 7 A first dynamic testing mode circuit diagram provided by the embodiment of the application is shown in the figure;
[0037] Figure 8 A second dynamic testing mode circuit diagram provided by the embodiment of the application is shown in the figure;
[0038] Figure 9 A second power semiconductor device dynamic testing device circuit diagram provided by the embodiment of the application is shown in the figure;
[0039] Figure 10 A second P bus current probe mounting structure schematic diagram provided by the embodiment of the application is shown in the figure;
[0040] Figure 11 A second N bus current probe mounting structure schematic diagram provided by the embodiment of the application is shown in the figure;
[0041] Figure 12 A second power semiconductor device dynamic testing device mounting structure schematic diagram provided by the embodiment of the application is shown in the figure. DETAILED DESCRIPTION
[0042] In order to make the purpose, technical scheme and advantages of the application more clear, the application will be further described in detail below with reference to the drawings.
[0043] The embodiment of the application provides a power semiconductor device dynamic testing device, through the optimized design of the circuit, the distal end use of the current probe is realized, the problems of inaccurate and unstable test data caused by the frequent disassembly of the current probe are avoided, and the accuracy and stability of the dynamic testing are ensured.
[0044] As shown in the figure, Figure 2 The embodiment of the application provides a power semiconductor device dynamic testing device, as shown in the figure, Figure 2 The testing device includes a power supply 100, an energy storage unit 200, a device to be tested unit 300 and a current collection unit 400;
[0045] The power supply 100 can be a high-voltage source, and can be implemented by a program-controlled high-voltage power supply, for example. The output interface of the power supply 100 is connected to the charging interface of the energy storage unit 200. The energy storage unit 200 is composed of a capacitor plate (the above-mentioned capacitor module) and a switch plate (the above-mentioned switch module). The capacitor plate is charged by the power supply 100, and the on-off of the test loop of the capacitor plate is controlled by the switch plate. The output interface of the energy storage unit 200 includes the P bus (the above-mentioned first positive output end) and the P_L bus (the above-mentioned second positive output end), the N bus (the above-mentioned first negative output end) and the N_L bus (the above-mentioned second negative output end) in parallel. The device under test unit 300 includes the device under test DUT1 (the above-mentioned first device under test) and the device under test DUT2 (the above-mentioned second device under test). The device under test DUT1 and the device under test DUT2 are connected in series between the P bus and the N bus of the energy storage unit 200. One end of the device under test DUT1 and the device under test DUT2 is connected to one end of the load inductor L1. The other end of the load inductor L1 is connected to the P_L bus and the N_L bus of the energy storage unit 200 through the switch K1 (the above-mentioned first switch) and the switch K2 (the above-mentioned second switch) respectively, so as to form a dynamic test loop. The current acquisition unit 400 can be an oscilloscope. The oscilloscope acquires the current waveform of the P bus of the energy storage unit 200 through the P bus current probe (the above-mentioned first current probe), and acquires the current waveform of the N bus of the energy storage unit 200 through the N bus current probe (the above-mentioned second current probe).
[0046] The embodiment of the present application sets the four-terminal output interface in parallel in the energy storage unit 200, and connects the device under test and the related load inductor in the device under test unit 300 to the four-terminal output interface, so as to form a dynamic test loop. The P bus and the N bus of the four-terminal output interface are connected to the two current probes of the current acquisition unit 400, so as to acquire the current waveforms on the two test loops. During dynamic testing, the switch K1 or K2 on the test loop can be controlled to switch different test loops, so as to realize dynamic testing of each device under test. The current probe is fixedly installed on the output interface of the energy storage unit, so as to avoid the problem of unstable test data caused by replacement of the DUT board or the device under test, and to ensure the accuracy and stability of current data acquisition. The test device of the present application can adapt to various application scenarios such as conventional switch parameter testing and short-circuit testing under extreme conditions, without additional hardware adjustment, and improves the flexibility and use efficiency of the equipment.
[0047] The following refers to Figures 3-12 The circuit structure and working principle of the dynamic test device for the power semiconductor device provided by the embodiment of the present application are described in detail.
[0048] Figure 3 Figure 1 is a circuit diagram of a dynamic testing device for a first power semiconductor device according to an embodiment of the present application. Figure 3 As shown, the dynamic testing device comprises a programmable high-voltage power supply 1, a capacitor plate 2, a switch plate 3, a DUT plate 4, an oscilloscope 5, a P bus current probe 6, and an N bus current probe 7.
[0049] The input interface of the programmable high-voltage power supply 1 is powered by mains electricity, and the output interface thereof is connected to the charging interface of the capacitor plate 2, allowing a user to set a specific charging voltage and current limit, and to control the programmable high-voltage power supply 1 to charge the capacitor C1 on the capacitor plate 2 in a constant-current limited-voltage mode. As an energy storage unit, the capacitor plate 2 will provide a continuous and stable current for the device under test during the dynamic testing process. The switch plate 3 is arranged on the capacitor plate 2 by plugging, and the switch plate 3 is provided with one or multiple transistor switch circuits T1 in parallel. By applying a driving signal to the one or multiple transistor switch circuits, the switching characteristics of the transistor (such as IGBT or MOSFET) can be utilized to quickly respond to changes in the driving signal, thereby ensuring the instant on-off of the test loop between the capacitor plate 2 and the DUT plate 4. Moreover, the parallel multiple transistor switch circuits T1 also have the effect of strong current-carrying capacity and small parasitic inductance.
[0050] In this embodiment, the capacitor board 2 provides a four-terminal output interface for the DUT board 4, which includes a positive output P bus, a P_L bus, a negative output N bus, and a N_L bus. The P_L bus and the N_L bus are current paths for switch parameter testing, and the P bus and the N bus are current paths for both switch parameter testing and short-circuit current testing. The DUT board 4 includes a series connection of a DUT1 and a DUT2. The input terminal of the DUT1 (the collector of an IGBT or the drain of a MOSFET) is connected to the P bus of the capacitor board 2, the output terminal of the DUT1 (the emitter of an IGBT or the source of a MOSFET) is connected to the input terminal of the DUT2 (the collector of an IGBT or the drain of a MOSFET), the output terminal of the DUT2 (the emitter of an IGBT or the source of a MOSFET) is connected to the N bus of the capacitor board 2, and the output terminal of the DUT1 (the emitter of an IGBT or the source of a MOSFET) and the input terminal of the DUT2 (the collector of an IGBT or the drain of a MOSFET) are connected to one end of a load inductor L1. The other end of the load inductor L1 is connected to the P_L bus of the capacitor board 2 through a switch K1 and to the N_L bus of the capacitor board 2 through a switch K2, thereby forming a dynamic test loop. One end of the P bus current probe 6 is connected to the P bus of the capacitor board 2, and the other end of the P bus current probe 6 is connected to a current acquisition port I1 of the oscilloscope 5, so as to acquire the current waveform of the P bus during dynamic testing. One end of the N bus current probe 7 is connected to the N bus of the capacitor board 2, and the other end of the N bus current probe 7 is connected to a current acquisition port I2 of the oscilloscope 5, so as to acquire the current waveform of the N bus during dynamic testing.
[0051] In this embodiment, the switches K1 and K2 can be relay switches or IGBTs, and the DUT1 and the DUT2 can be IGBTs or MOSFETs. In the dynamic testing process of this example, different test loops can be switched to achieve dynamic testing of the DUT1 and the DUT2, respectively. For example, when the DUT1 is the device under test, the DUT2 is the companion device. Similarly, when the DUT2 is the device under test, the DUT1 is the companion device. During dynamic testing, a certain pulse width double-pulse signal can be applied to the control terminal (e.g., the gate of an IGBT or a MOSFET) of the device under test through a drive circuit, and a turn-off signal can be applied to the control terminal of the companion device, so as to ensure that the device under test and the companion device can be turned on and turned off according to the preset time, thereby meeting the switching requirements of dynamic testing.
[0052] In some embodiments, the four-terminal output interface of the capacitor board 2 can be connected to the DUT board 4 in a plug-in manner using an output busbar. Figure 4As shown, the P bus and P_L bus are arranged on one side of the output busbar. The P bus serves as the current path for short-circuit current testing and switching parameter testing, while the P_L bus serves as the current path for switching parameter testing. Since the short-circuit test current value is typically 3-5 times the switching test current value, to ensure current carrying capacity, in this embodiment, the output width 'a' of the P bus on this side of the output busbar can be designed to be 3-5 times the output width 'b' of the P_L bus on this side of the output busbar, in order to carry higher current. Similarly, as... Figure 5 As shown, the N bus and the N_L bus are arranged on the other side of the output busbar. The N bus serves as the current path for short-circuit current testing and switching parameter testing, and the N_L bus serves as the current path for switching parameter testing. Since the short-circuit test current value is usually 3-5 times the switching test current value, in order to ensure current carrying capacity, in this embodiment, when designing the output busbar, the output width 'a' of the N bus on this side of the output busbar can be designed to be 3-5 times the output width 'b' of the N_L bus on this side of the output busbar, so as to carry higher current.
[0053] In some embodiments, based on the above Figures 4-5 In the design of the output busbar, the P bus current probe 6 can be connected to the P busbar on one side of the output busbar by bridging, and the N bus current probe 7 can be connected to the N busbar on the other side of the output busbar by bridging. By bridging the current probes, the PCB copper pours of the P busbar and the N busbar are stacked, thereby reducing the parasitic inductance in the test loop.
[0054] based on Figures 3-5 The provided circuit and hardware structures Figure 6 The diagram shown is a schematic representation of the installation structure of a dynamic testing device for a first type of power semiconductor device provided in this application embodiment. Figure 6 As shown, the testing device includes a programmable high-voltage power supply 1, a capacitor board 2, a switch board 3, a DUT board 4, an oscilloscope 5, a P bus current probe 6, and an N bus current probe 7.
[0055] The input interface of the program-controlled high-voltage power supply 1 is powered by commercial power, and the output interface is connected to the charging interface of the capacitor plate 2 through a charging cable to realize charging and discharging on the capacitor plate 2. The switch plate 3 is arranged on the capacitor plate 2 in a plug-in manner to control the on-off of the test loop of the capacitor plate 2. The capacitor plate 2 is connected to the DUT plate 4 in a plug-in manner through an output busbar, and the output busbar is designed in a four-terminal interface, including a P busbar and a P_L busbar arranged on one side of the output busbar and an N busbar and an N_L busbar arranged on the other side of the output busbar. The P_L busbar and the N_L busbar are current paths for switch parameter testing, and the P busbar and the N busbar are not only current paths for switch parameter testing but also current paths for short circuit testing. One end of the P busbar current probe 6 is connected to the P busbar on one side of the output busbar of the capacitor plate 2 in a bridging manner to collect the current waveform of the P busbar during dynamic testing and send the current waveform to the oscilloscope 5 through the other end. One end of the N busbar current probe 7 is connected to the N busbar on the other side of the output busbar of the capacitor plate 2 in a bridging manner to collect the current waveform of the N busbar during dynamic testing and send the current waveform to the oscilloscope 5 through the other end.
[0056] Reference will be made to Figures 7-8 The working principle of the dynamic testing device for the power semiconductor device provided in the embodiment of the application is explained in detail. Specifically, the embodiment introduces switch parameter testing.
[0057] As Figure 7As shown, when the switch parameter test of the measured device DUT1 is implemented, the output bus of the capacitor plate 2 is plugged with the socket of the DUT plate 4, at the same time, the switch K2 is closed and the switch K1 is opened, the program-controlled high-voltage power supply 1 charges the capacitor C1 of the capacitor plate 2 in the constant current and voltage limiting mode, when the capacitor C1 is fully charged, a driving signal is applied to the transistor switch T1 on the switch plate 3 to close the transistor switch T1 on the switch plate 3, at this time, the capacitor plate 2 and the DUT plate 4 form a test loop, a double pulse signal is applied to the gate of the measured device DUT1 on the DUT plate 4, at the same time, a turn-off signal is applied to the gate of the auxiliary measured device DUT2 on the DUT plate 4, in the state that the DUT2 keeps off, the DUT1 completes two times of turn-on and turn-off. During the turn-on of the DUT1, the capacitor C1 of the capacitor plate 2 outputs current to the DUT1 through the P bus on the output bus, after passing through the DUT1, the load inductor L1 and the switch K2, the current returns to the N_L bus of the output bus, when the DUT1 switches from the turn-on state to the turn-off state, the load inductor L1, the switch K2, the N_L bus, the N bus and the reverse parallel diode of the DUT2 form a freewheeling circuit to release the energy stored in the load inductor L1. The P bus current probe 6 is connected to the P bus of the capacitor plate 2, the N bus current probe 7 is connected to the N bus of the capacitor plate 2, the P bus current probe 6 collects the current waveform flowing through the DUT1 during the turn-on and turn-off of the DUT1 and sends it to the oscilloscope 5 to obtain the current data of the DUT1 during the turn-on and turn-off, the N bus current probe 7 collects the freewheeling current waveform flowing through the reverse parallel diode of the DUT2 during the turn-on and turn-off of the DUT1 and sends it to the oscilloscope 5 to obtain the reverse recovery current data of the reverse parallel diode of the DUT2.
[0058] When the above switch parameter test of the DUT1 is completed, another driving signal is applied to the transistor switch T1 on the switch plate 3 to open the transistor switch T1 on the switch plate 3, at this time, the loop formed by the capacitor plate 2 and the DUT plate 4 is disconnected, the program-controlled high-voltage power supply 1 discharges the capacitor C1 on the capacitor plate 2 to make the voltage reach a predetermined value, thereby completing the switch parameter test process.
[0059] As shown in the figure, Figure 8As shown, when the switch parameter test of the measured device DUT2 is implemented, the output bus of the capacitor board 2 is connected with the socket of the DUT board 4, and at the same time, the switch K1 is closed and the switch K2 is opened, the program-controlled high-voltage power supply 1 charges the capacitor C1 of the capacitor board 2 in the constant current and limited voltage mode, and when the capacitor C1 is fully charged, a driving signal is applied to the transistor switch T1 on the switch board 3 to close the transistor switch T1 on the switch board 3, at this time, the capacitor board 2 and the DUT board 4 form a test loop, a double pulse signal is applied to the gate of the measured device DUT2 on the DUT board 4, and at the same time, a turn-off signal is applied to the gate of the auxiliary measured device DUT1 on the DUT board 4, so that the DUT2 completes two times of turn-on and turn-off in the state that the DUT1 remains turned off. During the turn-on of the DUT2, the current output by the capacitor C1 on the capacitor board 2 passes through the P_L bus, the switch K1 and the load inductor L1 to reach the input end (the collector of the IGBT or the drain of the MOSFET) of the DUT2, and then passes through the output end (the emitter of the IGBT or the source of the MOSFET) of the DUT2 to return to the N bus of the output bus, when the DUT2 switches from the turn-on state to the turn-off state, the load inductor L1, the switch K1, the P_L bus, the P bus and the reverse parallel diode of the DUT1 form a freewheeling loop to release the energy stored in the load inductor L1. The P bus current probe 6 is connected with the P bus of the capacitor board 2, the N bus current probe 7 is connected with the N bus of the capacitor board 2, the N bus current probe 7 collects the current waveform flowing through the DUT2 during the turn-on and turn-off of the DUT2 and sends it to the oscilloscope 5 to obtain the current data of the DUT2 during the turn-on and turn-off, and the P bus current probe 6 collects the freewheeling current waveform flowing through the reverse parallel diode of the DUT1 during the turn-on and turn-off of the DUT2 and sends it to the oscilloscope 5 to obtain the reverse recovery current data of the reverse parallel diode of the DUT1.
[0060] When the above switch parameter test of the DUT2 is completed, another driving signal is applied to the transistor switch T1 on the switch board 3 to open the transistor switch T1 on the switch board 3, at this time, the test loop formed by the capacitor board 2 and the DUT board 4 is disconnected, the program-controlled high-voltage power supply 1 is controlled to discharge the capacitor C1 on the capacitor board 2, and the voltage reaches a predetermined value, thereby completing the switch parameter test process.
[0061] The above switches K1 and K2 in the embodiment can be arranged in the circuit of the DUT board 4, and when dynamic test is needed, the on-off of the switches K1 and K2 on the DUT board 4 is controlled to realize the switching of the dynamic test loop. The switches K1 and K2 can also be arranged on the capacitor board 2, and the switches K1 and K2 on the capacitor board 2 are controlled to realize the switching of the dynamic test loop. Figure 9 and Figure 10 As shown, the switch K1 can be arranged on the P_L bus of the output bus of the capacitor board 2. Similarly, referring to Figure 9 and Figure 11As shown, the switch K2 can be arranged on the N_L bus side of the output busbar of the capacitor plate 2. By arranging the switch plate 3, the switches K1 and K2 on the capacitor plate 2, only the switch control on the capacitor plate 2 is needed during the dynamic test, and the on-off of the dynamic test loop can be realized without operation on the DUT plate 4.
[0062] Based on Figures 9-11 The circuit structure and hardware structure provided, Figure 12 As shown in the installation structure schematic diagram of the dynamic test device of the second power semiconductor device provided by the embodiment of the application, as shown in the installation structure schematic diagram of the dynamic test device of the power semiconductor device provided by the embodiment of the application, Figure 12 As shown, the test device includes a programmable high-voltage power supply 1, a capacitor plate 2, a switch plate 3, a DUT plate 4, an oscilloscope 5, a P bus current probe 6 and an N bus current probe 7.
[0063] The input interface of the programmable high-voltage power supply 1 is powered by the mains, and the output interface is connected to the charging interface of the capacitor plate 2 through a charging cable to charge the capacitor on the capacitor plate 2. The switch plate 3 is arranged on the capacitor plate 2 in a plug-in manner to control the on-off of the test loop of the capacitor plate 2. The capacitor plate 2 is connected to the DUT plate 4 in a plug-in manner through an output busbar, and the output busbar is designed with a four-terminal interface, including a P bus arranged on one side of the output busbar, a P_L bus and an N bus arranged on the other side of the output busbar, and an N_L bus. The P_L bus and the N_L bus are current paths for switch parameter testing, and the P bus and the N bus are not only current paths for switch parameter testing, but also current paths for short circuit testing. The switch K1 is arranged on the P_L bus on one side of the output busbar of the capacitor plate 2 to control the on-off of the P_L bus and the load inductance on the DUT plate 4. The switch K2 is arranged on the N_L bus on one side of the output busbar of the capacitor plate 2 to control the on-off of the N_L bus and the load inductance on the DUT plate 4. One end of the P bus current probe 6 is connected to the P bus on one side of the output busbar of the capacitor plate 2 in a bridging manner to collect the current waveform of the P bus during dynamic testing, and the other end is sent to the oscilloscope 5. One end of the N bus current probe 7 is connected to the N bus on the other side of the output busbar of the capacitor plate 2 in a bridging manner to collect the current waveform of the N bus during dynamic testing, and the other end is sent to the oscilloscope 5.
[0064] Figures 9-12 The working principle of the dynamic test device of the power semiconductor device in the embodiment shown can refer to the working principle of the dynamic test device of the power semiconductor device provided by the embodiment of the application Figures 7-8 As shown, the working principle of the dynamic test device of the power semiconductor device in the embodiment shown can refer to the working principle of the dynamic test device of the power semiconductor device provided by the embodiment of the application
[0065] In summary, the embodiment of the present application aims at the problem of poor accuracy and stability of switch parameter acquisition caused by frequent disassembly and assembly of the current probe in the current near-end use mode of the current probe in the dynamic test of some semiconductor power devices at present, and proposes a dynamic test device for power semiconductor devices, adopts a four-terminal output interface mode, that is, P_L and N_L buses are added on the basis of original P and N buses, and then a low-stray inductance mounting mode is adopted to fix and mount the current probe on the P and N buses to collect the current waveform, which reduces the stray inductance of the test loop, avoids disassembly and assembly of the current probe, ensures the accuracy and stability of current data collection, and makes the dynamic test device provided by the embodiment of the present application be able to adapt to various application scenarios such as conventional switch parameter test and short-circuit test under extreme conditions, without additional hardware adjustment, and improve the flexibility and use efficiency of the equipment.
[0066] It should be noted that the embodiments described in the present application are only part of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the above detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0067] The words "first", "second", "third" and the like similar terms of description used in the specification and claims are only used to distinguish similar objects, and do not represent a specific order or sequence of the objects. It is understood that the specific order or sequence can be interchanged, if permitted, to enable the embodiments of the present application described herein to be implemented in an order other than that illustrated or described herein.
[0068] In the above description, the signs representing the steps involved do not necessarily mean that the steps are executed in this order, and can include intermediate steps or be replaced by other steps, and the order of the steps can be interchanged, or the steps can be executed simultaneously, if permitted.
[0069] The term "comprising" used in the specification and claims should not be interpreted as being limited to the listed elements; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof. Therefore, the expression "a device comprising means A and B" should not be limited to a device consisting only of components A and B.
[0070] The term "one embodiment" or "an embodiment" as may appear in the specification is intended to mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, but can refer to different embodiments. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner on the basis of one or more technological principles.
[0071] It should be noted that the above-mentioned preferred embodiments and technical principles of the application are only intended to explain the application and are not intended to limit the application. Those skilled in the art should understand that the application is not limited to the specific embodiments described herein, and various obvious changes, modifications and substitutions can be made by those skilled in the art without departing from the scope of the application. Therefore, although the application has been described in detail in the above embodiments, the application is not limited to the above embodiments, and more other equivalent embodiments can be included without departing from the concept of the application, and all fall within the scope of the application.
Claims
1. A dynamic testing device for power semiconductor devices, characterized in that, Includes power supply, energy storage unit, device under test unit, and current acquisition unit; The output interface of the power supply is connected to the charging interface of the energy storage unit. The output interface of the energy storage unit includes a first positive output terminal and a second positive output terminal, a first negative output terminal and a second negative output terminal connected in parallel. The device under test unit includes a first device under test and a second device under test. The first device under test and the second device under test are connected in series between the first positive output terminal and the first negative output terminal. The connection point of the first device under test and the second device under test passes through a load device and is respectively connected to the second positive output terminal and the second negative output terminal of the energy storage unit through the first switch and the second switch to form a dynamic test circuit. The current acquisition unit acquires the current waveform at the first positive output terminal of the energy storage unit through a first current probe, and acquires the current waveform at the first negative output terminal of the energy storage unit through a second current probe.
2. The apparatus according to claim 1, characterized in that, The energy storage unit includes a capacitor module and a switch module; The power supply's output interface is connected to the capacitor module's charging interface, and the capacitor module is charged through this charging interface. The switch module is connected to the output interface of the capacitor module and is used to control the connection and disconnection of the test circuit between the capacitor module and the device under test unit after the capacitor module is fully charged.
3. The apparatus according to claim 1, characterized in that, The output interface of the energy storage unit is connected to the device under test unit via an output busbar. The first positive output terminal and the second positive output terminal are arranged on one side of the output busbar, and the first negative output terminal and the second negative output terminal are arranged on the other side of the output busbar.
4. The apparatus according to claim 3, characterized in that, The output width occupied by the first positive output terminal on the output busbar side is greater than the output width occupied by the second positive output terminal on the output busbar side. The output width occupied by the first negative output terminal on the other side of the output busbar is greater than the output width occupied by the second negative output terminal on the other side of the output busbar.
5. The apparatus according to claim 1 or 3, characterized in that, The current acquisition unit includes an oscilloscope, which is connected to the first positive output terminal via the first current probe in a bridging manner, and the oscilloscope is connected to the first negative output terminal via the second current probe in a bridging manner.
6. The apparatus according to claim 2, characterized in that, The switching module includes one or more parallel transistor switching circuits. By driving the one or more transistor switching circuits to turn on or off, the connection and disconnection of the test circuit between the capacitor module and the device under test unit are controlled.
7. The apparatus according to claim 3, characterized in that, The first switch and the second switch are respectively arranged on both sides of the output busbar. The first switch controls the connection and disconnection of the circuit between the second positive output terminal and the load device, and the second switch controls the connection and disconnection of the circuit between the second negative output terminal and the load device.
8. The apparatus according to claim 1, characterized in that, The first and second devices under test include IGBTs or MOSFETs.
9. The apparatus according to claim 1, characterized in that, The load device includes a load inductor or a load resistor.