PCIE quantum chip password card

Abstract

The utility model discloses a PCIE (Peripheral Component Interface Express) quantum chip password card which comprises a quantum random number generation module, a control module, a processing module and a PCIE interface, the quantum random number generation module is connected with the control module, the output end of the control module is connected with the input end of the processing module, the processing module is connected with the PCIE interface, and the PCIE interface is used for being connected with external equipment. The utility model discloses a PCIE (Peripheral Component Interface Express) quantum chip password card, which is characterized in that a quantum random number generation module can quickly generate a large number of quantum random numbers, the randomness is better, a secret key is generated by utilizing the quantum random numbers generated by the quantum random number generation module, the secret key can be prevented from being cracked, and the data security is effectively improved; and the generation of the quantum random number is completed in the whole system, so that the risk of electromagnetic leakage is effectively avoided, and the method is widely applied to the fields of commercial passwords and the like.

Description

TECHNICAL FIELD

[0001] The utility model relates to quantum random number and password chip field, concretely relates to a PCIE quantum chip password card. BACKGROUND

[0002] The high -speed development of global information technology and quantum computation, the requirement of information security is higher and higher, and information encryption is the key among them.

[0003] Quantum random number generator (Quantum Random Number Generator, QRNG) is a kind of device using quantum mechanics principle to generate true random number, is the only true random number generator in theory so far, is the key technology of commercial password and quantum key distribution system (Quantum Key Distribion, QKD).

[0004] The existing password card generates key by random number generated by classical physical random number generator.The random signal source of classical physical random number generator comes from deterministic classical physical process, but because its physical system is complex system, so it is difficult to predict the random number generated.But from the theoretical point of view, when all initial conditions are known, it is still predictable, therefore, it is possible to be cracked under quantum computing, and it is difficult to guarantee the security of data.

[0005] Moreover, the speed of the random number generated by the existing password card using classical physical random number generator is relatively low, and it is also susceptible to external environmental interference, which cannot meet the high-speed application scenarios. UTILITY MODEL CONTENTS

[0006] The utility model discloses in order to solve the problem that the existing password card generates key by random number generated by classical physical random number generator, and the security of data is difficult to guarantee, proposes a PCIE quantum chip password card.

[0007] In order to achieve the above-mentioned purpose, the technical scheme adopted by the utility model is as follows:

[0008] A PCIE quantum chip password card, comprising a quantum random number generation module, a control module, a processing module and a PCIE interface;

[0009] The quantum random number generation module is connected with the control module, the output end of the control module is connected with the input end of the processing module, the processing module is connected with the PCIE interface, and the PCIE interface is used to connect external equipment.

[0010] In the scheme, the quantum random number generation module can quickly generate a large number of quantum random numbers, and the randomness is good, the key is generated by using the quantum random numbers generated by the quantum random number generation module, the data security is improved effectively, and the risk of electromagnetic leakage is avoided effectively.

[0011] Preferably, the quantum random number generation module is provided with two quantum random number generator chips.

[0012] Preferably, the system further comprises a storage module, and the storage module is connected with the processing module.

[0013] Preferably, the system further comprises a first crystal oscillator clock module, and an output end of the first crystal oscillator clock module is connected with an input end of the processing module.

[0014] Preferably, the system further comprises a second crystal oscillator clock module, and an output end of the second crystal oscillator clock module is connected with an input end of the control module.

[0015] Preferably, the system further comprises a USB interface, and the USB interface is connected with the processing module.

[0016] Preferably, the system further comprises a serial port interface, and the serial port interface is connected with the processing module.

[0017] Preferably, the control module is a CPLD control module.

[0018] In the scheme, the quantum random number is optimized by the CPLD control module, and the stability and practicability of the system are improved.

[0019] Preferably, the processing module is a security password chip.

[0020] Preferably, the PCIE interface is a PCIE2.0 X4 interface.

[0021] The application has the beneficial technical effects that:

[0022] The PCIE quantum chip password card provided by the application can quickly generate a large number of quantum random numbers, and the randomness is good, the key is generated by using the quantum random numbers generated by the quantum random number generation module, the data security is improved effectively, and the risk of electromagnetic leakage is avoided effectively. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The application is a whole structure block diagram;

[0024] Wherein: 1, quantum random number generation module; 11, quantum random number generator chip; 2, control module; 3, processing module; 4, PCIE interface; 5, storage module; 6, first crystal oscillator clock module; 7, second crystal oscillator clock module; 8, USB interface; 9, serial interface. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the utility model more clearly, the following will be further detailed with examples, but the scope of protection of the utility model is not limited to the following specific examples.

[0026] Example 1

[0027] As Figure 1 shown, a PCIE quantum chip password card, including quantum random number generation module 1, control module 2, processing module 3 and PCIE interface 4;

[0028] The quantum random number generation module 1 is connected with the control module 2, the output end of the control module 2 is connected with the input end of the processing module 3, the processing module 3 is connected with the PCIE interface 4, and the PCIE interface 4 is used to connect external equipment.

[0029] In the specific implementation process, the quantum random number generation module 1 can quickly generate a large number of quantum random numbers, and the randomness is better, the key is generated by using the quantum random number generated by the quantum random number generation module 1, which can prevent being cracked, effectively improve the security of data, and the generation of quantum random number is completed in the whole system, effectively avoiding the risk of electromagnetic leakage.

[0030] Example 2

[0031] A PCIE quantum chip password card, including quantum random number generation module 1, control module 2, processing module 3 and PCIE interface 4;

[0032] The quantum random number generation module 1 is connected with the control module 2, the output end of the control module 2 is connected with the input end of the processing module 3, the processing module 3 is connected with the PCIE interface 4, and the PCIE interface 4 is used to connect external equipment.

[0033] More specifically, the quantum random number generation module 1 is provided with two quantum random number generator chips 11.

[0034] In the implementation process, the two quantum random number generator chips 11 generate quantum random numbers at the same rate as the clock signal according to the clock signal and control signal given by the control module 2. The control module 2 detects the randomness of the quantum random numbers generated by the quantum random number generator chips 11, and the detected quantum random numbers are converted into level signals suitable for the processing module 3 and then output to the processing module 3. Since the generation process of quantum random numbers is completely unpredictable in theory, using quantum random numbers to process data information can improve the reliability and security of data processing.

[0035] More specifically, it also includes a storage module 5; the storage module 5 is connected with the processing module 3.

[0036] In the implementation process, the storage module 5 is used to store the quantum random numbers generated by the quantum random number generator chips 11, and also to realize the storage of data information, control information and processing results. The storage module 5 is composed of memory and flash memory. Among them, the memory in the storage module 5 adopts 8M high-speed static random memory composed of 16-bit 512k words, which is manufactured by ISSI high-performance CMOS technology. This highly reliable process combined with innovative circuit design technology can produce high-performance, low-power devices. The flash memory in the storage module 5 adopts 128Mb parallel interface NorFlash, which is used to store quantum random numbers, interactive data and program codes, etc.

[0037] More specifically, it also includes a first crystal oscillator clock module 6; the output end of the first crystal oscillator clock module 6 is connected with the input end of the processing module 3.

[0038] In the implementation process, the first crystal oscillator clock module 6 provides the clock signal required for normal operation of the processing module 3.

[0039] More specifically, it also includes a second crystal oscillator clock module 7; the output end of the second crystal oscillator clock module 7 is connected with the input end of the control module 2.

[0040] In the implementation process, the second crystal oscillator clock module 7 is used as a backup clock for the control module 2.

[0041] More specifically, it also includes a USB interface 8; the USB interface 8 is connected with the processing module 3.

[0042] In the implementation process, the USB interface 8 and the external equipment can be used for data interaction. The USB interface 8 has the advantages of plug and play, supporting hot plug, fast transmission speed, etc.

[0043] The security password chip in the embodiment supports USB_HOST and USB_OTG. Among them, the TYPE C interface in the USB interface 8 can be selected. Since the TYPE C interface is designed symmetrically, the user does not need to distinguish the interface direction when docking the equipment, and can be connected at will, which is more convenient in operation. Among them, B-5Pin, B-4Pin or Micro USB and other USB interfaces 8 can also be selected.

[0044] More specifically, it also includes a serial port interface 9; the serial port interface 9 is connected with the processing module 3.

[0045] In the specific implementation process, the program burning and the host computer control of the processing module 3 are performed through the serial port interface 9.

[0046] More specifically, the control module 2 is a CPLD control module.

[0047] In the specific implementation process, the quantum random number is optimized by the CPLD control module, which increases the stability and practicability of the system.

[0048] More specifically, the processing module 3 is a security password chip.

[0049] In the specific implementation process, the external equipment transmits data to the security password chip through the PCIE interface 4, the security password chip processes the data to be processed transmitted through the PCIE interface 4, and then outputs the processing result through the PCIE interface 4. Among them, the security password chip supports national standard algorithms including SM1\SM2\SM3\SM4\SM6, and international general algorithms including DES\AES\RSA\SHA1\SHA256\SH384\SHA512; therefore, the security password chip can select a plurality of different existing algorithms to process the data to be processed, and the processing mode is various, including encryption, decryption, hash, signature, signature verification, etc.

[0050] More specifically, the PCIE interface 4 is a PCIE2.0 X4 interface.

[0051] In the specific implementation process, PCIE is a high-speed serial computer expansion bus standard. Its classification can be divided into X1, X2, X4, X8, X16 (maximum support 32 channels) according to the number of channels, and gen1, gen2, gen3, gen4, gen5 (namely 1.0, 2.0, 3.0, 4.0, 5.0) according to the generation. PCIE2.0 X4 represents the second generation of PCIE with 4 channels.

[0052] According to the disclosure and teaching of the above description, the skilled in the art of the utility model can also change and modify the above-mentioned embodiments. Therefore, the utility model is not limited to the specific embodiments disclosed and described above, and some modifications and changes of the utility model should fall within the protection scope of the claims of the utility model. In addition, although some specific terms are used in the specification, these terms are only for convenience and do not constitute any limitation on the utility model.

Claims

1. A PCIe quantum chip cryptographic card, characterized in that, It includes a quantum random number generation module, a control module, a processing module, and a PCIe interface; The quantum random number generation module is connected to the control module, the output of the control module is connected to the input of the processing module, and the processing module is connected to the PCIe interface, which is used to connect external devices.

2. The PCIe quantum chip cryptographic card according to claim 1, characterized in that, The quantum random number generation module is equipped with two quantum random number generator chips.

3. A PCIe quantum chip cryptographic card according to claim 1, characterized in that, It also includes a storage module; the storage module is connected to the processing module.

4. A PCIe quantum chip cryptographic card according to claim 1, characterized in that, It also includes a first crystal clock module; the output of the first crystal clock module is connected to the input of the processing module.

5. A PCIe quantum chip cryptographic card according to claim 1, characterized in that, It also includes a second crystal clock module; the output of the second crystal clock module is connected to the input of the control module.

6. A PCIe quantum chip cryptographic card according to claim 1, characterized in that, It also includes a USB interface; the USB interface is connected to the processing module.

7. A PCIe quantum chip cryptographic card according to claim 1, characterized in that, It also includes a serial port interface; the serial port interface is connected to the processing module.

8. A PCIE quantum chip cryptographic card according to claim 5, characterized in that, The control module is a CPLD control module.

9. A PCIE quantum chip cryptographic card according to claim 4, characterized in that, The processing module is a secure cryptographic chip.

10. A PCIe quantum chip cryptographic card according to claim 1, characterized in that, The PCIe interface is a PCIe 2.0 x4 interface.

Images