Memory and electronic equipment
By using three-dimensional stacked packaging and a distributed memory architecture, the problem that traditional memory chips cannot meet the needs of modern computing is solved, and efficient parallel operation of memory groups and improved resource utilization are achieved.
Patent Information
- Application Number
- CN202520176105.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-27
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2035-01-27
AI Technical Summary
The traditional operating mode of memory chips cannot meet the ever-increasing computing demands and data volume of modern computing systems, resulting in storage bandwidth bottlenecks and resource waste, which limits system performance and efficiency.
By employing a three-dimensional stacked packaging process, memory chips and logic chips are connected through hybrid bonding and TSV technology to realize a distributed memory architecture, increasing the number of interfaces between memory groups and logic chips, and controlling the operation of each memory group through an independent memory group controller.
It improves memory resource utilization and data bandwidth, alleviates memory wall bottlenecks, supports simultaneous access from multiple memory groups, and enhances computing efficiency.
Smart Images
Figure CN223712430U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip technology, specifically to a memory and electronic device. Background Technology
[0002] like Figure 1 As shown, traditional memory chips typically contain one or more memory banks, each containing one or more memory blocks. These memory blocks communicate with the outside world through a standard interface conforming to a specific memory protocol. External control commands and data transfers are all conducted through the signal lines of this interface. In this memory architecture, when a memory bank or memory block occupies the interface, the other memory banks or memory blocks cannot interact with the outside world. Furthermore, since externally input addresses usually point to specific memory locations, which correspond to the storage circuitry of a specific memory block within a memory bank, each operation is executed only by the memory block pointed to by the address, while other memory blocks in that memory bank and other memory banks do not participate in the operation. This centralized operating mode has gradually evolved with the iteration of memory chips and has become a relatively common memory operating mode.
[0003] However, in recent years, the computational demands and data volumes of computing systems have continued to grow, while the bandwidth provided by storage devices has failed to keep pace. This has led to the traditional operating modes of memory chips gradually becoming inadequate for the needs of modern computing systems. This mismatch exacerbates the "memory wall" problem faced by computing systems, limiting their overall performance and efficiency. Therefore, there is an urgent need to explore new storage architectures and operating modes to cope with the ever-increasing demands for computation and data transfer.
[0004] To alleviate storage bandwidth bottlenecks, there are generally two solutions available. The first solution is to increase the number of storage devices operating in parallel, thereby increasing bandwidth by increasing the number of data channels. Figure 2 However, as computing power increases, the area occupied by computing circuits gradually increases, and adding more storage devices also requires more area resources. Furthermore, the controllers that control these storage devices further consume valuable area space, and the increased data paths also increase system complexity. Ultimately, the overall performance improvement of the system using this approach is limited, and as area resources are gradually depleted, system optimization and development face even greater bottlenecks.
[0005] The second approach is to use high-performance storage devices, such as high-bandwidth memory (HBM), to increase bandwidth by increasing the density of individual memory units and the number of interface signals. Figure 3This approach alleviates the bandwidth bottleneck and area issues of the aforementioned solutions to some extent. However, high-bandwidth memories such as HBM still require a single interface to connect to CPU / GPU / NPU circuits, thus their operating mode is similar to the traditional centralized operating mode. Specifically, external devices can only communicate by accessing a memory block or multiple memory blocks with the same address through this memory interface and addressing them based on the input address. Therefore, although this approach increases the number of memory blocks that can perform operations simultaneously, only a portion of the memory blocks pointed to by the external address perform operations, while other memory blocks do not participate. This still results in a waste of storage resources and limits further improvements in memory performance.
[0006] Therefore, it is necessary to improve the existing memory. Utility Model Content
[0007] To address the above problems, this utility model provides a memory, including a memory chip and a logic chip. The memory chip and the logic chip are packaged using a three-dimensional stacked packaging process. The memory chip includes multiple memory groups and an interface corresponding to each memory group. Each memory group interacts with the logic chip through an independent interface.
[0008] Optionally, the memory further includes a memory group controller, which corresponds one-to-one with the memory group and is capable of controlling the corresponding memory group in response to control instructions from the logic chip.
[0009] Optionally, the memory group controller is disposed on the memory chip, and the memory group controller is connected between the corresponding memory group and the interface.
[0010] Optionally, the memory group controller is disposed on the logic chip, and the memory group controller is connected to the corresponding memory group through the corresponding interface.
[0011] Optionally, different memory group controllers are configured to control the corresponding memory groups to execute completely different, partially the same, or completely the same operating instructions at the same time.
[0012] Optionally, along the direction of the three-dimensional stacking of the logic chip and the memory chip, corresponding to the position of the first interface, the logic chip is provided with a second interface, and the first interface and the second interface are connected along the direction of the three-dimensional stacking of the logic chip and the memory chip using a hybrid bonding process and / or a TSV process.
[0013] Optionally, the memory chip is a Flash memory chip, a DRAM memory chip, an SRAM memory chip, an MRAM chip, or an RRAM memory chip.
[0014] Optionally, the logic chip includes an arithmetic logic circuit, which is capable of performing calculation operations such as multiplication and addition.
[0015] Optionally, the three-dimensional stacked packaging process is: Hybrid bonding technology and / or TSV technology.
[0016] To achieve the aforementioned utility model objective, this application provides a method for controlling a memory, wherein the controller includes a logic chip and a memory chip, and the memory chip includes multiple memory groups, comprising the following steps:
[0017] Receive external operation commands;
[0018] The logic chip sends control commands to control each memory group of the memory chip based on external operation instructions; and
[0019] Each memory group interacts with the logic chip in response to the corresponding control command.
[0020] Optionally, the memory control method further includes the step of: different memory groups performing completely different, partially the same, or completely the same operations in response to corresponding control instructions.
[0021] In order to achieve the above-mentioned utility model objectives, this application provides an electronic device that uses the memory described above.
[0022] The memory provided in this application, when external operation instructions are input into the memory, converts these external operation instructions into control instructions for each memory group controller via a logic chip, and sends them to the corresponding memory groups. Therefore, taking a read operation as an example, a memory in a traditional architecture can only read data from a memory block in a specific memory group each time through a single interface based on address information. However, the memory provided in this embodiment, due to its distributed architecture, can support simultaneous access to different memory groups within the memory via multiple interfaces.
[0023] By employing advanced packaging methods and a distributed architecture design, the number of I / O interfaces for external communication of the memory chip has been increased, fundamentally changing the access mode of the memory to its internal memory groups and memory blocks. This transforms the original centralized working mode into a distributed working mode, thereby supporting memory groups and memory blocks to perform related operations at the same time, improving the resource utilization of the memory, providing greater data bandwidth for efficient computing, and effectively alleviating the "memory wall" bottleneck faced by the memory. Attached Figure Description
[0024] Figure 1 It is the architecture of memory in existing technology.
[0025] Figure 2 It is an improved memory architecture in the existing technology.
[0026] Figure 3 It is an improved memory architecture in the existing technology.
[0027] Figure 4 This is a schematic diagram of the memory architecture provided in an embodiment of this utility model.
[0028] Figure 5 This is a schematic diagram of the memory architecture provided in an embodiment of this utility model.
[0029] Figure 6 This is a schematic diagram of the steps of the memory control method provided in the embodiments of this utility model. Detailed Implementation
[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.
[0031] like Figure 4 As shown, this embodiment provides a memory, including a memory chip 100 and a logic chip 200. The memory chip 100 and the logic chip 200 are packaged using a three-dimensional stacked packaging process. The memory chip 100 includes multiple memory groups 110 and multiple first interfaces 120 corresponding to the memory groups 110. Each memory 110 interacts with the logic chip 200 through an independent first interface 120.
[0032] Specifically, the memory also includes a memory group controller 210 located in the logic chip 200 at a position corresponding to the memory group 110, and each memory group 110 can interact with the logic chip 200 through the memory group controller 210 via its independently configured first interface 120. Based on this, the logic chip 200 can control multiple memory groups 110 in the memory chip 100 to perform operations simultaneously, significantly improving the resource utilization of the memory chip 100 and providing higher data bandwidth for the logic chip 200.
[0033] Furthermore, the logic chip 200 is provided with a second interface 220 corresponding to the first interface 120. Taking the logic chip 200 and the memory chip 100 stacked in the vertical direction as an example, the position of the first interface 120 corresponds to the memory group 110 in the horizontal direction, and the position of the second interface 220 corresponds to the position of the first interface 120 in the horizontal direction. In other words, the first interface 120 and the second interface 220 are correspondingly set along the stacking direction of the logic chip 200 and the memory chip 100.
[0034] In this embodiment, the logic chip 200 and memory chip 100 are packaged using a three-dimensional stacking process, specifically Hybrid bonding technology or TSV technology. More specifically, the first interface 120 and the second interface 220 are connected along the stacking direction of the logic chip 200 and memory chip 100 using Hybrid bonding and / or TSV technology. Hybrid bonding is a direct bonding technology that directly bonds wafers or chips using chemical-mechanical methods, typically used in 3D integration. It achieves high-density connections through metal-to-metal and dielectric-to-dielectric bonding. Its advantages include ultra-high interconnect density: Hybrid bonding supports nanometer-level metal interconnect spacing (hundreds of nanometers to several micrometers), enabling extremely high signal transmission density to further reduce chip area, making it particularly suitable for high-density 3D integration. Due to the short interconnect channels and low signal loss, Hybrid bonding reduces parasitic resistance and capacitance, thereby significantly reducing power consumption. It is very suitable for low-power chips (such as mobile devices, AI accelerators, etc.). Performance improvement: Provides faster data transmission speeds and lower latency. Meets the requirements of high-performance computing (HPC), especially for the integration of high-bandwidth memory, processors, and accelerators. Greater design flexibility: Supports chip-level or wafer-level stacking without requiring additional silicon area, allowing for complex heterogeneous integration (such as the combination of logic and memory, analog and digital circuits). Cost optimization: Hybrid bonding integrates through wafer-level processes, reducing process steps and material waste, resulting in a cost advantage. TSV is a vertical interconnect technology using through-silicon vias (TSVs). It achieves electrical connections between chips by fabricating vias on a silicon wafer and filling them with conductive material. TSV is a three-dimensional interconnect technology that enables chip stacking (such as HBM high-bandwidth memory stacking for DRAM), supporting direct interconnection of multiple chip layers and increasing integration density. TSV provides high-bandwidth inter-chip communication paths, especially in applications requiring high data throughput (such as graphics processors and AI accelerators). Reduced signal transmission latency and improved operating speed. Compared to traditional packaging (such as Flip-Chip or WireBonding), TSV significantly shortens the signal transmission path, thereby reducing power consumption. TSV technology allows for the stacking of chips of different process nodes and types (such as logic, memory, and analog chips), making it suitable for heterogeneous computing platforms. After years of development, TSV technology has matured and has been successfully applied in many commercial products (such as HBM2 memory and 3D NAND).
[0035] The memory provided in this embodiment uses a three-dimensional stacked package for its memory chip 100 and logic chip 200, and specifically implements the three-dimensional stacked package using the two processes described above. The two can be used together or separately according to specific needs. For example, TSV can be used for global interconnection in three-dimensional integrated design, and Hybrid Bonding can be used to achieve local high-density interconnection, thereby giving full play to their respective advantages.
[0036] It should be noted that the memory chip 100 can be configured such that some memory groups 110 have independent interfaces, while the remaining memory groups 110 interact with the logic chip 200 through a shared interface; or it can be configured such that all memory groups 110 have independent interfaces and interact with the logic chip 200 through independent interfaces. All of the above embodiments are within the protection scope of this utility model.
[0037] Optionally, in this embodiment, the memory chip 100 and the logic chip 200 are electrically connected in the vertical direction through hybrid bonding technology.
[0038] Optionally, in this embodiment, the memory chip 100 and the logic chip 200 are electrically connected in the vertical direction through TSV technology.
[0039] By implementing the electrical connection between the memory chip 100 and the logic chip 200 using the two electrical connection methods described above, the area occupied by the electrical interface on the chip can be significantly reduced, thus providing a basis for each memory group 110 to independently set up a first interface 120 for interaction with the logic chip 200.
[0040] like Figure 5 As shown, this embodiment also provides a memory, which is connected to... Figure 4 The difference in the memory shown is that the memory group controller 130 is disposed on the memory chip 100. In this case, the memory group controller 130 is connected between the corresponding memory group 110 and the corresponding first interface 120.
[0041] If the memory group controller 130 is located on the memory chip 100, since it is on the same chip as the memory group 110, the two are more tightly coupled, the stability is stronger, and it is less likely to have problems such as signal distortion. If the memory group controller 130 is located on the logic chip 200, since the process of the logic chip 200 is more advanced than that of the memory chip 100, the performance of the memory group controller 130 will be better when it is located on the logic chip 200.
[0042] In the actual design process, based on the spirit of this utility model, those skilled in the art may need to weigh the stability and controller performance based on indicators such as process and interface signal frequency, and select a memory group controller design scheme that is more suitable for the current application scenario. All the above embodiments are within the protection scope of this application.
[0043] Regardless of the specific location of the memory group controller 130, its horizontal position corresponds to the corresponding memory group 110. This design can reduce the difficulty and cost of wiring.
[0044] by Figure 4 Taking the illustrated memory as an example, when external operation instructions are input into the memory, the memory converts these external operation instructions into control instructions for each memory group controller 210 via the logic chip 200, and sends them to the corresponding memory groups respectively. Therefore, taking a read operation as an example, a memory in a traditional architecture can only read data from a memory block in a specific memory group each time through a single interface based on address information. However, the memory provided in this embodiment, due to its distributed architecture, can support simultaneous access to different memory groups within the memory via multiple interfaces.
[0045] By employing advanced packaging methods and a distributed architecture design, the number of interfaces for external communication of the memory chip has been increased, fundamentally changing the access mode of the memory to its internal memory groups and memory blocks. This transforms the original centralized working mode into a distributed working mode, thereby supporting memory groups and memory blocks to perform related operations at the same time, improving the resource utilization of the memory, providing greater data bandwidth for efficient computing, and effectively alleviating the "memory wall" bottleneck faced by the memory.
[0046] Optionally, each memory group 110 includes at least one memory block, and different memory blocks are configured to have different address information. Based on this, in response to the address information in the control instruction, the memory block corresponding to the address information executes the control instruction.
[0047] Optionally, different memory group controllers 130 are configured to control corresponding memory groups to execute completely different, partially the same, or completely the same operating instructions at the same time.
[0048] Optionally, such as Figure 6 As shown, this embodiment provides a method for controlling a memory, which includes the following steps:
[0049] Receive external operation commands;
[0050] The logic chip sends control commands to control each memory group of the memory chip based on external operation instructions; and
[0051] Each memory bank interacts with the logic chip in response to the corresponding control commands.
[0052] Optionally, the control method includes the steps of:
[0053] Different memory banks respond to corresponding control instructions by performing completely different, partially the same, or completely the same operations.
[0054] With this configuration, the memory control method provided in this embodiment is more flexible than that in the prior art. It can make different memory groups execute different control instructions according to the needs, thereby improving the utilization rate of memory, data interaction efficiency and the diversity of working modes.
[0055] Optionally, in this embodiment, the logic chip 200 further includes a functional circuit 230, which includes an arithmetic logic circuit that performs calculation operations such as multiplication and addition.
[0056] Optionally, in this embodiment, the memory chip 100 also includes a functional circuit 140, which is responsible for multiple operations such as address resolution, error correction, and power management. The coordinated work between these circuits ensures that the memory chip can operate in an efficient, stable and reliable manner.
[0057] Optionally, in this embodiment, the memory chip 100 is a Flash memory chip, a DRAM memory chip, an SRAM memory chip, an MRAM chip, or an RRAM memory chip.
[0058] Optionally, the first interface 120 of the memory bank 110 is configured to receive any combination of the following signals: address input signal, data input / output signal, word or byte select input signal, hardware reset / sector protection unlock signal, output enable signal, command lane signal, address lane signal, Ready / Busy indicator signal, differential clock signal, clock enable signal, chip select signal, row address strobe signal, column address strobe signal, write enable signal, data read / write clock signal, BANK address signal, data mask signal, termination resistor signal, calibration signal, command address signal, and data bus signal.
[0059] Optionally, when the memory has multiple stacked memory chips, the upper-layer memory chips and the lower-layer memory chips are connected via I / O through an advanced package interface and are jointly controlled by a memory group controller on the logic chip. For example, when a memory group controller on the logic chip is working, it can simultaneously access the memory groups on these memory chips corresponding to that memory group controller.
[0060] Optionally, this embodiment also provides an electronic device that uses the memory provided in this embodiment; the electronic device may be a computer.
[0061] The technical solution of this utility model has now been described in conjunction with the accompanying drawings. However, it will be readily understood by those skilled in the art that the protection scope of this utility model is obviously not limited to the specific embodiments described above. Without departing from the principles of this utility model, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions resulting from these changes or substitutions will all fall within the protection scope of this utility model.
Claims
1. A memory, characterized in that, The device includes a memory chip and a logic chip. The memory chip and the logic chip are packaged using a three-dimensional stacked packaging process. The memory chip includes multiple memory groups and a first interface corresponding to at least a portion of the memory groups. The at least a portion of the memory groups interact with the logic chip through an independent first interface.
2. The memory according to claim 1, characterized in that, The memory also includes a memory group controller, which corresponds one-to-one with the at least some memory groups and is capable of controlling the corresponding memory group in response to control instructions from the logic chip.
3. The memory according to claim 2, characterized in that, The memory group controller is disposed on the memory chip and is connected between the corresponding at least part of the memory group and the first interface.
4. The memory according to claim 2, characterized in that, The memory group controller is located on the logic chip, and the memory group controller is connected to the corresponding memory group through the corresponding first interface.
5. The memory according to claim 2, characterized in that, Along the direction of the three-dimensional stacking of the logic chip and the memory chip, corresponding to the position of the first interface, the logic chip is provided with a second interface, and the first interface and the second interface are connected along the direction of the three-dimensional stacking of the logic chip and the memory chip using a hybrid bonding process and / or a TSV process.
6. The memory according to any one of claims 2-5, characterized in that, Different memory group controllers are configured to control the corresponding memory groups to execute completely different, partially the same, or completely the same operating instructions at the same time.
7. The memory according to any one of claims 1-5, characterized in that, The memory chip is a Flash memory chip, a DRAM memory chip, an SRAM memory chip, an MRAM chip, or an RRAM memory chip.
8. The memory according to any one of claims 1-5, characterized in that, The logic chip includes an arithmetic logic circuit, which is capable of performing computational operations.
9. The memory according to any one of claims 1-5, characterized in that, The process of the three-dimensional stacked packaging is: Hybrid bonding technology or TSV technology.
10. An electronic device, characterized in that, The memory described in any one of claims 1-9 is used.