NAND flash memory remapping method and apparatus based on access frequency

Abstract

The present invention provides a NAND flash memory remapping device and a NAND flash memory remapping method that maximize the utilization of internal memory bandwidth, reduce power consumption, and shorten processing delay time. [Solution] An access frequency-based NAND flash memory remapping device 100 according to one embodiment of the present invention includes: a data access frequency analysis unit that analyzes the access frequency to a memory area in which at least one target piece of information is stored; a data remapping unit that constructs a page containing the target information based on the analyzed access frequency; and a page buffer that stores the constructed page and loads it when an access request is made.

Description

Technical Field

[0001] The present invention relates to a NAND flash memory remapping method based on access frequency and an apparatus for assisting the same.

Background Art

[0002] In a personalized recommendation system that increasingly needs to process a large amount of user data in real time, generally, due to rare data access patterns, inefficient data access patterns occur in the memory system, and the performance of the entire system deteriorates.

[0003] In a conventional system based on DRAM or NAND flash memory, due to the bottleneck that occurs when data moves from the memory to the processor, there is a limit to efficiently processing irregular data access patterns. Also, in a recommendation system, only a very small part of the embedded vectors loaded in the page buffer is used, and most are not used, resulting in problems such as inefficient use of the hardware resources of the data center due to waste of the internal memory bandwidth, an increase in power consumption, and an increase in the system processing delay time.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention is for solving the above problems, and in order to maximize the utilization of the internal memory bandwidth, reduce power consumption, and shorten the processing delay time, data is intensively arranged in a specific page of the NAND flash according to the access frequency, enabling efficient use of the memory. A data remapping technology, and a page unit cache that supports high-speed access to frequently accessed data are used to maximize the utilization of the internal memory bandwidth, improve the efficiency of data processing, reduce power consumption, and reduce energy consumption. An object of the present invention is to provide a NAND flash memory remapping method based on access frequency and an apparatus for assisting the same.

[0005] The object of the present invention is not limited to the object mentioned above, and other object not mentioned above can be easily understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] An access frequency-based NAND flash memory remapping device according to one embodiment of the present invention for achieving the above technical problems includes: a data access frequency analysis unit that analyzes the access frequency to a memory area in which at least one target piece of information is stored; a data remapping unit that constructs a page containing the target information based on the analyzed access frequency; and a page buffer that stores the constructed page and loads it when an access request is made.

[0007] Furthermore, pages can be configured to allow access to target information through a single-page reading operation using a selective reading method.

[0008] Furthermore, the data access frequency analysis unit can analyze the access frequency to memory areas based on a hash table.

[0009] Furthermore, the data access frequency analysis unit can rearrange the target information based on the access frequency and then redistribute it to pages in the memory area that are allocated based on the balanced distribution between the memory planes.

[0010] Furthermore, the access frequency-based NAND flash memory remapping device according to one embodiment of the present invention may further include a page cache that stores target information rearranged based on an LRU policy and performs page-level caching.

[0011] Furthermore, the access frequency-based NAND flash memory remapping device according to one embodiment of the present invention may further include a data processing unit that performs embedding vector calculations based on target information loaded into the page buffer.

[0012] Furthermore, the data remapping unit sorts the target information according to a rank corresponding to the access frequency, clusters information belonging to the same access rank category onto a single page, and the same access rank category can be set by a predefined threshold for access frequency.

[0013] An access frequency-based NAND flash memory remapping method according to one embodiment of the present invention for achieving the above technical problems includes the steps of: analyzing the access frequency to a memory area in the NAND flash memory where at least one target information is stored; configuring a page containing the target information based on the access frequency to the analyzed memory area; and loading the configured page containing the target information into the page buffer of the plane in which the target information is stored.

[0014] Furthermore, the step of configuring a page containing the target information based on the access frequency to the analyzed memory area may include the step of arranging the target information in consecutive address regions within the same page so that the target information can be accessed by single-page read operations only, according to the selective read scheme.

[0015] Furthermore, in the step of analyzing the access frequency to a memory area in NAND flash memory where at least one piece of target information is stored, the number of accesses for each item in the memory area can be analyzed based on a hash table, and the determined access frequency can be analyzed.

[0016] Furthermore, the access frequency-based NAND flash memory remapping method according to one embodiment of the present invention may further include the step of rearranging target information on pages of a plane allocated based on a balanced arrangement between planes of the memory area, based on the access frequency.

[0017] Furthermore, the access frequency-based NAND flash memory remapping method according to one embodiment of the present invention may further include a step of storing the target information rearranged according to the LRU policy and performing page-level caching in order to access the target information with the highest priority based on the access frequency to the analyzed memory area.

[0018] Furthermore, the access frequency-based NAND flash memory remapping method according to one embodiment of the present invention may further include a step of performing calculations on an embedding vector based on target information loaded into a page buffer.

[0019] Furthermore, the step of constructing a page containing target information based on the access frequency to the analyzed memory area includes the steps of arranging the target information according to the rank corresponding to the access frequency, and clustering information belonging to the same access rank category into a single page, where the same access rank category can be set by a predefined threshold for access frequency. [Effects of the Invention]

[0020] According to the present invention, by using data remapping technology that concentrates data on specific target pages of NAND flash according to access frequency, enabling efficient use of memory, and a page-level cache that supports high-speed access to frequently accessed data, it is possible to maximize the utilization of internal memory bandwidth, improve the efficiency of data processing, reduce power consumption, and lower energy consumption.

[0021] Furthermore, various effects can be conveyed directly or indirectly through this specification. [Brief explanation of the drawing]

[0022] [Figure 1] This is a configuration diagram of a NAND flash memory remapping device based on access frequency according to one embodiment of the present invention. [Figure 2] An exemplary diagram of baseline mapping in a NAND flash memory according to the prior art. [Figure 3] An exemplary diagram of NAND flash memory remapping based on access frequency according to an embodiment of the present invention. [Figure 4] An exemplary diagram of NAND flash memory remapping based on access frequency according to an embodiment of the present invention. [Figure 5] An exemplary diagram of NAND flash memory remapping based on access frequency according to an embodiment of the present invention. [Figure 6] A configuration diagram of a NAND flash memory remapping device based on access frequency according to another embodiment of the present invention. [Figure 7] A flowchart of a method for NAND flash memory remapping based on access frequency according to an embodiment of the present invention. [Figure 8] An exemplary diagram of another dimensional information of RMC (Recommendation Model for Comparison) applied to a recommendation system according to the prior art. [Figure 9] An exemplary diagram of NAND flash memory remapping based on access frequency to which selective reading is applied according to an embodiment of the present invention. [Figure 10] An exemplary diagram of comparison of embedded operation time to which a NAND flash memory remapping device based on access frequency according to an embodiment of the present invention is applied in a recommendation system. [Figure 11] An exemplary diagram of comparison of energy consumption for page read operations for embedded operations to which a NAND flash memory remapping device based on access frequency according to an embodiment of the present invention is applied in a recommendation system. [Figure 12] An exemplary diagram of comparison of inference time when a NAND flash memory remapping device based on access frequency according to an embodiment of the present invention is applied using a synthetic dataset in a recommendation system. [Figure 13]This diagram illustrates a comparison of inference times when a NAND flash memory remapping device based on access frequency according to one embodiment of the present invention is applied to a recommendation system using a real dataset. [Modes for carrying out the invention]

[0023] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The advantages and features of the present invention, as well as methods for achieving them, will become clear by referring in detail to the embodiments described below, along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in a variety of different forms, although these embodiments are provided to complete the disclosure of the present invention and to allow a person ordinary skill in the art to fully understand the scope of the invention, and the present invention is defined solely by the claims. With reference to the drawings, identical or corresponding components may be given the same reference numeral.

[0024] Even though terms such as "first" and "second" are used to describe various elements, components, and / or sections, these elements, components, and / or sections are not limited by such terms. These terms are used simply to distinguish one element, component, or section from another. Therefore, the first element, first component, or first section referred to below may, within the scope of the technical idea of ​​the present invention, be a second element, a second component, or a second section.

[0025] The terms used herein are for illustrative purposes only and are not intended to limit the invention. In this specification, the singular form includes the plural form unless otherwise specified in the context. The terms “comprises” and / or “made of” as used herein do not preclude the presence or addition of one or more other components, stages, operations, and / or elements to the components, stages, operations, and / or elements described.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) are to be understood in a sense that can be commonly understood by a person of ordinary skill in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries are not to be idealized or over-analyzed unless specifically defined otherwise.

[0027] The configuration of the present invention will be described in detail below with reference to the attached drawings.

[0028] Figure 1 is a diagram showing the configuration of a NAND flash memory remapping device based on access frequency according to one embodiment of the present invention.

[0029] Referring to Figure 1, an access frequency-based NAND flash memory remapping device 100 according to one embodiment of the present invention includes a data access frequency analysis unit 110 that analyzes the access frequency to a memory area where at least one target information is stored, a data remapping unit 120 that configures a page containing the target information based on the analyzed access frequency, and a page buffer that stores the configured page and loads it when an access request is made.

[0030] NAND flash memory is a non-volatile storage medium that can store data even without a power supply. It offers high density, low cost, and high durability for data storage, making it particularly suitable for processing large amounts of data. It generally has the following configuration:

[0031] 1) NAND flash memory array: NAND flash memory is the basic unit in which data is stored, and a NAND flash chip contains multiple memory cells. Each cell can store multiple bits of data, and these cells are arranged to form pages, blocks, and planes (a cell is the basic unit for storing data, and each cell consists of a floating-gate transistor, which traps electrons to store data).

[0032] Page 2: - A page is the smallest read and write unit of NAND flash memory, and data is stored within it, typically ranging from 4 to 32 kilobytes (KB) of data. -As shown in Figure 9, the pages can be configured to allow access to target information through a single-page read operation using a selective read method, or they can be configured to allow access to target information using a sequential read method (however, in the case of a recommendation system, calculations in the embedded layer involve irregular memory access, so the selective read method is advantageous among conventional technologies, and the selective read method can be given priority).

[0033] 3) Block Multiple pages come together to form a single block, which is the smallest erasure unit of flash memory. NAND flash memory can erase or overwrite data in block units.

[0034] 4) Plain Multiple blocks come together to form a plane, and NAND flash memory generally consists of multiple planes, each of which can operate independently, thus enabling parallel data processing.

[0035] 5) Die A die is an independent operating unit of flash memory, and one die contains multiple planes; NAND flash memory processes data on a die-by-die basis.

[0036] 6) Controller When reading or writing data to NAND flash memory, the controller processes the instructions.

[0037] 7) Page buffer -The data is temporarily stored and then moved to another memory location or transferred to the CPU. - A page buffer is allocated to each plane, allowing for independent data processing via the page buffer, and data is temporarily stored there. - The page buffer can store the configured pages and load them when an access request is made.

[0038] As shown in Figure 2, the memory array of conventional NAND flash memory consists of small units called pages, each having a fixed size (for example, 16 kilobytes), and the information stored in this page is loaded into the page buffer. For example, in each time unit, the page buffer loads data from a specific page (e.g., pages #0 and #(P-1)). However, as shown in Figure 2, the majority of the page data loaded into the page buffer is not actually used, resulting in buffer waste (i.e., as shown in Figure 2, the data actually needed is located only in a limited portion of the page buffer, and the majority of the remaining page buffer stores unnecessary data, thus wasting memory bandwidth and storage space). Such waste of the page buffer reduces memory read / write efficiency and negatively impacts the overall system performance.

[0039] On the other hand, the aforementioned personalized recommendation system (hereinafter referred to as the recommendation system) is a system that analyzes a user's past activities, preferences, and behavioral patterns to provide personalized suggestions. By analyzing user experiences and preferences, such as video streaming viewing history, OTT media service click counts, and social network connection status, it is a powerful means of providing personalized recommendations. For example, various e-commerce companies have been using recommendation systems to recommend products suitable for customers and promote sales, and video service and SNS providers have been using them to suggest and provide personalized content based on the user's content usage history, thereby improving user satisfaction and sales.

[0040] In recommendation systems with these characteristics, NAND flash memory is used to improve performance through data storage efficiency, access speed, and system scalability. In other words, recommendation systems must process large amounts of user data and content information and perform complex data analysis and processing to provide personalized content to users, and in these processes, NAND flash memory plays the following roles:

[0041] (1) Storage of large-scale data Recommendation systems must store vast amounts of data, including records of users' past behavior, preferences, and interactions. NAND flash memory is a high-density storage medium that can store large amounts of data at a relatively low cost, allowing for efficient use of the physical data center space required for recommendation systems while enabling quick access to all the data needed by the recommendation system.

[0042] (2) High-speed data access Recommendation systems require high-speed data readouts to respond quickly to user requests, and NAND flash memory offers faster read and write speeds than conventional hard disk drives (HDDs), making it suitable for providing users with a lag-free service. Furthermore, recommendation systems frequently need to analyze and update user data in real time, making the high-speed data processing capabilities of NAND flash even more crucial.

[0043] (3) Scalability and flexibility Generally, recommendation systems operate on cloud-based services or large data centers, so they must be able to easily expand their data storage capacity in response to increases or decreases in the number of users. In this context, NAND flash memory provides high data transfer speeds without occupying much physical space, making it easy to integrate additional storage requirements and facilitating system scalability.

[0044] (4) Energy efficiency A significant portion of the operating costs of data centers running recommendation systems are related to energy consumption, but NAND flash memory is an energy-efficient storage medium that can reduce power consumption while maintaining the necessary performance.

[0045] Thus, the use of NAND flash memory in recommendation systems can improve the performance, cost-effectiveness, and operational flexibility of those systems.

[0046] As shown in Figure 2, in the operation of NAND flash memory in conventional recommendation systems, the physical location of stored data is determined via a hash table that records the number of accesses to each embedding vector (a vector that converts content features such as movie titles into numerical values) and the plane-page information in which the vector is stored. Stored data is then sequentially stored in the page order of each plane. At this time, page-level data is stored in the page buffer of each plane, but only a small portion of the data is actually needed. As a result, a large portion of the page-level data stored in the page buffer is not used and is wasted, reducing memory efficiency.

[0047] The embedded layer of the recommendation system exhibits irregular memory access patterns, selectively using only a small amount of necessary data from the page buffer, leaving the rest unused (in this case, the necessary data is discontinuously distributed, resulting in a very low data reuse rate in the page buffer). Furthermore, frequently accessed data is scattered across different planes and pages, preventing the equal utilization of the page buffers of each plane. Thus, in conventional recommendation systems using NAND flash memory, irregular memory access results in low data reuse rates in the page buffers of each plane, and the inefficient utilization of the page buffers of each plane can reduce the overall memory bandwidth of the system.

[0048] To solve these problems, the access frequency-based NAND flash memory remapping device 100 according to one embodiment operates the page buffer in the NAND flash memory based on access frequency information for the target information when recommending target information (for example, movies or music to be recommended). For this reason, the data access frequency analysis unit 110 of the access frequency-based NAND flash memory remapping device 100 according to one embodiment analyzes the access frequency to the memory area in which at least one piece of target information is stored.

[0049] In one embodiment, the data access frequency analysis unit 110 can sort a hash table of target information (such as movies and music to be recommended) according to the access frequency. In one embodiment, the data access frequency analysis unit 110 can analyze the access frequency to the memory area based on the hash table.

[0050] The data remapping unit 120 of the NAND flash memory remapping device 100 based on access frequency according to one embodiment can change and rearrange planes and pages in order to access target information (or embedding vectors for target information) at high speed based on the access frequency of the analyzed memory area. As an example, as shown in Figure 3, the data remapping unit 120 according to one embodiment can sequentially arrange the embedding vectors for target information on multiple planes according to the access frequency of a hash table aligned according to the access frequency.

[0051] The page buffer 130 of the NAND flash memory remapping device 100 based on access frequency according to one embodiment stores target information (or embedding vectors for target information) arranged by the data remapping unit 120 according to one embodiment. The page buffer 130 according to one embodiment stores the configured pages and can load them when an access request is made.

[0052] The hash table contains information about the frequency of access to target information and the location of that target information on the plane and page. The embedding table maps the categorical features of a specific item (for example, the title of recommended content) from a high-dimensional categorical space to a low-dimensional continuous vector space. The resulting vector is called an embedding vector, and it represents the features of the item in a numerical form.

[0053] Furthermore, as shown in Figure 4, the data remapping unit 120 according to one embodiment can distribute the embedding vectors for target information across multiple planes in a balanced manner according to the access frequency of the hash table, which is sorted according to the access frequency. That is, the data remapping unit 120 according to one embodiment can distribute a predetermined number of target information (or embedding vectors for target information) assigned to each plane and change to the next plane to place the target information. In this way, by distributing the target information evenly and cyclically across all planes, the balance of the planes on which the information is placed can be maintained. At this time, the target information (or embedding vectors for target information) to be placed is placed in the page buffer 130 of the plane on which it is placed.

[0054] Furthermore, the data remapping unit 120 according to one embodiment can arrange target information according to a rank corresponding to the access frequency and cluster information belonging to the same access rank category onto a single page. In this case, the same access rank category can be set by a predetermined threshold for access frequency. That is, the data remapping unit 120 according to one embodiment can arrange target information according to the access frequency and group information with similar access frequencies onto a single flash page (in this case, the criteria for similar access frequencies can be distinguished by a predetermined threshold).

[0055] Furthermore, the data remapping unit 120 according to one embodiment can sort target information according to a rank corresponding to the access frequency and cluster only target information with an access frequency above a predetermined threshold onto a single page. In the case of a large-scale personalized recommendation service, remapping all target information based on access frequency may result in significant overhead, so it is possible to remap only the top-ranking target information with high access frequency.

[0056] An access frequency-based NAND flash memory remapping device 100 according to one embodiment may further include a data processing unit 140 that reads the target information loaded into the page buffer.

[0057] On the other hand, the access frequency-based NAND flash memory remapping device 100 according to one embodiment may further include a page-wise cache 150 based on an LRU (Least Recently Used) policy to store the relocated target information. The page cache tracks the access time of the data stored on each page and updates the access time of the data each time it is accessed. The page cache 150 can use this information to decide which data to remove from the cache.

[0058] In one embodiment, the page cache 150 removes the page that has not been used for the longest time from the cache based on the LRU policy and replaces it with new data. Such an LRU-based page cache can improve the overall system response speed by reducing memory access time and accumulating frequently used data in the cache, which is useful in systems that require frequent data access. In one embodiment, the page cache 150 can be implemented using SRAM (Static Random Access Memory) for high-speed data processing and rapid access.

[0059] On the other hand, the NAND flash memory remapping device 100 based on access frequency according to one embodiment can implement the following additional technologies to further improve the performance of the recommended system by efficiently utilizing the storage area, improving the data processing speed, and optimizing the overall system. That is, the data remapping unit 120 according to one embodiment can apply data compression technology when remapping data using the method described above.

[0060] Furthermore, the data processing unit 140 according to one embodiment can improve processing speed by introducing multithreading and / or parallel processing techniques when reading target information loaded into the page buffer, thereby distributing the computational load required for processing large datasets. In addition, the data processing unit 140 according to one embodiment can perform embedding vector calculations based on the target information loaded into the page buffer.

[0061] Furthermore, the NAND flash memory remapping device 100 based on access frequency according to one embodiment may further include a performance monitoring unit that monitors the system performance. The performance monitoring unit according to one embodiment can monitor the system performance in real time based on metadata generated during the data processing process (e.g., access frequency, processing time, compression ratio, etc.) and take optimization measures as necessary.

[0062] On the other hand, while the aforementioned NAND flash memory remapping device 100 based on access frequency was described with the application to a personalized recommendation system as one example, it is not necessarily limited to this, and can also be applied to database management systems (DBMS), real-time analysis systems, machine learning and deep learning workloads, and various streaming services. In other words, in large-scale databases, it is important to efficiently manage frequently accessed data, so the NAND flash memory remapping device 100 based on access frequency according to one embodiment can improve data access speed and reduce I / O bottlenecks when the index access pattern shows randomness. Similarly, in real-time analysis systems that process real-time data streams requiring rapid data access and processing, the NAND flash memory remapping technology based on access frequency according to one embodiment can be used to effectively cache frequently used data and improve access speed.

[0063] Furthermore, in machine learning and deep learning that perform large-scale matrix operations, PIM-based systems can reduce data transfer costs between memory and processors and improve computation speed.

[0064] Figure 6 is an illustrative diagram of a flash memory mapping device based on access frequency according to another embodiment of the present invention.

[0065] Figure 6 is an illustrative diagram of a specific configuration of an access frequency-based flash memory mapping device according to one embodiment of the present invention shown in Figure 1, and is an illustrative diagram of a recommendation flash device (RecFlash) implemented as an access frequency-based NAND flash memory mapping device 100 consisting of a front-end 610 and a back-end 620.

[0066] The PCIe NVMe controller 630 in the front-end section 610 of the recommended flash drive 600 manages data transfer between the host system and the SSD (Solid-State Drive).

[0067] The microprocessor and DRAM within the FTL (Flash Translation Layer) 640 handle the translation between logical and physical addresses, and the DRAM contains a mapping table that stores the mapping information between these logical and physical addresses. The microprocessor also performs embedding operations and manages a transaction queue to optimize data access in the NAND flash memory. Furthermore, the SRAM (page-wise cache) within the FTL 630, operating as a page buffer 130 based on the LRU (Least Recently Used) policy, stores frequently used embedding vectors, thereby reducing the time it takes to read data from the NAND flash memory.

[0068] The page-wise cache can be stored within NAND flash memory, but basic NAND flash memory is used without modifying the commercial design. Instead, the page-wise cache is implemented within the SSD controller chip FTL630. The flash channel controller 650 is responsible for sending commands to the memory chip via the backend 620 and transferring data.

[0069] The backend section 620 of the recommended flash device 600 consists of multiple independent bus channels, each connected to one or more NAND flash chips. Each chip is divided into multiple dies 670, and each die consists of one or more planes. Each plane consists of multiple blocks, and each block consists of multiple pages. A dedicated page buffer is provided for each plane, which temporarily stores data read from the NAND flash array 660 before transferring it to the SSD controller.

[0070] When an embedded vector requiring data is requested, the recommended flash memory unit 600 first checks if the vector already exists in the page cache (Page-Wise Cache), as shown in Figure 5. If it exists in the page cache, it immediately reads the data from the page cache, reducing the time it takes to read from the NAND flash memory. If the data does not exist in the page cache, it reads the data from the NAND flash array into the page buffer, stores the data in the cache, and prepares it for future requests.

[0071] The following describes an access frequency-based NAND flash memory remapping method according to one embodiment of the present invention, based on the above description.

[0072] Figure 7 shows an access frequency-based NAND flash memory remapping method according to one embodiment of the present invention, and is a flowchart of the access frequency-based NAND flash memory remapping method using the access frequency-based NAND flash memory remapping device of the present invention shown in Figure 1.

[0073] Referring to Figure 7, in one embodiment of the present invention, the NAND flash memory remapping method based on access frequency analyzes the access frequency to a memory area in the NAND flash memory where at least one target piece of information is stored using a data access frequency analysis unit 110 (S710).

[0074] In this case, when analyzing the access frequency to a memory area in NAND flash memory where at least one target piece of information is stored, the number of accesses for each item in the memory area can be analyzed based on a hash table, and the determined access frequency can be analyzed.

[0075] Based on the access frequency to the analyzed memory area, the data remapping unit 120 configures a page containing the target information (S720), and loads the configured page containing the target information into the page buffer of the plane where the target information is stored (S730).

[0076] When the data remapping unit 120 constructs a page containing target information based on the access frequency of the analyzed memory area, the target information can be placed in consecutive address areas within the same page so that it can be accessed only by single-page read operations according to the selective read method.

[0077] When the data remapping unit 120 constructs a page containing target information based on the access frequency of the analyzed memory area, it can arrange the target information according to a rank corresponding to the access frequency and cluster information belonging to the same access rank category into a single page. At this time, the same access rank category can be set by a predefined threshold for access frequency.

[0078] On the other hand, based on the access frequency to the analyzed memory area, the data remapping unit 120 can rearrange the target information into pages for high-speed access.

[0079] At this time, when rearranging the target information into pages for high-speed access based on the access frequency of the analyzed memory area, the data remapping unit 120 can sequentially rearrange the target information into pages within the memory area based on the access frequency, as shown in Figure 3.

[0080] In contrast, when rearranging target information into pages for high-speed access based on the access frequency of the analyzed memory area, the data remapping unit 120 can rearrange the target information into pages of a plane allocated based on the balanced arrangement between memory area planes, as shown in Figure 4.

[0081] The data processing unit 140 reads the target information loaded into the page buffer (S740). The data processing unit 140 can perform calculations on the embedding vector based on the target information loaded into the page buffer.

[0082] On the other hand, the access frequency-based NAND flash memory remapping device 100 according to one embodiment can be additionally placed in a cache memory (page cache) for high-speed access with the highest priority based on the access frequency to the analyzed memory area. The access frequency-based NAND flash memory remapping device 100 according to one embodiment can store target information rearranged based on the LRU (Least Recently Used) policy and perform page-level caching in order to access target information with the highest priority based on the access frequency to the analyzed memory area.

[0083] As an example, the access frequency-based NAND flash memory remapping device 100, when an embedded vector requiring data is requested, first checks if the vector already exists in the page cache. If it exists in the page cache, it immediately reads the data from the page cache, reducing the time it takes to read from the NAND flash memory. If the data does not exist in the page cache, the device reads the data from the NAND flash array into the page buffer, stores the data in the cache, and prepares it for future requests.

[0084] Figures 10 to 13 are illustrative diagrams of performance tests for each RMC (Recommendation Model for Comparison) when the access frequency-based NAND flash memory remapping device 100 according to one embodiment of the present invention is applied to the conventional recommendation system shown in Figure 8.

[0085] The RMC model is a series of experimental models based on DLRM (Deep Learning Recommendation Model) used in recommendation systems. It is generally defined in papers and patents as a benchmark model for testing recommendation models of various structures, and can be used particularly when experimenting with different computational bottleneck structures in recommendation systems. The DLRM model is composed of an embedding layer and a fully-connected layer at its core.

[0086] Generally, the embedding layer transforms sparse features such as users and item categories into vectors, has random memory access patterns, and consumes a large amount of bandwidth. The fully connected layer (FC Layer) is the center of the computational bottleneck and, like conventional neural network layers, has computationally intensive characteristics. The configurations of the embedding and fully connected layers in the RMC1, RMC2, and RMC3 models can be configured as shown in Figure 8.

[0087] Figure 10 is an illustrative diagram of a comparison of embedding calculation times when the access frequency-based NAND flash memory remapping device 100 according to one embodiment of the present invention is applied in a recommendation system. Using a composite dataset (K0, K0.3, K0.8, K1, K2), normalization is performed based on RM-SSD (selective read), and since RecSSD is sequential read, each experimental result value is shown to be greater than 1.

[0088] Figure 10 quantitatively shows the extent to which access frequency-based clustering according to one embodiment of the present invention can substantially accelerate embedding operations. As shown in Figure 10, the access frequency-based NAND flash memory remapping device 100 according to one embodiment has the greatest effect in the RMC2 model centered on the embedding layer.

[0089] Specifically, the smaller the K value (i.e., the more frequently accessed data), the greater the performance improvement. Compared to RM-SSD, computation time can be reduced by up to 91.4% (K0, RMC2), demonstrating the cumulative performance improvement effects of clustering (AF), plane distribution (PD), and page caching (P$).

[0090] Figure 11 is an illustrative diagram of a comparison of energy consumption in a page read operation for embedding calculations in a recommendation system to which an access frequency-based NAND flash memory remapping device according to one embodiment of the present invention is applied. The figure shows the case where a composite dataset (K0, K0.3, K0.8, K1, K2) is used, and both RM-SSD (selective read) and RecSSD (sequential read) perform the same page read operation twice, with each experimental result value being the same at 1.

[0091] Figure 11 shows experimental results verifying the effectiveness of memory access optimization from an energy perspective. It shows experimental results measuring how much energy efficiency can be improved by various remapping methods (AF, AF+PD, AF+PD+P$) of an access frequency-based NAND flash memory remapping device according to one embodiment of the present invention compared to conventional technologies (RecSSD, RM-SSD).

[0092] As shown in Figure 11, the access frequency-based remapping method of the present invention shows a maximum page read energy reduction effect of 91.9% compared to conventional methods, with the most significant improvement being seen in the RMC2 model, which is centered on the embedded layer. The performance improvement compared to previous studies is greatest in the K0 case and smallest in the K2 case.

[0093] Figure 12 is an illustrative diagram of a comparison of inference times when a synthetic dataset is used in a recommendation system and an access frequency-based NAND flash memory remapping device according to one embodiment of the present invention is applied, showing the case when synthetic datasets (K0, K0.3, K0.8, K1, K2) are used.

[0094] As shown in Figure 12, in data access bottlenecks (embedding-heavy structures), it is possible to improve not only latency but also system throughput. Remapping alone is highly effective, and when combined with plane distribution (PD) and caching (P$) strategies, performance improves incrementally. Furthermore, the performance improvement compared to previous studies is greatest in the K0 case and smallest in the K2 case. Since this is inference time for the overall model, the performance improvement compared to previous studies is greatest in the RMC2 case and smallest in the RMC3 case.

[0095] Figure 13 is an illustrative diagram of the inference time comparison when an access frequency-based NAND flash memory remapping device according to one embodiment of the present invention is applied to a recommendation system using a real dataset. It shows experimental results measuring how much the access frequency-based NAND flash memory remapping device according to one embodiment reduces the overall model inference time (End-to-End Inference Latency) in actual recommendation system data, using real datasets such as Criteo TB and Criteo Kaggle, which are the largest real-world datasets used in the recommendation system.

[0096] Referring to Figure 13, when a real dataset is used in a recommendation system and the access frequency-based NAND flash memory remapping device according to one embodiment of the present invention is applied, the performance improvement compared to the previous study is greatest with the Criteo TB dataset. The performance improvement compared to the previous study is greatest in the K0 case and smallest in the K2 case, showing a maximum performance improvement of 80.1% based on the total inference time, demonstrating that a significant reduction in latency is possible even in an actual recommendation system.

[0097] As described above, the present invention maximizes the utilization of internal memory bandwidth and improves the efficiency of data processing by using data remapping technology, which concentrates data on specific pages of NAND flash according to access frequency to enable efficient use of memory, and a page-level cache that supports high-speed access to frequently accessed data. As a result, power consumption can be reduced and energy consumption can be lowered.

[0098] The embodiments described above can be implemented using various forms of computing means, including one or more processors, memory, and storage means. They can also include a network interface connected to a wired or wireless network. The processor may be a central processing unit or semiconductor device that executes processing instructions stored in memory and / or storage units. The memory and storage units may include volatile or non-volatile storage media. For example, the memory may include ROM and RAM. Thus, embodiments of the present invention can be implemented as a method on a computer or as a non-temporary computer-readable medium having computer-executable instructions stored on the computer. In one embodiment of the present invention, when implemented by a processor, the computer-readable instructions can execute a method according to at least one aspect of the present invention.

[0099] As described above with reference to the illustrated embodiments of the present invention, these are merely illustrative examples, and it will be clear to any person with ordinary skill in the art to which the present invention pertains that various modifications, changes, and equivalent embodiments are possible without departing from the spirit and scope of the present invention. For example, the data access frequency analysis unit 110 and the data remapping unit 120 may be implemented as an integrated module or divided and implemented in two or more devices. Therefore, the true scope of technical protection of the present invention should be determined by the technical idea of ​​the appended claims. [Explanation of Symbols]

[0100] 100 NAND flash memory remapping device based on access frequency 110 Data Access Frequency Analysis Unit 120 Data Remapping Section 130 page buffer 140 Data Processing Unit 150 pages cache

Claims

1. A data access frequency analysis unit analyzes the access frequency to a memory area where at least one piece of target information is stored, A data remapping unit that configures a page containing the target information based on the analyzed access frequency, A NAND flash memory remapping device based on access frequency, including a page buffer that stores the configured pages and loads them when an access request is made.

2. The NAND flash memory remapping device according to claim 1, wherein the page is configured to allow access to target information through a single-page read operation using a selective read method.

3. The NAND flash memory remapping device based on access frequency according to claim 1, wherein the data access frequency analysis unit analyzes the access frequency to the memory area based on a hash table.

4. The NAND flash memory remapping device based on access frequency according to claim 1, wherein the data access frequency analysis unit rearranges the target information on pages of planes allocated based on the balanced arrangement between planes of the memory area based on the access frequency.

5. The access frequency-based NAND flash memory remapping device according to claim 1, further comprising a page-wise cache that stores target information rearranged based on an LRU (Least Recently Used) policy and performs page-wise caching.

6. The NAND flash memory remapping apparatus based on access frequency according to claim 1, further comprising a data processing unit that performs an embedding vector calculation based on the target information loaded into the page buffer.

7. The data remapping unit sorts the target information according to a rank corresponding to the access frequency, and clusters the information belonging to the same access rank category onto a single page. The NAND flash memory remapping device based on access frequency according to claim 1, wherein the same access rank category is set by a predefined access frequency threshold.

8. The steps involve analyzing the access frequency to a memory area in NAND flash memory where at least one target piece of information is stored, A step of constructing a page containing the target information based on the frequency of access to the analyzed memory area, A NAND flash memory remapping method based on access frequency, comprising the steps of loading a page containing the configured target information into a page buffer of a plane storing the target information.

9. The step of configuring a page containing the target information based on the access frequency to the analyzed memory region is: The NAND flash memory remapping method based on access frequency according to claim 8, further comprising the step of arranging the target information in a contiguous address area within the same page such that the target information can be accessed by a single-page read operation only, according to a selective read method.

10. The step of analyzing the access frequency to a memory area in the NAND flash memory where at least one target piece of information is stored is: The NAND flash memory remapping method based on access frequency according to claim 8, further comprising the step of analyzing the number of accesses per item in the memory area based on a hash table and analyzing the determined access frequency.

11. The access frequency-based NAND flash memory remapping method according to claim 8, further comprising the step of rearranging the target information on pages of planes allocated based on a balanced arrangement between planes of the memory area based on the access frequency.

12. In order to access the target information at high speed with the highest priority based on the access frequency to the analyzed memory area, The access frequency-based NAND flash memory remapping method according to claim 8, further comprising storing target information rearranged based on an LRU (Least Recently Used) policy and performing page-level caching.

13. The access frequency-based NAND flash memory remapping method according to claim 8, further comprising the step of performing an embedding vector operation based on the target information loaded into the page buffer.

14. The step of configuring a page containing the target information based on the access frequency to the analyzed memory region is: The step of sorting the aforementioned target information according to a rank corresponding to the access frequency, Does it belong to the same access rank category? This includes the stage of clustering information onto a single page. The NAND flash memory remapping method based on access frequency according to claim 8, wherein the same access rank category is set by a predefined access frequency threshold.

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