Chip scale packaging bare crystal protection plate on printed circuit board

Abstract

The utility model relates to the technical field of printed circuit boards, and discloses a chip scale packaging bare crystal protection board on a printed circuit board, which comprises a protection board main body, the protection board main body comprises a substrate layer, a shielding layer, a waterproof layer and a buffer layer, the shielding layer is arranged on the upper surface of the substrate layer, the waterproof layer is arranged on the upper surface of the shielding layer, and the buffer layer is arranged on the upper surface of the waterproof layer. The buffer layer is arranged on the upper surface of the waterproof layer; the substrate layer adopts a polyimide plate body; the shielding layer adopts a copper foil net layer; the waterproof layer adopts a nano waterproof coating layer; the buffer layer is an elastic rubber layer. According to the utility model, the problem that the chip scale packaging bare crystal is easily influenced by environmental factors to be damaged is effectively solved from multiple aspects, the chip scale packaging bare crystal has excellent performance in the aspects of ensuring the stable operation of the chip, prolonging the service life of the chip, reducing the maintenance difficulty and cost and the like, provides powerful support for the reliability and the stability of electronic products, and is suitable for popularization and application. The method has an important practical value and a wide application prospect, and is helpful for promoting further development of the technical field of electronics.

Description

TECHNICAL FIELD

[0001] The utility model relates to printed circuit board technical field especially relates to a chip scale package bare chip protection plate on printed circuit board. BACKGROUND

[0002] With the rapid development of electronic technology, chip scale package (CSP) technology has been widely used in electronic products. On the printed circuit board, the chip scale package bare chip is directly exposed to the outside, which is easily affected by external environmental factors such as humidity, dust, static electricity and physical impact, resulting in performance degradation, short circuit, open circuit and even permanent damage of the chip.

[0003] In the prior art, although there are some simple packaging methods, the protection effect of the chip scale package bare chip is not ideal. For example, the traditional plastic packaging may have water vapor penetration in high temperature and high humidity environment, affecting the reliability of the chip; and some simple shielding cover has the disadvantage of poor protection against physical impact, and cannot fully meet the protection requirements of the chip scale package bare chip in complex environment.

[0004] Therefore, it is of great practical significance to develop a protection plate that can effectively protect the chip scale package bare chip. UTILITY MODEL CONTENTS

[0005] The utility model discloses a chip scale package bare chip protection plate on printed circuit board, which can effectively protect the chip scale package bare chip, prevent the chip scale package bare chip from being damaged by external environmental factors, and improve the reliability of the chip scale package bare chip.

[0006] In order to achieve the above-mentioned purpose, the utility model adopts the following technical scheme:

[0007] A chip scale package bare chip protection plate on printed circuit board, comprising a protection plate main body, the protection plate main body includes a substrate layer, a shielding layer, a waterproof layer and a buffer layer, the shielding layer is arranged on the upper surface of the substrate layer, the waterproof layer is arranged on the upper surface of the shielding layer, and the buffer layer is arranged on the upper surface of the waterproof layer.

[0008] The substrate layer is made of a polyimide plate body.

[0009] The shielding layer is made of a copper foil net layer.

[0010] The waterproof layer is made of a nano waterproof coating layer.

[0011] The buffer layer is made of an elastic rubber layer.

[0012] Preferably, the four side walls of the substrate layer, the four side walls of the shielding layer, the four side walls of the waterproof layer and the four side walls of the buffer layer are provided with the same sealing frame, and the material of the sealing frame is the same as that of the substrate layer.

[0013] Preferably, the lower surface of the substrate layer is provided with a plurality of welding pins extending outward on both sides.

[0014] Preferably, the lower surface of the substrate layer is provided with a heat-conducting silica gel layer in contact with the circuit board.

[0015] Preferably, the thickness of the substrate layer is 0.1mm-0.5mm, the thickness of the shielding layer is 0.05mm-0.2mm, the thickness of the waterproof layer is 0.01mm-0.05mm, and the thickness of the buffer layer is 0.5mm-0.8mm.

[0016] Preferably, the four side walls of the sealing frame are provided with anti-skid lines.

[0017] Compared with the prior art, the chip scale package bare die protection plate on the printed circuit board has the following beneficial effects:

[0018] 1. All-round environmental protection: the protection plate body is designed through a multi-layer structure, the shielding layer (copper foil net layer) can block external electromagnetic interference and static electricity, avoid damage to the chip scale package bare die, and ensure the electrical stability of the chip; the waterproof layer (nanometer waterproof paint layer) forms a dense waterproof film, effectively prevents moisture penetration, prevents short circuit or performance degradation of the chip due to moisture erosion, and significantly improves the reliability of the chip in a humid environment; the buffer layer (elastic rubber layer) can absorb and disperse impact force when subjected to physical impact, reduce the impact of impact on the bare die, and reduce the risk of damage to the chip due to external impact.

[0019] 2. Stable installation and heat dissipation assistance: the welding pins on both sides of the lower surface of the substrate layer ensure the firm connection between the protection plate body and the printed circuit board, ensure that the protection plate body is stable in position during equipment operation, and will not be displaced due to factors such as vibration, maintaining continuous protection of the bare die, and at the same time, the heat-conducting silica gel layer on the lower surface of the substrate layer helps to quickly conduct the heat generated by the bare die during operation to the printed circuit board, avoiding heat accumulation in the protection plate affecting the performance of the bare die, further ensuring that the chip works stably in a suitable temperature environment, and prolonging the service life of the chip.

[0020] 3. Enhanced structural integrity and operational convenience: the sealing frame (same material as the substrate layer) provided on the four side walls strengthens the overall structure of the protection plate, prevents dust and other impurities from entering the inside of the protection plate from the edges, and keeps the environment around the bare die clean.

[0021] The part not involved in the device is the same as or can be realized by the prior art, the chip scale package bare chip is effectively solved from multiple aspects The problem of being easily damaged by environmental factors, performs well in aspects of guaranteeing stable operation of the chip, prolonging service life of the chip, reducing maintenance difficulty and cost, and the like, and provides strong support for reliability and stability of electronic products. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 A structure schematic diagram of a chip scale package bare chip protection plate on a printed circuit board is provided in the utility model.

[0023] Figure 2 For Figure 1 The cross-sectional structure schematic diagram of the protection plate main body is shown in the figure.

[0024] Figure 3 For Figure 2 The structure schematic diagram of the shielding layer is shown in the figure.

[0025] In the figure: 1, protection plate main body; 2, base plate layer; 3, shielding layer; 4, waterproof layer; 5, buffer layer; 6, sealing frame; 7, welding pin; 8, heat-conducting silica gel layer; 9, anti-skid lines. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments.

[0027] In the description of the utility model, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the utility model.

[0028] Referring to Figures 1-3A chip-scale packaged bare die protection board for a printed circuit board includes a protection board body 1. The protection board body 1 includes a substrate layer 2, a shielding layer 3, a waterproof layer 4, and a buffer layer 5. The shielding layer 3 is disposed on the upper surface of the substrate layer 2, the waterproof layer 4 is disposed on the upper surface of the shielding layer 3, and the buffer layer 5 is disposed on the upper surface of the waterproof layer 4. The substrate layer 2 is made of polyimide, the shielding layer 3 is made of copper foil mesh, the waterproof layer 4 is made of nano-waterproof coating, and the buffer layer 5 is made of elastic rubber. The four sides of the substrate layer 2, the four sides of the shielding layer 3, and the waterproof layer 4 are all protected by a protective layer. The four sides of the substrate layer 2 and the four sides of the buffer layer 5 are provided with the same sealing frame 6, and the material of the sealing frame 6 is the same as that of the substrate layer 2. The four sides of the sealing frame 6 are provided with anti-slip textures 9 to prevent slippage, improve the convenience and accuracy of operation, and reduce the difficulty and time cost of maintenance. The thickness of the substrate layer 2 is 0.1mm-0.5mm, the thickness of the shielding layer 3 is 0.05mm-0.2mm, the thickness of the waterproof layer 4 is 0.01mm-0.05mm, and the thickness of the buffer layer 5 is 0.5mm-0.8mm.

[0029] Reference Figures 1-2 Multiple outwardly extending solder pins 7 are provided on both sides of the lower surface of the substrate layer 2 to ensure a firm connection between the protection board body 1 and the printed circuit board, ensuring that the position of the protection board body 1 is stable during equipment operation and will not be displaced due to vibration or other factors, thus maintaining continuous protection for the bare die. A thermally conductive silicone layer 8 is provided on the lower surface of the substrate layer 2 to contact the circuit board, which helps to quickly conduct the heat generated by the bare die during operation to the printed circuit board, preventing heat from accumulating in the protection board and affecting the performance of the bare die.

[0030] In this invention, in practical applications, the protective board body 1 is mounted on the printed circuit board via the soldering pins 7 on the lower surface of the substrate layer 2, so that the protective board body 1 covers the bare die of the chip-scale package. When there is electromagnetic interference or static electricity in the outside, the shielding layer 3 uses its metallic properties to shield and conduct it away, avoiding interference and static electricity from affecting the bare die. If there is moisture in the environment, the waterproof layer 4 uses the properties of nano-waterproof coating to block moisture from entering. Once subjected to physical collision, the elastic rubber structure of the buffer layer 5 deforms to absorb the impact force. The heat generated by the bare die during operation is conducted to the printed circuit board through the thermally conductive silicone layer 8 and dissipated. The sealing frame 6 always maintains the sealing of the protective board body 1 to prevent dust intrusion. The anti-slip texture 9 provides convenient hand grip points during installation and disassembly.

[0031] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A chip scale package die shield for a printed circuit board, comprising a shield body (1), characterized in that The protection plate body (1) comprises a substrate layer (2), a shielding layer (3), a waterproof layer (4) and a buffer layer (5), the shielding layer (3) is arranged on the upper surface of the substrate layer (2), the waterproof layer (4) is arranged on the upper surface of the shielding layer (3), and the buffer layer (5) is arranged on the upper surface of the waterproof layer (4). The substrate layer (2) is a polyimide plate body. The shielding layer (3) is a copper foil net layer. The waterproof layer (4) is a nano waterproof coating layer. The buffer layer (5) is an elastic rubber layer.

2. The chip scale package die panel for printed circuit boards of claim 1 wherein, The four peripheral side walls of the substrate layer (2), the four peripheral side walls of the shielding layer (3), the four peripheral side walls of the waterproof layer (4) and the four peripheral side walls of the buffer layer (5) are provided with the same sealing frame (6), and the material of the sealing frame (6) is the same as that of the substrate layer (2).

3. The chip scale package die panel on printed circuit board of claim 1, wherein, The lower surface of the substrate layer (2) is provided with a plurality of welding pins (7) extending outward on both sides.

4. The chip scale package die panel for printed circuit boards of claim 1 wherein, The lower surface of the substrate layer (2) is provided with a heat-conducting silica gel layer (8) in contact with the circuit board.

5. The chip scale package die panel for printed circuit boards of claim 1 wherein, The thickness of the substrate layer (2) is 0.1-0.5mm, the thickness of the shielding layer (3) is 0.05-0.2mm, the thickness of the waterproof layer (4) is 0.01-0.05mm, and the thickness of the buffer layer (5) is 0.5-0.8mm.

6. The chip scale package die panel on printed circuit board of claim 2, wherein, The four peripheral side walls of the sealing frame (6) are provided with anti-skid lines (9).

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