Bootstrap driving module based on three-level circuit topology

Abstract

The utility model discloses a bootstrap driving module based on a three-level circuit topology, which successfully provides a power supply for all power devices in a three-level inverter topology by using a low-voltage input direct-current power supply, so that the system cost is remarkably reduced. According to the innovative scheme, a common multi-path high-voltage power supply and a complex voltage conversion unit in a traditional three-level inverter design are avoided, and power supply management is simplified. According to the scheme, efficient motor driving is provided under the low-voltage condition, and the cost and the system weight are reduced by reducing the use of a high-voltage system.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the self-boosting drive module field, concretely relates to a self-boosting drive module based on three level circuit topology. BACKGROUND

[0002] At present, three-level inverter is widely applied in multiple fields, for example photovoltaic power generation, wind power generation, can improve the efficiency, stability and safety of system, and simultaneously improves power factor and harmonic distortion problem, improves the overall performance of system.

[0003] Because the voltage platform is high in the application field, the power supply and the driving part all adopt the isolation scheme, Figure 1 As shown in the driving scheme principle architecture, Figure 2 As shown in the power part electrical architecture diagram.

[0004] Combining Figure 4 With Figure 6 Taking A phase as an example, the original side input low voltage direct current, passes through the transformer original side non-isolation feedback, and the secondary side isolation generates the secondary side positive and negative power supply voltage of isolation drive chip. The ground of power device A1 drive power supply is Hs1, the ground of A2 drive power supply is HS2, the ground of A3 / 6 drive power supply is HS3, the ground of A4 drive power supply is GND, and the ground of A5 drive power supply is HS5. Again combining Figure 2 The power architecture diagram can know that the ground of A / B / C4 drive power supply is GND, the ground of A / B / C5 drive power supply is HS5, so 11 isolation power supplies are needed.

[0005] Combining Figure 4 , 5 , 6 can know that there are 11 grounds of three-level inverter architecture power device, and it is commonly used for superhigh voltage platform, so the driving adopts full isolation scheme, and 11 isolation power supplies and 18 isolation drives are needed. If the scheme is applied to low voltage platform, the system cost will be greatly increased, and the product has no competitiveness at all.

[0006] Therefore, the utility model is provided. UTILITY MODEL CONTENT

[0007] The utility model solves the technical problem of overcoming the defects of prior art, and provides a self-boosting drive module based on three level circuit topology, which solves the problems in the background technology.

[0008] To solve the above technical problems, the basic idea of the technical scheme of the utility model is:

[0009] The bootstrap drive module based on the three-level circuit topology comprises a first drive circuit, a second drive circuit, a third drive circuit, a fourth drive circuit, the second drive circuit is signal-connected with the first drive circuit, the third drive circuit and the fourth drive circuit, and the first drive circuit and the fourth drive circuit both receive signals of the third drive circuit.

[0010] Optionally, the first drive circuit comprises a triode Q1, a triode Q2, a triode Q3, a reverse isolation diode D1, a reverse isolation diode D2 and a first optocoupler, a No. 1 pin of the triode Q1 is used for receiving an A1 drive signal, a No. 2 pin of the triode Q1 is grounded, and a No. 3 pin of the triode Q1 is electrically connected with an output side of the first optocoupler.

[0011] An anode of the reverse isolation diode D1 is used for receiving a power supply voltage, a cathode of the reverse isolation diode D1 is electrically connected with a No. 2 pin of the triode Q2, and the cathode of the reverse isolation diode D1 is further electrically connected with a first A1_HS high-side switch after receiving the power supply voltage.

[0012] A No. 1 pin of the triode Q2 is electrically connected with an input side of the first optocoupler, and a No. 3 pin of the triode Q2 is connected with an anode of the reverse isolation diode D2.

[0013] A cathode of the reverse isolation diode D2 is connected with a No. 2 pin of the triode Q3, and the cathode of the reverse isolation diode D6 is further connected with a No. 2 pin of the triode Q9 and a second A1_HS high-side switch.

[0014] A No. 1 pin of the triode Q3 is electrically connected with a No. 3 pin of the triode Q3 and a third A1_HS high-side switch.

[0015] Optionally, the second drive circuit further comprises a triode Q4, a triode Q5, a triode Q6, a reverse isolation diode D3, a reverse isolation diode D4 and a second optocoupler.

[0016] A No. 1 pin of the triode Q4 is used for receiving an A4 drive signal, a No. 2 pin of the triode Q4 is grounded, and a No. 3 pin of the triode Q4 is electrically connected with an output side of the second optocoupler.

[0017] A No. 2 pin of the triode Q5 is used for being grounded after receiving the power supply voltage, and a No. 1 pin of the triode Q5 is electrically connected with an input side of the second optocoupler.

[0018] A No. 3 pin of the triode Q5 is connected with an anode of the reverse isolation diode D4, a cathode of the reverse isolation diode D4 is connected with a No. 2 pin of the triode Q6, the cathode of the reverse isolation diode D4 is further connected with the No. 2 pin of the triode Q6 and an A4_HS high-side switch, and a No. 1 pin and a No. 3 pin of the triode Q6 are used for being grounded.

[0019] Optionally, the third driving circuit comprises a transistor Q7, a transistor Q8, a transistor Q9, a transistor Q10, a reverse isolation diode D5, a reverse isolation diode D6, a third optocoupler;

[0020] The No.1 pin of the transistor Q7 and the No.1 pin of the transistor Q10 are used for receiving an A2 / 6 driving signal, the No.2 pin of the transistor Q7 and the No.2 pin of the transistor Q10 are grounded, and the No.3 pin of the transistor Q7 is electrically connected with the output side of the third optocoupler;

[0021] The anode of the reverse isolation diode D5 is used for receiving a power supply voltage, the cathode of the reverse isolation diode D5 and the No.2 pin of the transistor Q8 are electrically connected, and the first A2_HS high side switch is further electrically connected after receiving the power supply voltage;

[0022] The No.1 pin of the transistor Q8 and the input side of the third optocoupler are electrically connected, the No.3 pin of the transistor Q8 and the anode of the reverse isolation diode D6 are connected, the cathode of the reverse isolation diode D6 and the No.2 pin of the transistor Q9 are connected, the cathode of the reverse isolation diode D6 and the No.2 pin of the transistor Q9 are further connected with the second A2_HS high side switch, and the No.1 pin and the No.3 pin of the transistor Q9 are electrically connected with the third A2_HS high side switch.

[0023] Optionally, the third driving circuit further comprises a transistor Q11, a transistor Q12, a reverse isolation diode D7, a reverse isolation diode D8, a fourth optocoupler;

[0024] The No.3 pin of the transistor Q10 and the output side of the fourth optocoupler are electrically connected, and the No.1 pin of the transistor Q11 and the input side of the fourth optocoupler are electrically connected;

[0025] The anode of the reverse isolation diode D7 is used for receiving a power supply voltage, the cathode of the reverse isolation diode D7 and the No.2 pin of the transistor Q10 are electrically connected and generate an A3 / 6_PW signal after receiving the power supply voltage, and the first A3 / 6_HS high side switch is further electrically connected at the same time of generating the signal;

[0026] The No.3 pin of the transistor Q11 and the anode of the reverse isolation diode D4 are connected, the cathode of the reverse isolation diode D8 and the No.2 pin of the transistor Q12 are electrically connected with the A6_HS high side switch, and the No.1 pin and the No.3 pin of the transistor Q12 are electrically connected with the second A3 / 6_HS high side switch.

[0027] Optionally, the fourth driving circuit comprises a transistor Q13, a transistor Q14, a transistor Q15, a transistor Q16, a reverse isolation diode D9, a fifth optocoupler;

[0028] The No.1 pin of the triode Q13 is used for receiving an A3 / 5 driving signal, the No.2 pin of the triode Q13 and the No.2 pin of the triode Q16 are grounded, and the No.3 pin of the triode Q13 is electrically connected with the output side of the fourth optical coupler;

[0029] The No.1 pin of the triode Q14 is electrically connected with the input side of the fifth optical coupler, the No.2 pin of the triode Q14 is used for receiving an A3 / 6_PW signal and is electrically connected with a first A3 / 6_HS high-side switch;

[0030] The No.3 pin of the triode Q14 is connected with the anode of the reverse isolation diode D9, the cathode of the reverse isolation diode D9 is connected with the No.2 pin of the triode Q16, and the No.1 pin and the No.3 pin of the triode Q16 are electrically connected with a second A3 / 6_HS high-side switch.

[0031] Optionally, the fourth driving circuit further comprises a triode Q17, a triode Q18, a reverse isolation diode D10, a reverse isolation diode D11, a sixth optical coupler;

[0032] The No.3 pin of the triode Q16 is electrically connected with the output side of the sixth optical coupler, and the No.1 pin of the triode Q17 is electrically connected with the input side of the fourth optical coupler;

[0033] The anode of the reverse isolation diode D10 is used for receiving an A3 / 6_PW, the cathode of the isolation diode D10 is electrically connected with the No.2 pin of the triode Q17, and the cathode of the isolation diode D10 is further electrically connected with a first A5_HS high-side switch;

[0034] The No.3 pin of the triode Q16 is connected with the anode of the reverse isolation diode D11, and the cathode of the reverse isolation diode D11 is electrically connected with the No.2 pin of the triode Q18 and a second A5_HS high-side switch;

[0035] The No.1 pin and the No.3 pin of the triode Q18 are electrically connected with a third A5_HS high-side switch.

[0036] Compared with the prior art, the utility model has the following beneficial effects, of course, any product implementing the utility model does not necessarily need to achieve all the advantages described below:

[0037] By using a low-voltage input DC power supply, the design successfully provides power supply for all power devices in the three-level inverter topology, thereby significantly reducing the system cost. This innovative scheme avoids the common multi-high-voltage power supply and complex voltage conversion unit in the traditional three-level inverter design, simplifying power management. It is particularly suitable for low-voltage and low-speed electric vehicle motor drive. This scheme not only provides efficient motor drive under low-voltage conditions, but also reduces cost and system weight by reducing the use of high-voltage systems.

[0038] The specific embodiments of the present application will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0039] The drawings described in the following description are only some embodiments, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings. In the drawings

[0040] In the drawings:

[0041] Figure 1 is a schematic diagram of the first drive circuit and the second drive circuit;

[0042] Figure 2 is a schematic diagram of the third drive circuit;

[0043] Figure 3 is a schematic diagram of the fourth drive circuit;

[0044] Figure 4 is one of the schematic diagrams of the prior art three-level inverter architecture;

[0045] Figure 5 is one of the schematic diagrams of the prior art three-level inverter architecture;

[0046] Figure 6 is one of the schematic diagrams of the prior art three-level inverter architecture.

[0047] It should be noted that these drawings and written descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0048] The present application will now be further described in detail with reference to the accompanying drawings.

[0049] Please refer to Figures 1-3As shown, in the embodiment, a bootstrap drive module based on a three-level circuit topology is provided, which comprises a first drive circuit, a second drive circuit, a third drive circuit, and a fourth drive circuit, the second drive circuit is connected with the first drive circuit, the third drive circuit, and the fourth drive circuit in signal, and the first drive circuit and the fourth drive circuit both receive signals from the third drive circuit.

[0050] The first drive circuit of the embodiment comprises a transistor Q1, a transistor Q2, a transistor Q3, a reverse isolation diode D1, a reverse isolation diode D2, and a first optocoupler, the No. 1 pin of the transistor Q1 is used for receiving an A1 drive signal, the No. 2 pin of the transistor Q1 is grounded, and the No. 3 pin of the transistor Q1 is electrically connected with the output side of the first optocoupler.

[0051] The anode of the reverse isolation diode D1 is used for receiving a power supply voltage, the cathode of the reverse isolation diode D1 is electrically connected with the No. 2 pin of the transistor Q2, and the cathode of the reverse isolation diode D1 is further electrically connected with a first A1_HS high-side switch after receiving the power supply voltage.

[0052] The No. 1 pin of the transistor Q2 is electrically connected with the input side of the first optocoupler, and the No. 3 pin of the transistor Q2 is connected with the anode of the reverse isolation diode D2.

[0053] The cathode of the reverse isolation diode D2 is connected with the No. 2 pin of the transistor Q3, and the cathode of the reverse isolation diode D6 is further connected with a second A1_HS high-side switch with the No. 2 pin of the transistor Q9.

[0054] The No. 1 pin and the No. 3 pin of the transistor Q3 are electrically connected with a third A1_HS high-side switch.

[0055] The second drive circuit of the embodiment further comprises a transistor Q4, a transistor Q5, a transistor Q6, a reverse isolation diode D3, a reverse isolation diode D4, and a second optocoupler.

[0056] The No. 1 pin of the transistor Q4 is used for receiving an A4 drive signal, the No. 2 pin of the transistor Q4 is grounded, and the No. 3 pin of the transistor Q4 is electrically connected with the output side of the second optocoupler.

[0057] The No. 2 pin of the transistor Q5 is used for being grounded after receiving a power supply voltage, and the No. 1 pin of the transistor Q5 is electrically connected with the input side of the second optocoupler.

[0058] The No. 3 pin of the transistor Q5 is connected with the anode of the reverse isolation diode D4, the cathode of the reverse isolation diode D4 is connected with the No. 2 pin of the transistor Q6, the cathode of the reverse isolation diode D4 is further connected with an A4_HS high-side switch with the No. 2 pin of the transistor Q6, and the No. 1 pin and the No. 3 pin of the transistor Q6 are used for being grounded.

[0059] The third driving circuit of the embodiment comprises a transistor Q7, a transistor Q8, a transistor Q9, a transistor Q10, a reverse isolation diode D5, a reverse isolation diode D6, a third optocoupler;

[0060] The No.1 pin of the transistor Q7 and the No.1 pin of the transistor Q10 are used for receiving an A2 / 6 driving signal, the No.2 pin of the transistor Q7 and the No.2 pin of the transistor Q10 are grounded, and the No.3 pin of the transistor Q7 is electrically connected with the output side of the third optocoupler;

[0061] The anode of the reverse isolation diode D5 is used for receiving a power supply voltage, the cathode of the reverse isolation diode D5 is electrically connected with the No.2 pin of the transistor Q8, and the cathode of the reverse isolation diode D5 is further electrically connected with a first A2_HS high side switch after receiving the power supply voltage;

[0062] The No.1 pin of the transistor Q8 is electrically connected with the input side of the third optocoupler, the No.3 pin of the transistor Q8 is connected with the anode of the reverse isolation diode D6, the cathode of the reverse isolation diode D6 is connected with the No.2 pin of the transistor Q9, the cathode of the reverse isolation diode D6 is further connected with a second A2_HS high side switch, and the No.1 pin and the No.3 pin of the transistor Q9 are electrically connected with a third A2_HS high side switch.

[0063] The third driving circuit of the embodiment further comprises a transistor Q11, a transistor Q12, a reverse isolation diode D7, a reverse isolation diode D8, a fourth optocoupler;

[0064] The No.3 pin of the transistor Q10 is electrically connected with the output side of the fourth optocoupler, and the No.1 pin of the transistor Q11 is electrically connected with the input side of the fourth optocoupler;

[0065] The anode of the reverse isolation diode D7 is used for receiving a power supply voltage, the cathode of the reverse isolation diode D7 is electrically connected with the No.2 pin of the transistor Q10, and the cathode of the reverse isolation diode D7 generates an A3 / 6_PW signal after receiving the power supply voltage, and the cathode of the reverse isolation diode D7 is further electrically connected with a first A3 / 6_HS high side switch while generating the signal;

[0066] The No.3 pin of the transistor Q11 is connected with the anode of the reverse isolation diode D4, the cathode of the reverse isolation diode D8 is electrically connected with the No.2 pin of the transistor Q12 through an A6_HS high side switch, and the No.1 pin and the No.3 pin of the transistor Q12 are electrically connected with a second A3 / 6_HS high side switch.

[0067] The fourth driving circuit of the embodiment comprises a transistor Q13, a transistor Q14, a transistor Q15, a transistor Q16, a reverse isolation diode D9, a fifth optocoupler;

[0068] The No.1 pin of the transistor Q13 is used for receiving an A3 / 5 driving signal, the No.2 pin of the transistor Q13 and the No.2 pin of the transistor Q16 are grounded, and the No.3 pin of the transistor Q13 is electrically connected with the output side of the fourth optical coupler;

[0069] The No.1 pin of the transistor Q14 is electrically connected with the input side of the fifth optical coupler, the No.2 pin of the transistor Q14 is used for receiving an A3 / 6_PW signal and is electrically connected with a first A3 / 6_HS high side switch;

[0070] The No.3 pin of the transistor Q14 is connected with the anode of the reverse isolation diode D9, the cathode of the reverse isolation diode D9 is connected with the No.2 pin of the transistor Q16, and the No.1 pin and the No.3 pin of the transistor Q16 are electrically connected with a second A3 / 6_HS high side switch.

[0071] The fourth driving circuit of the embodiment further comprises a transistor Q17, a transistor Q18, a reverse isolation diode D10, a reverse isolation diode D11, a sixth optical coupler;

[0072] The No.3 pin of the transistor Q16 is electrically connected with the output side of the sixth optical coupler, and the No.1 pin of the transistor Q17 is electrically connected with the input side of the fourth optical coupler;

[0073] The anode of the reverse isolation diode D10 is used for receiving an A3 / 6_PW, the cathode of the isolation diode D10 is electrically connected with the No.2 pin of the transistor Q17, and the cathode of the isolation diode D10 is further electrically connected with a first A5_HS high side switch and the No.2 pin of the transistor Q17;

[0074] The No.3 pin of the transistor Q16 is connected with the anode of the reverse isolation diode D11, and the cathode of the reverse isolation diode D11 is electrically connected with the No.2 pin of the transistor Q18 and a second A5_HS high side switch;

[0075] The No.1 pin and the No.3 pin of the transistor Q18 are electrically connected with a third A5_HS high side switch.

[0076] The utility model is not limited to the above-mentioned embodiment, any person should know that the structural change made under the enlightenment of the utility model, any technical scheme with the same or similar technical scheme of the utility model falls into the protection scope of the utility model. The utility model is not described in detail, and the technical, shape and structure parts are all known technologies.

Claims

1. A bootstrap drive module based on a three-level circuit topology, characterized by, Comprise: The first drive circuit, the second drive circuit, the third drive circuit, the fourth drive circuit, the second drive circuit and the first drive circuit, the third drive circuit, the fourth drive circuit are signal connected, the first drive circuit and the fourth drive circuit are all receiving the signal of the third drive circuit.

2. A bootstrap drive module based on three-level circuit topology according to claim 1, characterized in that, The first drive circuit includes triode Q1, triode Q2, triode Q3, reverse isolation diode D1, reverse isolation diode D2, first optical coupler, the No.1 pin of triode Q1 is used for receiving A1 drive signal, the No.2 pin of triode Q1 is grounded, the No.3 pin of triode Q1 and the output side of first optical coupler are electrically connected; The anode of reverse isolation diode D1 is used for receiving power supply voltage, the cathode of isolation diode D1 and the No.2 pin of triode Q2 are electrically connected and after receiving power supply voltage, the first A1_HS high side switch is further electrically connected; The No.1 pin of triode Q2 and the input side of first optical coupler are electrically connected, the No.3 pin of triode Q2 and the anode of reverse isolation diode D2 are connected; The cathode of reverse isolation diode D2 and the No.2 pin of triode Q3 are connected, the cathode of reverse isolation diode D6 and the No.2 pin of triode Q9 are further connected with the second A1_HS high side switch; The No.1 pin and No.3 pin of triode Q3 are electrically connected with the third A1_HS high side switch.

3. The bootstrap drive module based on three-level circuit topology according to claim 1, characterized in that, The second drive circuit further includes triode Q4, triode Q5, triode Q6, reverse isolation diode D4, second optical coupler; The No.1 pin of triode Q4 is used for receiving A4 drive signal, the No.2 pin of triode Q4 is grounded, the No.3 pin of triode Q4 and the output side of second optical coupler are electrically connected; The No.2 pin of triode Q5 is used for receiving to ground after receiving power supply voltage, the No.1 pin of triode Q5 and the input side of second optical coupler are electrically connected; The No.3 pin of triode Q5 and the anode of reverse isolation diode D4 are connected, the cathode of reverse isolation diode D4 and the No.2 pin of triode Q6 are connected, the cathode of reverse isolation diode D4 and the No.2 pin of triode Q6 are further connected with A4_HS high side switch, the No.1 pin and No.3 pin of triode Q6 are used for grounding.

4. The bootstrap drive module based on three-level circuit topology according to claim 1, characterized in that, The third drive circuit includes triode Q7, triode Q8, triode Q9, triode Q10, reverse isolation diode D5, reverse isolation diode D6, third optical coupler; The No.1 pin of triode Q7 and triode Q10 are both used for receiving A2 / 6 drive signal, the No.2 pin of triode Q7 and triode Q10 are both grounded, the No.3 pin of triode Q7 and the output side of third optical coupler are electrically connected; The anode of reverse isolation diode D5 is used for receiving power supply voltage, the cathode of isolation diode D5 and the No.2 pin of triode Q8 are electrically connected and after receiving power supply voltage, the first A2_HS high side switch is further electrically connected; The No. 1 pin of the triode Q8 is electrically connected with the input side of the third optical coupler, the No. 3 pin of the triode Q8 is connected with the anode of the reverse isolation diode D6, the cathode of the reverse isolation diode D6 is connected with the No. 2 pin of the triode Q9, and the cathode of the reverse isolation diode D6 is also connected with the No. 2 pin of the triode Q9 through the second A2_HS high side switch, and the No. 1 pin and the No. 3 pin of the triode Q9 are electrically connected with the third A2_HS high side switch.

5. The bootstrap drive module based on three-level circuit topology according to claim 1, characterized in that, The third drive circuit further comprises a triode Q11, a triode Q12, a reverse isolation diode D7, a reverse isolation diode D8 and a fourth optical coupler; The No. 3 pin of the triode Q10 is electrically connected with the output side of the fourth optical coupler, and the No. 1 pin of the triode Q11 is electrically connected with the input side of the fourth optical coupler; The anode of the reverse isolation diode D7 is used for receiving a power supply voltage, the cathode of the reverse isolation diode D7 is electrically connected with the No. 2 pin of the triode Q10 and generates an A3 / 6_PW signal after receiving the power supply voltage, and the cathode of the reverse isolation diode D7 is also electrically connected with the first A3 / 6_HS high side switch when the signal is generated; The No. 3 pin of the triode Q11 is connected with the anode of the reverse isolation diode D4, the cathode of the reverse isolation diode D8 is electrically connected with the No. 2 pin of the triode Q12 through the A6_HS high side switch, and the No. 1 pin and the No. 3 pin of the triode Q12 are electrically connected with the second A3 / 6_HS high side switch.

6. The bootstrap drive module based on three-level circuit topology according to claim 1, characterized in that, The fourth drive circuit comprises a triode Q13, a triode Q14, a triode Q15, a triode Q16, a reverse isolation diode D9 and a fifth optical coupler; The No. 1 pin of the triode Q13 is used for receiving an A3 / 5 drive signal, the No. 2 pin of the triode Q13 and the No. 2 pin of the triode Q16 are grounded, and the No. 3 pin of the triode Q13 is electrically connected with the output side of the fourth optical coupler; The No. 1 pin of the triode Q14 is electrically connected with the input side of the fifth optical coupler, and the No. 2 pin of the triode Q14 is used for receiving an A3 / 6_PW signal and is electrically connected with the first A3 / 6_HS high side switch; The No. 3 pin of the triode Q14 is connected with the anode of the reverse isolation diode D9, the cathode of the reverse isolation diode D9 is connected with the No. 2 pin of the triode Q16, and the No. 1 pin and the No. 3 pin of the triode Q16 are electrically connected with the second A3 / 6_HS high side switch.

7. The bootstrap drive module based on three-level circuit topology according to claim 1, characterized in that, The fourth drive circuit further comprises a triode Q17, a triode Q18, a reverse isolation diode D10, a reverse isolation diode D11 and a sixth optical coupler; The No. 3 pin of the triode Q16 is electrically connected with the output side of the sixth optical coupler, and the No. 1 pin of the triode Q17 is electrically connected with the input side of the fourth optical coupler; The anode of the reverse isolation diode D10 is used for receiving an A3 / 6_PW, the cathode of the reverse isolation diode D10 is electrically connected with the No. 2 pin of the triode Q17, and the cathode of the reverse isolation diode D10 is also electrically connected with the first A5_HS high side switch between the cathode of the reverse isolation diode D10 and the No. 2 pin of the triode Q17; The pin 3 of the triode Q16 and the anode of the reverse isolation diode D11 are connected, and the cathode of the reverse isolation diode D11 and the pin 2 of the triode Q18 are electrically connected with the second A5_HS high side switch; The pin 1 and the pin 3 of the triode Q18 are electrically connected with the third A5_HS high side switch.

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