Millimeter wave high-voltage high-power low-noise amplifier
By employing a combination of E-mode and D-mode transistors in a low-noise amplifier, the problem of limited voltage output was solved, enabling high-power output at higher bias voltages and improved temperature stability.
Patent Information
- Application Number
- CN202520091985.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-15
- Publication Date
- 2025-12-30
- Estimated Expiration
- 2035-01-15
AI Technical Summary
In existing low-noise amplifiers, the drain-source breakdown voltage of E-mode transistors is relatively low, which limits the voltage output of two-stage current-reused structures and single-stage common-source structures, making it difficult to output greater power at higher bias voltages.
E-mode transistors are used in the two-stage current multiplexing structure, and D-mode transistors are used in the final stage single-stage common-source structure. Combined with input matching network, gate bias and drain bias design, the voltage swing and temperature stability of the transistors are improved.
This resulted in a low-noise amplifier that outputs greater power at higher bias voltages, improved the voltage swing and temperature stability of the final stage, and achieved good noise performance and linearity.
Smart Images
Figure CN223744681U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to millimeter wave radio frequency integrated technical field, concretely relates to a millimeter wave high voltage high power low noise amplifier. BACKGROUND
[0002] At present, the transistor of two-stage current multiplexing structure and single-stage common source structure in low noise amplifier adopts E-mode transistor to obtain better noise performance. The voltage swing of E-mode transistor in two-stage current multiplexing structure is limited when two E-mode transistors are divided in two-stage current multiplexing structure. At this time, if the transistor of single-stage common source structure also adopts E-mode transistor, the voltage output will be greatly limited. SUMMARY
[0003] The utility model discloses a kind of millimeter wave high voltage high power low noise amplifiers, E-mode transistor is used to obtain good noise performance to the two-stage current multiplexing structure located in front, simultaneously, D-mode transistor is used to obtain better temperature stability and linearity to the single-stage common source structure located in final stage, can work output greater power under higher bias.
[0004] To solve the above technical problems, the utility model adopts the following scheme:
[0005] A kind of millimeter wave high voltage high power low noise amplifier, it includes input port, two-stage current multiplexing structure, single-stage common source structure, output port connected in turn;
[0006] The two-stage current multiplexing structure includes input matching network, first transistor, one-two interstage matching network, second transistor connected in turn, and the single-stage common source structure includes two-three interstage matching network, third transistor, output matching network connected in turn;
[0007] The gate of the first transistor is connected with input matching network, the one-two interstage matching network is connected between the drain of the first transistor and the gate of the second transistor, and the current multiplexing direct current path is further connected between the drain of the first transistor and the source of the second transistor, the two-three interstage matching network is connected between the drain of the second transistor and the gate of the third transistor, and the drain of the third transistor is connected with output matching network;
[0008] The first transistor and the second transistor are E-mode transistor, and the third transistor is D-mode transistor.
[0009] Further, a first-stage gate bias is arranged on the gate of the first transistor, and the first-stage gate bias is located between the gate of the first transistor and an input matching network.
[0010] Further, a second-stage gate bias is arranged on the gate of the second transistor, and the second-stage gate bias is located between a two-stage matching network and the gate of the second transistor.
[0011] Further, a first stabilizing network is arranged between the second-stage gate bias and the gate of the second transistor.
[0012] Further, a second-stage drain bias is arranged on the drain of the second transistor, and the second-stage drain bias is connected to a three-stage matching network.
[0013] Further, a second stabilizing network is arranged between the three-stage matching network and the gate of the third transistor.
[0014] Further, a third-stage drain bias is arranged on the drain of the third transistor, and the third-stage drain bias is connected to an output matching network, and a self-bias circuit is arranged on the source of the third transistor.
[0015] The millimeter wave high-voltage high-power low-noise amplifier has the advantages that:
[0016] The millimeter wave high-voltage high-power low-noise amplifier has the advantages that:
[0017] In addition, the two-stage current multiplexing structure in front is arranged with an E-mode transistor to obtain good noise performance, and the single-stage common-source structure in the last stage is arranged with a D-mode transistor to obtain better temperature stability and linearity, so that the D-mode transistor can work at a higher bias voltage to output greater power. BRIEF DESCRIPTION OF DRAWINGS
[0018] Figure 1 FIG. 1 is a structural schematic diagram of a millimeter wave high-voltage high-power low-noise amplifier according to an embodiment of the present application.
[0019] Figure 2 FIG. 2 is a module schematic diagram of the millimeter wave high-voltage high-power low-noise amplifier according to the embodiment of the present application.
[0020] Figure 3 FIG. 3 is a circuit schematic diagram of the millimeter wave high-voltage high-power low-noise amplifier according to the embodiment of the present application. DETAILED DESCRIPTION
[0021] To enable those skilled in the art to better understand the technical solution of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments, but the embodiments of this utility model are not limited thereto.
[0022] In the description of this utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "longitudinal", "lateral", "horizontal", "inner", "outer", "front", "rear", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the utility model product is in use. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0023] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "have," "install," "connect," and "connect" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0024] The present invention will now be described in detail with reference to the accompanying drawings and embodiments:
[0025] Example 1
[0026] In this embodiment, as Figure 1 As shown, a millimeter-wave high-voltage high-power low-noise amplifier includes an input port, a two-stage current multiplexing structure, a single-stage common-source structure, and an output port connected in sequence. The two-stage current multiplexing structure at the front stage uses two cascaded voltage divider E-mode transistors to achieve good noise performance. Meanwhile, the single-stage common-source structure at the last stage uses a D-mode transistor to achieve better temperature stability and linearity, and can output more power at higher bias voltages.
[0027] The voltage of the D-mode transistor is higher than that of the E-mode transistor, and the maximum absolute drain-source voltage that a single E-mode transistor can withstand is +5V, provided that the E-mode transistor is a gallium arsenide high electron mobility transistor, i.e., GaAs pHEMT. When both transistors in the two-stage current reuse structure are E-mode transistors, if an E-mode transistor is selected for use in the single-stage common-source structure, the drain-source voltage can only be +5V, resulting in limited output. If a D-mode transistor is selected for use in the single-stage common-source structure, the voltage swing can be further improved.
[0028] As shown in Figure 2 The two-stage current reuse structure includes, in sequence, an input matching network, a first-stage gate bias, a first transistor, an inter-stage matching network, a second-stage gate bias, a first stabilization network, and a second transistor. A current reuse DC path is further arranged between the first transistor and the second transistor. In this case, both the first transistor and the second transistor are E-mode transistors.
[0029] Specifically, the input matching network and the first-stage gate bias are connected to the gate of the first transistor, a source feedback is arranged on the source of the first transistor, the drain of the first transistor is sequentially connected to the inter-stage matching network, the second-stage gate bias, the first stabilization network, and the gate of the second transistor, the source of the second transistor is connected to the current reuse DC path and is connected to the drain of the first transistor through the current reuse DC path to provide a drain DC bias for the first transistor. The current reuse DC path is located between the drain of the first transistor and the source of the second transistor. The drain of the second transistor is further connected to the second-stage drain bias.
[0030] The single-stage common-source structure includes, in sequence, an inter-stage matching network, a second-stage drain bias, a second stabilization network, and a third transistor. In this case, the third transistor is a D-mode transistor.
[0031] Specifically, the second-stage drain bias is connected to the inter-stage matching network, the drain of the second transistor is connected to the inter-stage matching network, the drain of the second transistor is sequentially connected to the inter-stage matching network, the second-stage drain bias, the second stabilization network, and the gate of the third transistor, a self-bias circuit is arranged on the source of the third transistor, the drain of the third transistor is connected to the output matching network, and the drain of the third transistor is further provided with a third-stage drain bias connected to the output matching network.
[0032] As shown in Figure 3As shown, the input port Rfin is connected to an input matching network, which is composed of a capacitor C1 and a microstrip line TL1 connected in sequence, and an open-circuit microstrip line TL2 is connected between the capacitor C1 and the microstrip line TL1, the first-stage gate bias is composed of a microstrip line TL3, a capacitor C2 and a port VG1, the input port Rfin is connected to the capacitor C1, a connection point between the microstrip line TL1 and the microstrip line TL3 is connected to the gate of a first transistor T1, the microstrip line TL3 is connected to the port VG1 and the capacitor C2, and the capacitor C2 is grounded.
[0033] The source feedback comprises a microstrip line TL4, one end of which is connected to the source of the first transistor, and the other end of which is grounded.
[0034] The inter-stage matching network between the first stage and the second stage comprises a microstrip line TL5, a capacitor C3 and a microstrip line TL6 connected in sequence, the drain of the first transistor is connected to the microstrip line TL5, and a capacitor C4 is further connected between the capacitor C3 and the microstrip line TL6, and the capacitor C4 is grounded.
[0035] The second-stage gate bias comprises a resistor R1 and a port VG2 connected in sequence, the resistor R1 is connected to the microstrip line TL6, and a capacitor C5 is connected between the resistor R1 and the port VG2, and the capacitor C5 is grounded.
[0036] The first stabilizing network is composed of two branches connected in parallel, one of which is provided with a capacitor C6, and the other of which is provided with a microstrip line TL7 and a resistor R2 connected in sequence, the microstrip line TL7 and the capacitor C6 are connected in parallel to a connection point between the microstrip line TL6 and the resistor R1, and the resistor R2 and the capacitor C6 are connected in parallel to the gate of a second transistor.
[0037] The current multiplexing direct current path comprises a microstrip line TL8 and a microstrip line TL9 connected in sequence, the microstrip line TL9 is connected between the microstrip line TL5 and the capacitor C3, and a capacitor C7 is connected between the microstrip line TL8 and the microstrip line TL9, and the capacitor C7 is grounded.
[0038] The inter-stage matching network between the second stage and the third stage comprises a microstrip line TL10, a microstrip line TL11, a capacitor C8, a microstrip line TL12, a microstrip line TL13 and a resistor R3 connected in sequence, a capacitor C9 is connected between the capacitor C8 and the microstrip line TL12, the capacitor C9 is grounded, and the resistor R3 is grounded.
[0039] The second-stage drain bias comprises a microstrip line TL14 and a port VD2 connected in sequence, the microstrip line TL14 is connected to the microstrip line TL10 and the microstrip line TL11, so that the second-stage drain bias is connected to the inter-stage matching network between the second stage and the third stage, and a resistor R4 and a capacitor C10 are further connected in sequence between the microstrip line TL14 and the port VD2, and the capacitor C10 is grounded.
[0040] The second stable network is the same structure as the first stable network, and is composed of two parallel paths, one of which is provided with a capacitor C11, and the other of which is provided with a microstrip line TL15 and a resistor R5 connected in sequence, the microstrip line TL15 and the capacitor C11 are connected in parallel to the connecting point between the microstrip line TL12 and the microstrip line TL13, and the resistor R5 and the capacitor C11 are connected in parallel to the gate of the third transistor.
[0041] The source of the third transistor is connected with a microstrip line TL16 and a self-bias circuit in sequence, the self-bias circuit is composed of a resistor R6 and a capacitor C12 connected in parallel, and the self-bias circuit is grounded.
[0042] The output matching network includes a microstrip line TL17, a microstrip line TL18, and a capacitor C13 connected in sequence, an open-circuit microstrip line TL19 is connected between the microstrip line TL18 and the capacitor C13, the third gate-drain bias includes a microstrip line TL20 and a port VD3 connected in sequence, a resistor R7 and a capacitor C14 are connected in sequence between the microstrip line TL20 and the port VD3, the capacitor C14 is grounded, the third gate-drain bias is connected to the output matching network, and the capacitor C13 is connected to the output port Rfout.
[0043] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present application, and these modifications and improvements are also regarded as the protection scope of the present application.
Claims
1. A millimeter wave high voltage high power low noise amplifier, characterized by, The input port, two-stage current multiplexing structure, single-stage common source structure and output port are connected in sequence. The two-stage current multiplexing structure comprises an input matching network, a first transistor, a first-second-stage matching network and a second transistor connected in sequence, and the single-stage common source structure comprises a second-third-stage matching network, a third transistor and an output matching network connected in sequence. The gate of the first transistor is connected to the input matching network, the first-second-stage matching network is connected between the drain of the first transistor and the gate of the second transistor, a current multiplexing direct current path is further connected between the drain of the first transistor and the source of the second transistor, the second-third-stage matching network is connected between the drain of the second transistor and the gate of the third transistor, and the drain of the third transistor is connected to the output matching network. The first transistor and the second transistor are E-mode transistors, and the third transistor is a D-mode transistor.
2. The millimeter wave high-voltage high-power low-noise amplifier according to claim 1, wherein, A first-stage gate bias is arranged on the gate of the first transistor, and the first-stage gate bias is located between the gate of the first transistor and the input matching network.
3. The millimeter wave high-voltage high-power low-noise amplifier according to claim 1, wherein, A source feedback is arranged on the source of the first transistor.
4. The millimeter wave high-voltage high-power low-noise amplifier according to claim 3, characterized in that, A second-stage gate bias is arranged on the gate of the second transistor, and the second-stage gate bias is located between the first-second-stage matching network and the gate of the second transistor.
5. The millimeter wave high-voltage high-power low-noise amplifier according to claim 1, wherein, A first stabilizing network is further arranged between the second-stage gate bias and the gate of the second transistor.
6. The millimeter wave high-voltage high-power low-noise amplifier according to claim 5, wherein, A second-stage drain bias is arranged on the drain of the second transistor, and the second-stage drain bias is connected to the second-third-stage matching network.
7. The millimeter wave high-voltage high-power low-noise amplifier according to claim 1, wherein, A second stabilizing network is arranged between the second-third-stage matching network and the gate of the third transistor. A third-stage drain bias is arranged on the drain of the third transistor, and the third-stage drain bias is connected to the output matching network. A self-biasing circuit is arranged on the source of the third transistor.