Silicon wafer, battery piece and photovoltaic module

Abstract

The utility model discloses a silicon wafer, a battery piece and a photovoltaic module, relates to the technical field of silicon wafer manufacturing, and is used for solving the problem that a conductive interconnection piece slides on the battery piece. The silicon wafer is provided with a first surface, a second surface and a side surface, the first surface and the second surface are opposite, the side surface is positioned between the first surface and the second surface, the silicon wafer is provided with at least one groove, the groove is formed inwards from the side surface and penetrates through the first surface and the second surface, the groove is provided with a plurality of first grooves, and the first grooves extend along the direction from the first surface to the second surface. When a battery piece prepared by the silicon wafer is connected with a conductive interconnection piece in series, the conductive interconnection piece penetrates through the groove, and the extension direction of the conductive interconnection piece is basically parallel to the extension direction of the first groove; and meanwhile, the edge of the conductive interconnection piece is in contact with the first groove, and the first groove and the conductive interconnection piece can limit the conductive interconnection piece from sliding in the groove along the length direction of the side surface due to the friction resistance, so that the alignment precision of the conductive interconnection piece when the conductive interconnection piece is connected with the battery piece is improved.

Description

Technical Field

[0001] This utility model relates to the field of silicon wafer manufacturing technology, and in particular to a silicon wafer, a solar cell, and a photovoltaic module. Background Technology

[0002] In traditional photovoltaic (PV) modules, each cell is connected in series via a conductive interconnect, linking the negative terminal of one cell to the positive terminal of the next. This results in gaps between cells due to the thickness of the interconnect. As customers increasingly demand higher module efficiency, reducing the gaps between cells to increase the module's light-receiving area and thus improve efficiency has become a viable solution. To reduce these gaps, existing solutions incorporate grooves on either side or one side of the cell's connection point for the conductive interconnect to pass through.

[0003] Since the conductive interconnect needs to connect multiple solar cells, the conductive interconnect will slide along the silicon wafer surface during the string bonding of the conductive interconnect to the solar cells, affecting the alignment accuracy of the conductive interconnect. Utility Model Content

[0004] The purpose of this invention is to provide a silicon wafer, a solar cell, and a photovoltaic module to reduce the slippage of conductive interconnects on the surface of the solar cell.

[0005] In a first aspect, the present invention provides a silicon wafer having a first side and a second side opposite to each other and a side side located between the first side and the second side. The silicon wafer has at least one groove, which is opened inward from the side side and penetrates the first side and the second side. The groove has a plurality of first grooves, which extend along the direction of the first side to the second side.

[0006] In the case of the above technical solution, the silicon wafer has at least one groove, and the groove has multiple first trenches extending along the direction from the first surface to the second surface. When a solar cell fabricated from such a silicon wafer is connected in series with a conductive interconnect, the conductive interconnect passes through the groove, and the extension direction of the conductive interconnect is substantially parallel to the extension direction of the first trench, allowing the conductive interconnect to extend along the direction of the first trench. Simultaneously, the edge of the conductive interconnect contacts the first trench, and due to frictional resistance, the conductive interconnect can be restricted from sliding along its length within the groove, thereby improving the alignment accuracy of the conductive interconnect when connected to the solar cell.

[0007] In some possible implementations, the spacing of the first trench is 0.05 μm to 1 μm; and / or, the depth of the first trench is 0.01 μm to 2 μm. If the spacing of the first trench is less than 0.05 μm, the denser the arrangement of the first trenches within the groove, the more it affects the mechanical strength of the silicon wafer. If the spacing of the first trench is greater than 1 μm, there are too few first trenches within the groove, resulting in less frictional resistance to the conductive interconnects and hindering the restriction of the conductive interconnects' slippage within the groove. Therefore, the spacing of the first trench is chosen to be 0.05 μm to 1 μm. If the depth of the first trench is less than 0.01 μm, the frictional resistance to the conductive interconnects is less. If the depth of the first trench is greater than 2 μm, it affects the mechanical strength of the silicon wafer. Therefore, the depth of the first trench is chosen to be 0.01 μm to 2 μm.

[0008] In some possible implementations, the groove includes a first arc and two second arcs, the two second arcs being located on opposite sides of the first arc and both connecting the first arc to the side of the silicon wafer, and the radius of the first arc being greater than or equal to the radius of the second arcs.

[0009] With the above technical solution, the groove is composed of a first circular arc and two second circular arcs on both sides, which makes the groove area smooth and more reasonably disperses the stress concentration that may be experienced during processing, reducing the probability of hidden cracks and fragments at the groove.

[0010] In some possible implementations, the radius R1 of the first arc is 0.5mm ≤ R1 ≤ 1mm, and the radius R2 of the second arc is 0.3mm ≤ R2 ≤ 0.5mm. The radius of the first arc is large enough to accommodate the conductive interconnects without causing excessive movement, allowing for precise positioning of the interconnects. Furthermore, the radius of the first arc within this range maintains the mechanical strength of the silicon wafer. The radius of the second arc is less than or equal to the radius of the first arc, enabling a smooth transition between the first arc and its surrounding side, reducing the wafer breakage rate.

[0011] In some possible implementations, the radian a1 of the first arc is: 1 / 2π ≤ a1 ≤ π, and the radian a2 of the second arc is: 0 < a2 ≤ 1 / 2π. That is, the central angle of the first arc is 90°–180°, which is beneficial for accommodating conductive interconnects and for frictionally limiting the conductive interconnects on both sides. If the central angle is less than 90°, the groove walls of the first arc are located below the conductive interconnects on both sides, failing to effectively limit the conductive interconnects. If the central angle is greater than 180°, the opening of the groove is small, which is not conducive to the conductive interconnects passing through the groove. The central angle of the second arc is greater than zero degrees and less than or equal to 90°, which is beneficial for forming a smooth groove shape with the first arc, avoiding stress concentration and reducing the risk of fragmentation and microcracks.

[0012] In some possible implementations, the first arc and / or the second arc have a first groove, the extension direction of which is perpendicular to the first surface.

[0013] When the above technical solution is adopted, the extension direction of the first groove on the first arc and / or the second arc is perpendicular to the first surface. Since the conductive interconnect passes through the groove in a direction perpendicular to the first surface, the first groove of the first arc and / or the second arc is basically parallel to the extension direction of the conductive interconnect. The edge of the conductive interconnect can make parallel contact with the first groove on the second arc, so that the first groove has a locking and limiting effect on the conductive interconnect. Frictional resistance is generated between the conductive interconnect surface near the inside of the groove and the first groove. Since the conductive interconnect is parallel to the first groove, there is a large frictional resistance in the length direction of the side of the groove (i.e., the direction perpendicular to the first groove), which is more conducive to restricting the conductive interconnect from sliding in the groove along the length direction of the side of the groove.

[0014] In some possible implementations, the side of the silicon wafer has a second trench, the extension direction of which forms an angle of less than 90° with the first surface.

[0015] When the above technical solution is adopted, the angle between the second groove on the side of the silicon wafer and the first surface is less than 90°, that is, there is an angle between the second groove on the side of the silicon wafer and the extension direction of the conductive interconnect. After the first groove on the second arc limits the conductive interconnect, if the conductive interconnect is offset, the friction of the conductive interconnect on the side of the silicon wafer will increase, further restricting the slippage of the conductive interconnect. Therefore, in order to facilitate the conductive interconnect to pass through the groove from the outside during the string bonding process, when the conductive interconnect passes through the side of the silicon wafer, the second groove on the side of the silicon wafer further limits the conductive interconnect, making it easier for the conductive interconnect to slide into the first arc, reducing the risk of getting stuck outside the groove, and improving the efficiency of string bonding.

[0016] In some possible implementations, the width of each groove on the side is 1mm to 1.5mm. This allows the conductive interconnect to pass through the groove, and the first groove on the groove limits the two sides of the conductive interconnect. If the width is less than 1mm, the conductive interconnect cannot fully enter the groove. If the width is greater than 1.5mm, it increases the space for the conductive interconnect to wobble in the groove, which is not conducive to accurate positioning. Therefore, the width of the groove is chosen to be 1mm to 1.5mm.

[0017] And / or, the depth of each groove is 0.5mm to 1mm; the depth of the groove is greater than the thickness of the conductive interconnect at the groove location. If the groove depth is less than 0.5mm, it is not conducive to the conductive interconnect being embedded in the groove, causing the conductive interconnect to protrude from the edge of the silicon wafer. During the assembly lamination, the conductive interconnect is prone to squeezing the edge of the silicon wafer, causing microcracks or fragments in the silicon wafer. If the groove depth is greater than 1mm, it affects the mechanical strength of the silicon wafer. Therefore, the width of the groove is selected to be 0.5mm to 1mm.

[0018] And / or, the distance between the grooves is 9mm to 10mm. The groove spacing is determined based on the overall size of the silicon wafer and the number of conductive interconnects. If the distance between the grooves is less than 9mm, there are too many grooves, which affects the mechanical strength of the silicon wafer; if the distance between the grooves is greater than 10mm, there are too few grooves, which means that some conductive interconnects do not have corresponding grooves to pass through, which is not conducive to reducing the spacing between the cells.

[0019] In some possible implementations, the surface roughness of the groove is 0.08 to 1.2. If the roughness is less than 0.08, the conductive interconnects are more likely to slip within the groove. If the roughness is greater than 1.2, the stress within the groove is too high, the mechanical strength is lower, and microcracks or fragmentation are more likely to occur. Therefore, the surface roughness of the groove is selected to be 0.08 to 1.2.

[0020] Secondly, this utility model also provides a battery cell, comprising a silicon wafer, wherein the silicon wafer is as described in any of the above claims. Since this battery cell uses the silicon wafer described in any of the above claims, it has the same beneficial effects as the silicon wafer, and will not be elaborated further.

[0021] Thirdly, this utility model also provides a photovoltaic module, including at least two solar cells and at least one conductive interconnect. The solar cells are as described above, and the conductive interconnect connects two adjacent solar cells, passing through a groove. Since this photovoltaic module uses the solar cells described above, it has the same beneficial effects as the solar cells, and will not be described again.

[0022] In some possible implementations, the portion of the conductive interconnect that passes through the groove is flat, with a thickness of 0.07 mm to 0.14 mm and a width of 0.52 mm to 0.587 mm. Thus, the thickness and width of the conductive interconnect are both less than the depth and width of the groove, allowing the conductive interconnect to be embedded within the groove, reducing the spacing between the battery cells. Furthermore, the groove can limit the movement of the conductive interconnect, reducing slippage and improving positioning accuracy.

[0023] In some possible implementations, the conductive interconnect spans 100 to 600 first trenches at the location where it crosses the groove. By contacting these spanning first trenches, the conductive interconnect increases the resistance to sliding within the groove, thus better limiting its movement. If the number of spanning first trenches exceeds 600, there will be too many first trenches within the groove, affecting the mechanical strength of the silicon wafer. Therefore, the number of spanning first trenches is limited to 100 to 600. Attached Figure Description

[0024] The accompanying drawings, which are included to provide a further understanding of the present invention and constitute a part of this invention, illustrate exemplary embodiments of the present invention and, together with the description thereof, serve to explain the present invention and do not constitute an undue limitation thereof. In the drawings:

[0025] Figure 1 An enlarged schematic diagram of a groove in a silicon wafer provided for an embodiment of this utility model;

[0026] Figure 2 for Figure 1 A top view of the second arc on the left side of the groove and the side of the silicon wafer;

[0027] Figure 3 for Figure 1 A top view of a portion of the first circular arc of the groove in the diagram;

[0028] Figure 4 for Figure 1 A top view of the second arc on the right side of the groove and the side of the silicon wafer;

[0029] Figure 5 This is a schematic diagram of the arrangement of multiple silicon wafers in this utility model;

[0030] Figure 6 This is a partial structural diagram of a photovoltaic module composed of battery cells according to this utility model.

[0031] Reference numerals: 1 for groove, 11 for first arc, 12 for second arc, 13 for first groove, 2 for side surface, 21 for second groove, 3 for battery cell, 4 for conductive interconnect. Detailed Implementation

[0032] To make the technical problems, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0033] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0035] In the description of this utility model, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0036] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0037] Please refer to Figures 1-4 and Figure 6 This utility model provides a silicon wafer having a first surface and a second surface facing each other, and a side surface 2 located between the first surface and the second surface. The side surface 2 is a narrow, elongated side surface. The silicon wafer has at least one groove 1, which is opened inward from the side surface 2 and penetrates the first surface and the second surface. The groove 1 has a plurality of first grooves 13, which extend along the direction from the first surface to the second surface. The first grooves 13 can be ridge grooves at the microscopic level. A first groove 13 can be a continuous ridge groove or a partially discontinuous ridge groove at the microscopic level. The first grooves 13 generally extend between the first surface and the second surface facing each other.

[0038] Because the silicon wafer has a groove 1 with multiple first trenches 13 extending along the direction from the first surface to the second surface, when a solar cell made from such a silicon wafer is connected in series with a conductive interconnect 8, the conductive interconnect 4 passes through the groove 1. The extension direction of the conductive interconnect 4 is substantially parallel to the extension direction of the first trenches 13, allowing the conductive interconnect 4 to extend along the direction of the first trenches 13. Simultaneously, the edge of the conductive interconnect 4 contacts the first trenches 13, generating frictional resistance between them. Furthermore, the edge of the conductive interconnect 4 can also make limiting contact with the corresponding first trench 13, which acts as a limiting element, restricting the conductive interconnect 4 from sliding along the length of the side of the groove 1 within the groove 1. Compared to existing technologies, this reduces the offset by approximately 0.2mm to 0.5mm, thereby improving the alignment accuracy of the conductive interconnect 4 when connected to the solar cell, reducing photovoltaic module power attenuation, and improving the performance of the photovoltaic module.

[0039] In some embodiments, the spacing between adjacent first trenches 13 is 0.05 μm to 1 μm, specifically 0.05 μm, 0.1 μm, 0.2 μm, 0.5 μm, 0.7 μm, 1 μm, etc. If the spacing between the first trenches 13 is less than 0.05 μm, the more first trenches 13 there are in the groove 1, the denser their arrangement, which affects the mechanical strength of the silicon wafer. If the spacing between the first trenches 13 is greater than 1 μm, there are too few first trenches 13 in the groove 1, resulting in a smaller frictional resistance to the conductive interconnect 4, which is not conducive to restricting the sliding of the conductive interconnect 4 in the groove 1. Therefore, considering the effect of restricting the sliding of the conductive interconnect 4 and the mechanical strength of the silicon wafer, the spacing between the first trenches 13 in this embodiment is selected to be 0.05 μm to 1 μm.

[0040] In some embodiments, the depth of the first trench 13 is 0.01 μm to 2 μm, specifically 0.01 μm, 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.7 μm, 2 μm, etc. If the depth of the first trench 13 is less than 0.01 μm, the frictional resistance to the conductive interconnect 4 is small, which is not conducive to restricting the sliding of the conductive interconnect 4 in the groove 1. If the depth of the first trench 13 is greater than 2 μm, it affects the mechanical strength of the silicon wafer. Therefore, considering the effect of restricting the sliding of the conductive interconnect 4 and the mechanical strength of the silicon wafer, the depth of the first trench 13 in this embodiment is selected to be 0.01 μm to 2 μm.

[0041] like Figure 1As shown, in some embodiments, the groove 1 includes a first arc 11 and two second arcs 12. The two second arcs 12 are located on opposite sides of the first arc 11 and are connected between the first arc 11 and the side surface 2 of the silicon wafer. That is, along the length direction of the side surface where the groove 1 is located, the groove 1 includes a second arc 12 on the left, a first arc 11 and a second arc 12 on the right. The first arc 11 is smoothly connected to the side surface where the groove 1 is located through the second arcs 12 on both sides. The first arc 11 and the second arc 12 are both arc-shaped in cross-section parallel to the first surface. The radius of the first arc 11 is greater than or equal to the radius of the second arc 12. The first arc 11 and / or the second arc 12 have a first groove 13.

[0042] With the above technical solution, the groove 1 is composed of a first circular arc 11 and two second circular arcs 12 on both sides, which makes the groove area of ​​the groove 1 smooth and more reasonably disperses the stress concentration that the silicon wafer may be subjected to during the processing, reducing the probability of microcracks and wafer breakage at the groove.

[0043] For example, the radius R1 of the first arc 11 is 0.5mm ≤ R1 ≤ 1mm, specifically 0.5mm, 0.55mm, 0.6mm, 0.75mm, 0.8mm, 0.85mm, 0.9mm, 1mm, etc. The radius R2 of the second arc 12 is 0.3mm ≤ R2 ≤ 0.5mm, specifically 0.3mm, 0.35mm, 0.4mm, 0.45mm, 0.5mm, etc. The dimensions of the second arc 12 on the left and the second arc 12 on the right can be the same or different. If they are the same, they can be processed using the same process, simplifying the process. The first arc 11 within this radius range can accommodate the conductive interconnect 4 to pass through without being too large, causing the conductive interconnect 4 to have a large wobbling space. It can position the conductive interconnect 4 in a relatively precise position range, and the radius of the first arc 11 within this range can also take into account the mechanical strength of the silicon wafer. The radius of the second arc 12 is less than or equal to the radius of the first arc 11, which allows the first arc 11 to smoothly transition and connect with the side surface, reducing the breakage rate of the silicon wafer and improving mechanical strength. The smaller size of the second arc 12 saves processing time.

[0044] In some possible implementations, the radian a1 of the first arc 11 is: 1 / 2π ≤ a1 ≤ π, where a1 can specifically be 1 / 2π, 2 / 3π, 3 / 4π, 4 / 5π, π, etc. The radian a2 of the second arc 12 is: 0 < a2 ≤ 1 / 2π, where a2 can specifically be 1 / 6π, 1 / 5π, 1 / 4π, 1 / 3π, 1 / 2π, etc. That is, the central angle of the first arc 11 is 90° to 180°, which is beneficial for accommodating the conductive interconnect 4 and for frictionally limiting the two sides of the conductive interconnect 4. If the central angle of the first arc 11 is less than 90°, the groove wall of the first arc 11 is located below the two sides of the conductive interconnect 4, which cannot effectively limit the conductive interconnect 4. If the central angle of the first arc 11 is greater than 180°, the opening of the groove 1 is small and the bottom of the groove is large, which is not conducive to the conductive interconnect 4 passing through the groove 1. The central angle of the second arc 12 is greater than zero degrees and less than or equal to 90°, which helps to form a smooth groove with the first arc 11, avoid stress concentration, and reduce the risk of fragmentation and hidden cracks.

[0045] like Figures 2-4 As shown, in some embodiments, the first arc 11 and / or the second arc 12 have a first groove 13, the extension direction of the first groove 13 is perpendicular to the first surface, and the plurality of first grooves 13 located on the first arc 11 and / or the second arc 12 are parallel to each other. With the above technical solution, the extension direction of the first groove 13 on the first arc 11 and / or the second arc 12 is perpendicular to the first surface. Since the conductive interconnect 4 passes through the groove 1 in a direction perpendicular to the first surface, the first groove 13 on the first arc 11 and / or the second arc 12 is basically parallel to the extension direction of the conductive interconnect 4. The two side edges of the conductive interconnect 4 can contact the first groove 13 in parallel, so that the first groove 13 has a locking and limiting effect on the conductive interconnect 4. Furthermore, frictional resistance is generated between the surface of the conductive interconnect 4 near the bottom of the groove 1 and the first groove 13. Since the conductive interconnect 4 is parallel to the first groove 13, there is a large frictional resistance in the length direction of the side of the groove 1 (i.e., the left-right direction perpendicular to the first groove 13), which is more conducive to restricting the conductive interconnect 4 from sliding in the groove 1 along the length direction of the side.

[0046] like Figure 2 and Figure 4 As shown, the side surface 2 of the silicon wafer has a second groove 21. The extension direction of the second groove 21 is inclined to the first surface, that is, there is an angle between the second groove 21 on the side surface 2 and the first groove 13 located on the groove 1. The angle is less than 90° and can be 10° to 80°, or even 30° to 60°. Specifically, it can be 30°, 45°, 60°, etc. Figure 2 The second groove 21 located on the side 2 to the left of the groove 1 and Figure 4The second groove 21 located on the side 2 to the right of the groove 1 can be parallel to each other and can be formed by the same grinding process, simplifying the grinding process. Of course, the second groove 21 located on the side 2 to the left of the groove 1 and the second groove 21 located on the side 2 to the right of the groove 1 can not be parallel, such as being symmetrical with respect to the axis of the groove 1 or having different included angles with respect to the first surface.

[0047] When the above technical solution is adopted, the angle between the second groove 21 on the silicon wafer side 2 and the first surface is less than 90°, that is, there is an angle between it and the extension direction of the conductive interconnect 4. After the first groove 13 on the second arc 12 limits the conductive interconnect 4, if the displacement occurs, the friction of the conductive interconnect 4 on the silicon wafer side 2 will increase, further restricting the slippage of the conductive interconnect 4. Therefore, in order to facilitate the conductive interconnect 4 to pass through the groove 1 from the outside during the string bonding process, when the conductive interconnect 4 passes through the silicon wafer side 2, the second groove 21 on the silicon wafer side 2 further limits the conductive interconnect 4, making it easier for the conductive interconnect 4 to slide into the first arc 11, reducing the risk of getting stuck outside the groove 1, and improving the efficiency of string bonding.

[0048] In some embodiments, the width of the groove 1 on the side 2 along the length direction of the side 2 where the groove 1 is located is 1mm to 1.5mm, that is, the total width of the second arc 12 and the first arc 11 on both sides is 1mm to 1.5mm, specifically 1mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, etc. In this way, the groove 1 can accommodate the conductive interconnect 4 passing through, and the first groove 13 on the groove 1 can limit the two sides of the conductive interconnect 4. If the width is less than 1mm, the conductive interconnect 4 cannot completely enter the groove 1. If the width is greater than 1.5mm, it increases the space for the conductive interconnect 4 to wobble in the groove 1, which is not conducive to accurate positioning. Therefore, the width of the groove 1 is selected to be 1mm to 1.5mm.

[0049] In some embodiments, the depth of each groove 1 is 0.5mm to 1mm, that is, the distance from the side of the groove 1 to the furthest wall of the groove 1 is 0.5mm to 1mm, specifically 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, etc. The depth of the groove 1 is greater than the thickness of the conductive interconnect 4 at the groove location. If the depth of the groove 1 is less than 0.5mm, it is not conducive to the conductive interconnect 4 being embedded in the groove 1, causing the conductive interconnect 4 to protrude from the edge of the silicon wafer. During the assembly pressing, the conductive interconnect 4 is prone to squeezing the edge of the silicon wafer, causing microcracks or fragments in the silicon wafer. If the depth of the groove 1 is greater than 1mm, it affects the mechanical strength of the silicon wafer. Therefore, considering the mechanical strength of the silicon wafer and the penetration effect of the conductive interconnect 4, the width of the groove 1 in this embodiment is selected to be 0.5mm to 1mm.

[0050] In some embodiments, the spacing between grooves 1 is 9mm to 10mm, specifically 9mm, 9.2mm, 9.5mm, 9.7mm, 9.8mm, 10mm, etc. The spacing of the grooves 1 is determined based on the overall size of the silicon wafer and the number of conductive interconnects 4. If the spacing of the grooves 1 is less than 9mm, the number of grooves 1 is too large, affecting the mechanical strength of the silicon wafer; if the spacing is greater than 10mm, the number of grooves 1 is too small, resulting in some conductive interconnects 4 not having corresponding grooves 1 to pass through, which is not conducive to reducing the spacing between solar cells. Therefore, considering the mechanical strength of the silicon wafer and the spacing between solar cells, the groove spacing of 1 in this embodiment is selected as 9mm to 10mm.

[0051] In this embodiment, the surface roughness of the groove 1 is 0.08 μm to 1.2 μm. The roughness can be detected using a pin-type roughness tester. During the test, the probe's testing direction can be along the entire surface to be tested, i.e., the probe's testing direction can be perpendicular to the extension direction of the first groove 13. If the roughness is less than 0.08 μm, the conductive interconnect 4 is more prone to slippage within the groove 1. If the roughness is greater than 1.2 μm, the stress within the groove 1 is too high, resulting in lower mechanical strength and a higher likelihood of microcracks or fragmentation. Therefore, the surface roughness of the groove 1 is selected to be 0.08 μm to 1.2 μm. The inventors of this application have discovered through extensive research that the roughness of the grooves fabricated on silicon wafers is related to the grit size and grinding depth of the grinding wheel used during processing, as shown in Table 1 below.

[0052] Table 1. Surface roughness data of grooves

[0053]

[0054] As shown in Table 1, with the same grinding depth, a smaller grinding wheel mesh count results in a greater surface roughness of the resulting groove; a larger grinding wheel mesh count results in a smoother silicon wafer surface, but during groove processing, the grinding wheel is prone to slippage, leading to reduced processing efficiency. With the same grinding wheel mesh count, a greater grinding depth results in a greater surface roughness of the resulting groove; however, excessive roughness increases the risk of silicon wafer breakage. Therefore, this application achieves the roughness listed in the above embodiments by setting a reasonable grinding wheel mesh count and grinding depth, thereby ensuring the mechanical strength of the silicon wafer, preventing slippage of conductive interconnects, and improving the groove processing speed.

[0055] like Figure 6As shown, based on the silicon wafer described in any of the above embodiments, this utility model embodiment also provides a battery cell 3, including a silicon wafer, which is the silicon wafer described in any of the above embodiments. The battery cell 3 also has a groove 1, and the groove 1 also has a first trench 13. Since the battery cell 3 uses the silicon wafer described in any of the above embodiments, the battery cell 3 has the same beneficial effects as the silicon wafer, and will not be described again.

[0056] It is understood that a silicon wafer with a groove 1 on one side 2 can be obtained by dicing a silicon wafer with grooves 1 on two opposite sides 2, or by forming the groove 1 directly on the half-wafer during the wafer fabrication process. This application does not limit this to either method. The resulting silicon wafer is as follows: Figure 5 As shown. The corresponding battery cell 3 can also be a cell with a groove 1 on one side 2, as shown. Figure 6 As shown.

[0057] like Figure 6 As shown, this utility model also provides a photovoltaic module, including at least two solar cells 3 and at least one conductive interconnect 4. The conductive interconnect 4 connects two adjacent solar cells 3. The solar cells 3 are as described in the above embodiments. The solar cells 3 are arranged sequentially along the extension direction of the conductive interconnect 4. The conductive interconnect 4 passes through the groove 1 of the solar cell 3, and both ends of the conductive interconnect 4 are connected to the front and back components of the two adjacent solar cells 3, respectively. For example, one end of the conductive interconnect is connected to the positive electrode of the front of one solar cell, and the other end of the conductive interconnect 4 passes through the groove 1 and is connected to the negative electrode of the back of another solar cell. Since this photovoltaic module uses the solar cells 3 described above, it has the same beneficial effects as the solar cells 3, which will not be repeated here. In addition, the solar cells 3 of this photovoltaic module have grooves 1, and the conductive interconnect 4 can pass through the grooves 1. Therefore, the gap can be reduced at the junction of two solar cells 3, that is, at the overlapping position, which can increase the area of ​​the solar cells with the same area and improve the power generation efficiency.

[0058] In one embodiment, the conductive interconnect 4 is flattened at least at the location where it passes through the groove 1, meaning that all parts of the conductive interconnect 4 are flattened, or other parts are filamentous, with flattening treatment at the bend where it passes through the groove 1. The thickness of the flattened portion of the conductive interconnect 4 is 0.07mm to 0.14mm, specifically 0.07mm, 0.09mm, 0.1mm, 0.12mm, 0.14mm, etc., and the width of the flattened portion of the conductive interconnect 4 is 0.52mm to 0.587mm, specifically 0.52mm, 0.53mm, 0.55mm, 0.56mm, 0.57mm, 0.587mm, etc. Thus, the thickness and width of the conductive interconnect 4 are both less than the depth and width of the groove 1, allowing the conductive interconnect 4 to be embedded within the groove 1, reducing the spacing between the battery cells 3, and enabling the groove 1 to limit the conductive interconnect 4, reducing slippage and improving positioning accuracy.

[0059] In some possible implementations, the conductive interconnect 4 spans 100 to 600 first trenches 13 at the location where it passes through the groove 1. By contacting these spanning first trenches 13, the conductive interconnect 4 increases the sliding resistance within the groove 1, thus better limiting its slippage within the groove 1. If the number of spanning trenches is too large, the number of first trenches 13 within the groove 1 will exceed 600, affecting the mechanical strength of the silicon wafer. Therefore, the number of spanning first trenches 13 is 100 to 600.

[0060] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0061] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope of the claims.

Claims

1. A silicon wafer, characterized by, The silicon wafer has opposite first and second faces and a side surface between the first and second faces, the silicon wafer has at least one groove, the groove is inwardly opened from the side surface and penetrates through the first and second faces, the groove has a plurality of first grooves, the first grooves extend in a direction from the first face to the second face.

2. The silicon wafer of claim 1, wherein, The interval of the first grooves is 0.05um-1um; and / or, the depth of the first grooves is 0.01um-2um.

3. The silicon wafer according to claim 1 or 2, characterized in that The groove comprises a first circular arc and two second circular arcs, the two second circular arcs are respectively located on opposite sides of the first circular arc and are connected between the first circular arc and the side surface, the radius of the first circular arc is greater than or equal to the radius of the second circular arc.

4. The silicon wafer of claim 3, wherein, The radius R1 of the first circular arc is 0.5mm≤R1≤1mm, and the radius R2 of the second circular arc is 0.3mm≤R2≤0.5mm.

5. The silicon wafer of claim 3, wherein the first and second regions are formed by a process selected from the group consisting of ion implantation, diffusion, and epitaxy. The radian a1 of the first circular arc is 1 / 2π≤a1≤π, and the radian a2 of the second circular arc is 0 6. The silicon wafer of claim 3, wherein, The first circular arc and / or the second circular arc has the first grooves, and the extension direction of the first grooves is perpendicular to the first face.

7. The silicon wafer of claim 3, wherein, The side surface of the silicon wafer has second grooves, and the angle between the extension direction of the second grooves and the first face is less than 90°.

8. The silicon wafer of claim 1, wherein, The width of each groove is 1mm-1.5mm; And / or, the depth of each groove is 0.5mm-1mm; And / or, the distance between the grooves is 9mm-10mm.

9. The silicon wafer according to any one of claims 1 to 8, wherein The roughness of the surface of the groove is 0.08-1.

2.

10. A battery sheet comprising a silicon sheet, characterized in that, The silicon wafer is as claimed in any one of claims 1-9.

11. A photovoltaic module comprising at least two cells and at least one electrically conductive interconnector connected between two adjacent cells, characterized in that, The battery piece is as claimed in claim 10, and the conductive interconnection passes through the groove.

12. The photovoltaic module of claim 11, wherein, At least the position of the conductive interconnection passing through the groove is flat, the thickness of the flat position of the conductive interconnection is 0.07mm-0.14mm, and the width of the flat position of the conductive interconnection is 0.52mm-0.587mm.

13. The photovoltaic module of claim 11, wherein, The position of the conductive interconnection passing through the groove spans 100-600 first grooves.

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