Power meter device based on multi-shunt seamless switching

Abstract

The utility model discloses a power meter device based on multi-shunt seamless switching, which is characterized in that sampling circuits are connected in series, then are connected in series with the input end of a tested power supply, and then are connected in parallel with a program control alternating current source; the voltage conditioning circuit is connected with the program control alternating current source, is connected with the main DSP controller through an ADC1, and is connected with the main DSP controller through a first PGA and an ADC2; the first current conditioning circuit is connected with the first current sampling circuit and the ADC3, the second current conditioning circuit is connected with the first current channel control circuit and the second current channel control circuit, and the first current channel control circuit is connected with the second current conditioning circuit and the main DSP controller; the second current channel control circuit is connected with the first current conditioning circuit and the second current conditioning circuit. The second current channel control circuit is sequentially connected with the second PGA, the ADC4 and the main DSP controller. According to the utility model, the three shunts are connected in series, so that a current channel is ensured not to be interrupted in the switching process of the multiple shunts.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of power electronics, especially relates to a power meter device based on seamless switching of multiple shunters. BACKGROUND

[0002] Power meter is widely used in input characteristic detection of power supply product, in recent years, the detection requirement about efficiency and standby power consumption of power supply product is more and more strict, according to the detection requirement of six grade energy efficiency, power meter must be suitable for wider current measurement dynamic range, and the traditional power meter product is often difficult to meet the detection requirement of six grade energy efficiency because of the insufficient number of range or the low signal-to-noise ratio of current sampling.

[0003] Part of power meter adopts multiple range design, but often adopts single shunt design, leading to insufficient signal-to-noise ratio under small signal range, affecting the measurement precision, and in the process of range switching, data loss is caused, and the accuracy and objectivity of integration function are affected. Part of power meter adopts multiple shunt design, but often causes short open circuit in the switching of shunt, which is not allowed in part of use occasions. UTILITY MODEL CONTENT

[0004] Technical purpose: for the defects in the prior art, the utility model discloses a kind of power meter device based on seamless switching of multiple shunters, to improve the test process of power supply product, provide more range, to realize wider current measurement dynamic range, meet the test requirement of six grade energy efficiency, and in all range designs, it is guaranteed that higher signal-to-noise ratio, to ensure the precision of current measurement, more require in the switching process of range, guarantee the integrity of data acquisition, do not lose any data, and ensure that in the switching process of multiple shunters, it is guaranteed that current loop does not occur any interruption.

[0005] Technical scheme: to realize the above technical purpose, the utility model adopts the following technical scheme.

[0006] A kind of power meter device based on seamless switching of multiple shunters, including program-controlled AC source, several current sampling circuits, voltage conditioning circuit, several current conditioning circuits, several current channel control circuits, several PGAs, several ADCs and main DSP controller;ADC includes ADC1, ADC2, ADC3, ADC4;ADC is connected with main DSP controller;PGA includes first PGA and second PGA, and first PGA and second PGA are connected with main DSP controller;

[0007] The current sampling circuit comprises a first current sampling circuit, a second current sampling circuit and a third current sampling circuit, which are connected in series, connected in series with the input end of the measured power supply, and then connected in parallel with the programmed AC source, so that the shunt in the current sampling circuit realizes current signal sampling.

[0008] The input end of the voltage conditioning circuit is connected with the programmed AC source to complete voltage signal sampling; the output end of the voltage conditioning circuit is connected with the input end of the ADC1, and the output end of the ADC1 is connected with the main DSP controller; the output end of the voltage conditioning circuit is also connected with the input end of the first PGA, the output end of the first PGA is connected with the input end of the ADC2, and the output end of the ADC2 is connected with the main DSP controller.

[0009] The current conditioning circuit comprises a first current conditioning circuit and a second current conditioning circuit; the input end of the first current conditioning circuit is connected with the first current sampling circuit, the output end of the first current conditioning circuit is connected with the input end of the ADC3, and the output end of the ADC3 is connected with the main DSP controller.

[0010] The input end of the second current conditioning circuit is connected with the output end of the first current channel control circuit, and the output end of the second current conditioning circuit is connected with the input end of the second current channel control circuit.

[0011] The current channel control circuit comprises a first current channel control circuit and a second current channel control circuit; the input end of the first current channel control circuit is connected with the second current sampling circuit and the third current sampling circuit, the output end of the first current channel control circuit is connected with the input end of the second current conditioning circuit; the control end of the first current channel control circuit is connected with the main DSP controller; the input end of the second current channel control circuit is connected with the output end of the first current conditioning circuit and the output end of the second current conditioning circuit, the output end of the second current channel control circuit is connected with the input end of the second PGA, the output end of the second PGA is connected with the input end of the ADC4, and the output end of the ADC4 is connected with the main DSP controller; and the control end of the second current channel control circuit is connected with the main DSP controller.

[0012] Advantages:

[0013] The utility model discloses the measurement of voltage and current, each adopts two two-stage PGA, realizes multi-range measurement, and guarantees the dynamic range and precision of voltage and current measurement.

[0014] The utility model discloses a 3 shunt series connection design and its supporting protection mechanism are adopted, ensure that the current channel is uninterrupted in the multi shunt switching process, and on the basis of the PGA design, under the condition of no signal noise ratio loss, the range quantity is increased to 3 times, further expand the dynamic range and precision of current measurement, satisfy the latest requirement of power industry six grade energy efficiency test.

[0015] The utility model discloses a 4 way 24 bit high -speed synchronous sampling ADC, realizes the intelligent design of no data loss in range switching process, solves the adverse effect of high -precision measurement multi -range switching to wattmeter integration function and waveform presentation. DRAWINGS

[0016] Figure 1 It is total structure schematic drawing of the utility model;

[0017] Figure 2 It is voltage conditioning circuit schematic diagram provided by the utility model embodiment;

[0018] Figure 3 It is current conditioning circuit schematic diagram provided by the utility model embodiment;

[0019] Figure 4 It is PGA circuit schematic diagram provided by the utility model embodiment. CONCRETE EMBODIMENT

[0020] The utility model is further explained and explained in combination with the drawings and embodiment.

[0021] As shown in the accompanying Figure 1 The utility model discloses a kind of based on multi shunt seamless switching wattmeter device of the embodiment, comprising: program-controlled ac source, several current sampling circuits, voltage conditioning circuit, several current conditioning circuits, several protection circuits, several current channel control circuits, several PGAs, several ADC and main DSP controller;ADC includes ADC1, ADC2, ADC3, ADC4;ADC is analog-digital conversion module, also 24 bit four-channel high-speed synchronous sampling ADC, model is AD7768-4, ADC is connected with main DSP controller, and the model of main DSP controller is STM32F446RC;PGA includes first PGA and second PGA, and first PGA and second PGA are connected with main DSP controller;

[0022] Current sampling circuit includes first current sampling circuit, second current sampling circuit, third current sampling circuit, first current sampling circuit, second current sampling circuit, third current sampling circuit are connected in series, then with the input end of measured power source in series, again with program-controlled ac source parallel connection, so that shunt in current sampling circuit realizes current signal sampling;

[0023] The protection circuit comprises a first protection circuit and a second protection circuit, an input end of the first protection circuit is connected with the third current sampling circuit, and a control end of the first protection circuit is connected with the main DSP controller; an input end of the second protection circuit is connected with the second current sampling circuit and the third current sampling circuit, and a control end of the second protection circuit is connected with the main DSP controller;

[0024] An input end of the voltage conditioning circuit is connected with the program-controlled alternating current source to complete sampling of the voltage signal; an output end of the voltage conditioning circuit is connected with an input end of the ADC1, an output end of the ADC1 is connected with the main DSP controller; the output end of the voltage conditioning circuit is also connected with an input end of the first PGA, an output end of the first PGA is connected with an input end of the ADC2, and an output end of the ADC2 is connected with the main DSP controller;

[0025] The current conditioning circuit comprises a first current conditioning circuit and a second current conditioning circuit; an input end of the first current conditioning circuit is connected with the first current sampling circuit, an output end of the first current conditioning circuit is connected with an input end of the ADC3, and an output end of the ADC3 is connected with the main DSP controller;

[0026] An input end of the second current conditioning circuit is connected with an output end of the first current channel control circuit, and an output end of the second current conditioning circuit is connected with an input end of the second current channel control circuit;

[0027] The current channel control circuit comprises a first current channel control circuit and a second current channel control circuit, an input end of the first current channel control circuit is connected with the second current sampling circuit and the third current sampling circuit, and an output end of the first current channel control circuit is connected with an input end of the second current conditioning circuit; a control end of the first current channel control circuit is connected with the main DSP controller, specifically, connected with a SW3 pin of the main DSP controller, and the main DSP controller realizes selection of the shunt in the second current sampling circuit and the third current sampling circuit by controlling the level of the SW3, when the SW3 is at a low level, the shunt of the second current sampling circuit is selected, and when the SW3 is at a high level, the shunt of the third current sampling circuit is selected.

[0028] An input end of the second current channel control circuit is connected with an output end of the first current conditioning circuit and an output end of the second current conditioning circuit, an output end of the second current channel control circuit is connected with an input end of the second PGA, an output end of the second PGA is connected with an input end of the ADC4, and an output end of the ADC4 is connected with the main DSP controller; a control end of the second current channel control circuit is connected with the main DSP controller, specifically, connected with a SW4 pin of the main DSP controller.

[0029] The main DSP controller is in communication connection with the first PGA and the second PGA through an SPI bus;

[0030] In this embodiment, the number of current sampling circuits is three, which are a first current sampling circuit, a second current sampling circuit and a third current sampling circuit; each current sampling circuit has the same structure, and the current sampling circuits are connected in series;

[0031] The measured power supply, the first current sampling circuit, the second current sampling circuit and the third current sampling circuit are connected in series with the output pin of the program-controlled AC source, so as to realize sampling of the current signal, and the output current of the program-controlled AC source is the input current of the measured power supply, thereby realizing sampling of the current signal of the measured power supply; the output pin of the program-controlled AC source includes a pin L and a pin N; the pin N of the program-controlled AC source is grounded, and the pin L of the measured power supply is connected with the pin L of the program-controlled AC source. It should be noted that the program-controlled AC source is an external device of the measured power supply, and is not a component of the power meter device of the utility model, which is equivalent to that the measured power supply is connected to the power grid, and the program-controlled AC source is a device for simulating the power grid.

[0032] The first current sampling circuit includes a resistor R1, a diode D1 and a diode D2; one end of the resistor R1 is connected with the anode of the diode D1 and the cathode of the diode D2 as the input end of the first current sampling circuit; the other end of the resistor R1 is connected with the cathode of the diode D1 and the anode of the diode D2 as the output end of the first current sampling circuit; the input end of the first current sampling circuit is connected with the pin N of the measured power supply;

[0033] The second current sampling circuit includes a resistor R2, a diode D3 and a diode D4; one end of the resistor R2 is connected with the anode of the diode D3 and the cathode of the diode D4 as the input end of the second current sampling circuit; the other end of the resistor R2 is connected with the cathode of the diode D3 and the anode of the diode D4 as the output end of the second current sampling circuit; the input end of the second current sampling circuit is connected with the output end of the first current sampling circuit;

[0034] The third current sampling circuit includes a resistor R3, a diode D5 and a diode D6; one end of the resistor R3 is connected with the anode of the diode D5 and the cathode of the diode D6 as the input end of the third current sampling circuit; the other end of the resistor R3 is connected with the cathode of the diode D5 and the anode of the diode D6 as the output end of the third current sampling circuit; the input end of the third current sampling circuit is connected with the output end of the second current sampling circuit; and the output end of the third current sampling circuit is grounded.

[0035] The resistor R1 in the first current sampling circuit is used as a large-range shunt, and the diode D1 and the diode D2 are clamping diodes. When the current exceeds the maximum range that can be accommodated by the shunt, the voltage on the resistor R1 will be clamped by one of the diodes D1 and D2 when it rises, and the current will be shunted from the clamping diode, ensuring that the resistor R1 shunt will not be damaged by heat due to overcurrent. Similarly, the working processes of the second current sampling circuit and the third current sampling circuit are the same as that of the first current sampling circuit, and the difference lies in that the resistor R2 in the second current sampling circuit is used as a medium-range shunt, and the resistor R3 in the third current sampling circuit is used as a small-range shunt, and R1 < R2 < R3.

[0036] The protection circuit includes a first protection circuit and a second protection circuit, and the first protection circuit and the second protection circuit are the same in structure; the first protection circuit is connected with the third current sampling circuit to realize overcurrent protection of the third current sampling circuit; the second protection circuit is connected with the second current sampling circuit to realize overcurrent protection of the second current sampling circuit.

[0037] The first protection circuit includes a relay S1, a diode D9 and a transistor Q3. The relay S1 is a single-pole single-throw relay, and the model is SHV9. The pin 1 of the relay S1 is connected with the output end of the third current sampling circuit, i.e. the other end of the resistor R3, the pin 2 of the relay S1 is connected with the input end of the third current sampling circuit, i.e. one end of the resistor R3. The pin 3 of the relay S1 is connected with the negative electrode of the diode D9, the pin 4 of the relay S1 is connected with the positive electrode of the diode D9, the positive electrode of the diode D9 is connected with the collector of the transistor Q3, the emitter of the transistor Q3 is grounded, and the base of the transistor Q3 is connected with the main DSP controller, specifically connected with the SW1 pin of the main DSP controller.

[0038] In the first current protection circuit, when the measured current exceeds the maximum range matched by the resistor R3, the main DSP controller will set the SW1 to high level, so as to short-circuit the relay S1, and then make the current flow through the relay S1, so as to ensure the low impedance characteristic of the current loop, and prevent the shunt R3 and the diodes D5 and D6 from being overheated and damaged due to large current. The diode D9 is used to suppress the reverse excitation voltage generated by the relay driving coil during the switching process of the relay, and the transistor Q3 is used for driving the working current of the relay S1.

[0039] The second protection circuit comprises a relay S2, a diode D10 and a transistor Q4. The relay S2 is a single-pole single-throw relay, and the model is SHV9. The pin 1 of the relay S2 is connected with the output end of the third current sampling circuit, i.e. the other end of the resistor R3. The pin 2 of the relay S2 is connected with the input end of the second current sampling circuit, i.e. one end of the resistor R2. The pin 3 of the relay S2 is connected with the negative end of the diode D10. The pin 4 of the relay S2 is connected with the positive end of the diode D10. The positive end of the diode D10 is connected with the collector of the transistor Q4. The emitter of the transistor Q4 is grounded. The base of the transistor Q4 is connected with the main DSP controller, specifically, connected with the SW2 pin of the main DSP controller.

[0040] In the second current protection circuit, when the measured current exceeds the maximum range matched by the resistor R2, the main DSP controller will set the SW2 to high level, so as to short the relay S2, and then make the current flow through the relay S2, so as to ensure the low impedance characteristic of the current loop, and prevent the shunt resistor R2 and the diodes D3 and D4 from being damaged due to overheating caused by large current. The diode D10 is used to suppress the reverse excitation voltage generated by the relay driving coil during the switching process of the relay. The transistor Q4 is used to drive the working current of the relay S2.

[0041] The R1 of the first current sampling circuit is a shunt resistor corresponding to the large current range. The R2 of the second current sampling circuit is a shunt resistor corresponding to the medium current range. The R3 of the third current sampling circuit is a shunt resistor corresponding to the small current range. The diodes D1, D2, D3, D4, D5 and D6 are all clamping diodes for protection. The large current range has 20A, 10A, 5A and 2A, i.e. four ranges. The medium current range has 1A, 0.5A, 0.2A and 0.1A, i.e. four ranges. The small current range has 0.05A, 0.02A, 0.01A and 0.005A, i.e. four ranges. There are totally 12 current ranges, which can be set according to the actual situation. When the current exceeds the range of the shunt resistor, the clamping diode can protect the shunt resistor to work in a safe area. The first protection circuit and the two ends of the third current sampling circuit are connected. When the main DSP controller detects that the measured current value exceeds the maximum range of the small current range, the third current sampling circuit is opened or short-circuited by controlling the level of the SW1 signal pin. The opening means enabling the third current sampling circuit, and the short-circuiting means disabling the third current sampling circuit. The two ends of the series connection of the second current sampling circuit and the third current sampling circuit are connected with the second protection circuit. When the main DSP controller detects that the measured current value exceeds the maximum range of the medium current range, the second current sampling circuit and the third current sampling circuit are opened or short-circuited by controlling the level of the SW2 signal pin. The opening means enabling the second current sampling, and the short-circuiting means disabling the second current sampling circuit and the third current sampling circuit.

[0042] As shown in the accompanying Figure 2 The voltage conditioning circuit includes an operational amplifier chip U21A, the model of which is OP2177; pin 3 of the operational amplifier chip U21A is connected to the Vin+ signal end through a resistor R21, the Vin+ signal end serves as a first input end of the voltage conditioning circuit and is connected to pin L of the programmable AC source; pin 2 of the operational amplifier chip U21A is connected to the Vin- signal end through a resistor R22, the Vin- signal end serves as a second input end of the voltage conditioning circuit and is connected to pin N of the programmable AC source; pin 3 of the operational amplifier chip U21A is connected to ground through a resistor R23, pin 2 of the operational amplifier chip U21A is connected to pin 1 of the operational amplifier chip U21A through a resistor R24, pin 4 of the operational amplifier chip U21A is connected to a -12V voltage signal, pin 4 of the operational amplifier chip U21A is connected to ground through a capacitor C22, pin 8 of the operational amplifier chip U21A is connected to a +12V voltage signal, pin 8 of the operational amplifier chip U21A is connected to ground through a capacitor C21, and pin 1 of the operational amplifier chip U21A is connected to the Vout signal end, which serves as an output end of the voltage conditioning circuit.

[0043] The voltage conditioning circuit is a differential amplifier, the capacitors C21 and C22 are decoupling capacitors, the resistors R21 and R22 are required to be as consistent as possible, the resistors R23 and R24 are required to be as consistent as possible, and the gain G of the voltage conditioning circuit is R23 / R21.

[0044] The voltage conditioning circuit is connected to the programmable AC source, the Vin+ signal end is connected to pin L of the programmable AC source, and the Vin- signal end is connected to pin N of the programmable AC source, so as to complete sampling of the voltage signal of the measured power supply; the output end of the voltage conditioning circuit is connected to the input end of an ADC1, the ADC1 is used for analog-to-digital conversion of the output of the voltage conditioning circuit and transmission to a main DSP controller, so as to complete measurement of the maximum range of the voltage signal.

[0045] The output end of the voltage conditioning circuit is connected to the input end of a first PGA, the output end of the first PGA is connected to the input end of an ADC2, the ADC2 is used for analog-to-digital conversion of the output of the first PGA and transmission to the main DSP controller, so as to complete measurement of the voltage signal range specified by the main DSP controller; the main DSP controller is connected to the first PGA through an SPI bus, and the main DSP controller sets different PGA gains to match the specified voltage range. After the voltage conditioning circuit and the ADC1 measure the voltage of the measured power supply, the voltage is transmitted to the main DSP controller, the voltage range to which the measured power supply belongs is determined according to the voltage measured by the main DSP controller, the DAC in the first PGA is set according to the determined voltage range, and adjustment of the PGA gain is realized. Different voltage ranges correspond to different PGA gains, and the smaller the voltage range, the higher the PGA gain.

[0046] The main DSP controller reads the analog-digital conversion result of ADC1 to obtain the measurement data of the maximum range of the voltage signal, and reads the analog-digital conversion result of ADC2 to obtain the measurement data of the most appropriate range of the voltage signal. In the process of range switching, the main DSP controller takes the data of ADC1 as the effective voltage signal to ensure the integrity of the data. In the time when range switching is not required, the main DSP controller takes the data of ADC1 as the effective voltage signal to ensure the accuracy of the data.

[0047] The current conditioning circuit in the embodiment includes a first current conditioning circuit and a second current conditioning circuit; the first current conditioning circuit and the second current conditioning circuit are identical in structure,

[0048] As shown in the accompanying Figure 3 The first current conditioning circuit includes an operational amplifier chip U31A, and the model of the operational amplifier chip U31A is AD8422. Pin 4 of the operational amplifier chip U31A is connected with a Vin+ signal end through a resistor R31, and the Vin+ signal end is taken as a first input end of the first current conditioning circuit and is connected with an input end of the first current sampling circuit, i.e. one end of a resistor R1 in the first current sampling circuit. Pin 1 of the operational amplifier chip U31A is connected with a Vin- signal end through a resistor R32, and the Vin- signal end is taken as a second input end of the first current conditioning circuit and is connected with an output end of the first current sampling circuit, i.e. the other end of the resistor R1 in the first current sampling circuit. Pin 4 of the operational amplifier chip U21A is connected with pin 1 of the operational amplifier chip U21A through a capacitor C31. Pin 4 of the operational amplifier chip U21A is grounded through a capacitor C32, and pin 4 of the operational amplifier chip U21A is connected with pin 8 of the operational amplifier chip U21A through the capacitor C32 and a capacitor C34, and pin 8 of the operational amplifier chip U21A is connected with a +12V voltage signal. Pin 1 of the operational amplifier chip U21A is grounded through a capacitor C33, and pin 1 of the operational amplifier chip U21A is connected with pin 5 of the operational amplifier chip U21A through the capacitor C33 and a capacitor C35, and pin 5 of the operational amplifier chip U21A is connected with a -12V voltage signal. Pin 2 of the operational amplifier chip U21A is connected with pin 3 of the operational amplifier chip U21A through a resistor R33, and pin 7 of the operational amplifier chip U21A is taken as a Vout signal end, and the Vout signal end is taken as an output end of the first current conditioning circuit.

[0049] The resistor R33 is used for gain G control of the current conditioning circuit, and G = 19800 / R33+1. The resistor R31 and the resistor R32 are as consistent as possible, the capacitor C32 and the capacitor C33 are as consistent as possible, the resistor R31 and the capacitor C32 constitute an RC filter circuit, the resistor R32 and the capacitor C33 constitute an RC filter circuit, the capacitor C31 is used for suppressing common-mode interference of the current signal, and the capacitor C34 and the capacitor C35 are decoupling capacitors.

[0050] The output end of the first current conditioning circuit is connected with the input end of the ADC3, and the ADC3 is used for analog-digital conversion of the output of the first current conditioning circuit and is transmitted to the main DSP controller to complete the measurement of the maximum range of the current signal.

[0051] Similarly, the first input end and the second input end of the second current conditioning circuit are connected with the first output end and the second output end of the first current channel control circuit respectively, and the output end of the second current conditioning circuit is connected with the second input end of the second current channel control circuit. The output of the first current channel control circuit is connected with the second current conditioning circuit, and the second current conditioning circuit linearly amplifies the output of the first current channel control circuit.

[0052] The current channel control circuit comprises the first current channel control circuit and the second current channel control circuit;

[0053] The first current channel control circuit comprises a relay S3, which is a double-pole double-throw relay with a model of G6K-2F. The pin 1 of the relay S3 is connected with the input end of the second current sampling circuit, i.e. one end of the resistor R2, the pin 3 of the relay S3 is connected with the output end of the second current sampling circuit, i.e. the other end of the resistor R2; the pin 8 of the relay S3 is connected with the input end of the third current sampling circuit, i.e. one end of the resistor R3, the pin 6 of the relay S3 is connected with the output end of the third current sampling circuit, i.e. the other end of the resistor R3; the pin 4 of the relay S3 is connected with the positive electrode of the diode D7, the pin 5 of the relay S3 is connected with the negative electrode of the diode D7, and the pin 5 of the relay S3 is connected with a +12V voltage signal; the pin 4 of the relay S3 is connected with the collector of the transistor Q1, the emitter of the transistor Q1 is grounded, and the base of the transistor Q1 is connected with the main DSP controller, specifically connected with the SW3 signal end of the main DSP controller. The pins 2 and 7 of the relay S3 are two output ends of the first current channel control circuit, which are connected with the second current conditioning circuit, i.e. connected with Vin+ and Vin- of the second current conditioning circuit.

[0054] The inputs of the relay S3 are connected with the outputs of the second current sampling circuit and the third current sampling circuit respectively, and the output of the relay S3 is connected with the input of the second conditioning circuit. The main DSP controller realizes the selection of the two shunters R2 and R3 by controlling the level of SW3. When SW3 is at low level, the R2 shunt is selected, and the output of the first current channel control circuit is the double end of the second current sampling circuit. When SW3 is at high level, the R3 shunt is selected, and the output of the first current channel control circuit is the double end of the third current sampling circuit.

[0055] The second current channel control circuit comprises a relay S4, which is a double-pole double-throw relay with a model of G6K-2F. The pin 1 of the relay S4 is connected with the output end of the first current conditioning circuit, and the pin 3 of the relay S4 is connected with the output end of the second current conditioning circuit. The pin 4 of the relay S4 is connected with the positive electrode end of a diode D8, the pin 5 of the relay S4 is connected with the negative electrode end of the diode D8, and the pin 5 of the relay S4 is connected with a +12V voltage signal. The pin 4 of the relay S4 is connected with the collector of a transistor Q2, the emitter of the transistor Q2 is grounded, and the base of the transistor Q2 is connected with the main DSP controller, specifically, connected with the SW4 signal end of the main DSP controller. The pin 2 of the relay S4 is the output end of the second current channel control circuit, and is connected with the second PGA, i.e., connected with the Vin of the second PGA.

[0056] The second current channel control circuit is connected with the outputs of the first current conditioning circuit and the second current conditioning circuit. The main DSP controller controls the output of the second current channel control circuit by controlling the level of the SW4 signal pin. When the SW4 signal is at a low level, the output of the second current channel control circuit is the output of the first current conditioning circuit, which corresponds to the amplified signal of the first current sampling circuit. When the SW4 signal is at a high level, the output of the second current channel control circuit is the output of the second current conditioning circuit. At this time, when the main DSP controller controls the SW3 to be at a low level and the SW4 to be at a high level, the output of the second current channel control circuit corresponds to the signal of the second current sampling circuit. When the main DSP controller controls the SW3 to be at a high level and the SW4 to be at a high level, the output of the second current channel control circuit corresponds to the amplified signal of the third current sampling circuit.

[0057] The main DSP controller selects one shunt from the first current sampling circuit, the second current sampling circuit and the third current sampling circuit by controlling the levels of the SW3 and the SW4, and then realizes a 3-fold multi-range design without signal-to-noise ratio loss on the basis of the multi-range control realized by the PGA. Specifically, after the current size of the measured power supply is measured by the first current conditioning circuit and the ADC3, the measured current size is transmitted to the main DSP controller. The main DSP controller determines the current range according to the measured current size of the measured power supply, and manually sets the level of the SW signal according to the determined current range to select the corresponding current sampling circuit.

[0058] The output of the second current channel control circuit is connected to the input of the second PGA, and the output of the second PGA is connected to the input of ADC4. ADC4 performs analog-to-digital conversion on the output of the second PGA and transmits it to the main DSP controller to complete the measurement of the specified current signal range by the main DSP controller. The main DSP controller is connected to the second PGA through the SPI bus. The main DSP controller matches the specified current range by setting different PGA gains.

[0059] The main DSP controller reads the analog-to-digital conversion result of ADC3 to obtain the measurement data of the current signal at its maximum range. The main DSP controller reads the analog-to-digital conversion result of ADC4 to obtain the measurement data of the current signal at its most suitable range. During the range switching process, the main DSP controller takes the data from ADC3 as the valid current signal to ensure data integrity. When range switching is not required, the main DSP controller takes the data from ADC4 as the valid current signal to ensure data accuracy.

[0060] In this embodiment, the PGA includes a first PGA and a second PGA, which have the same structure; the PGA is a programmable gain amplifier, and the PGA is connected to the main DSP controller via an SPI bus.

[0061] As attached Figure 4 As shown, the first PGA includes operational amplifier chips U41A, U41B, U42A, U42B, and conversion chip U43. Operational amplifier chips U41A and U41B share a single operational amplifier chip, and operational amplifier chips U42A and U42B also share a single operational amplifier chip, model OP2177. Conversion chip U43 is an 8-bit dual-channel current-output multiplier DAC converter, model AD5429.

[0062] The pin 2 of the operational amplifier chip U41A is connected with the Vin signal end through the resistor R1, the Vin signal end is used as the input end of the first PGA; the pin 3 of the operational amplifier chip U41A is connected with the pin 1 of the operational amplifier chip U41A, the pin 2 of the operational amplifier chip U41A is connected with the pin 1 of the operational amplifier chip U41A through the capacitor C41, the pin 1 of the operational amplifier chip U41A is connected with the pin 2 of the operational amplifier chip U42A through the resistor R42, the pin 2 of the operational amplifier chip U42A is connected with the pin 1 of the operational amplifier chip U42A through the capacitor C43, the pin 3 of the operational amplifier chip U41A is connected with the pin 7 of the operational amplifier chip U41B, and the pin 7 of the operational amplifier chip U41B outputs the V1 signal; the pin 6 of the operational amplifier chip U41B is connected with the pin 7 of the operational amplifier chip U41B through the capacitor C42, the pin 7 of the operational amplifier chip U41B outputs the V2 signal, and the pin 5 of the operational amplifier chip U41B is grounded; the pin 3 of the operational amplifier chip U42A is connected with the pin 7 of the operational amplifier chip U42B, the pin 7 of the operational amplifier chip U42B is connected with the pin 6 of the operational amplifier chip U42B through the capacitor C44, and the pin 5 of the operational amplifier chip U42B is grounded; the pin 3 of the conversion chip U43 is connected with the pin 7 of the operational amplifier chip U41B, the pin 1 of the conversion chip U43 is connected with the pin 6 of the operational amplifier chip U41B, the pin 2 of the conversion chip U43 is grounded, the pin 4 of the conversion chip U43 is connected with the pin 1 of the operational amplifier chip U42A, the pin 1 of the operational amplifier chip U42A outputs the V3 signal, the pin 14 of the conversion chip U43 is connected with the pin 7 of the operational amplifier chip U42B, the pin 7 of the operational amplifier chip U42B outputs the V4 signal, the pin 16 of the conversion chip U43 is connected with the pin 6 of the operational amplifier chip U42B, the pin 15 of the conversion chip U43 is grounded, and the pin 13 of the conversion chip U43 is connected with the pin 1 of the operational amplifier chip U42A; the pins 11 and 12 of the conversion chip U43 are connected with +3.3V voltage signals, the pins 10, 7, 8 and 9 of the conversion chip U43 are respectively used as the SYNC signal end, the SCLK signal end, the SDIN signal end and the SDO signal end, and SPI communication is realized with the main DSP controller; the pins 5 and 6 of the conversion chip U43 are grounded, the pin 6 of the conversion chip U43 is connected with +3.3V voltage signal through the capacitor C45, the pin 12 of the conversion chip U43 is connected with +3.3V voltage signal, the pin 13 of the conversion chip U43 is connected with the Vout signal end, and the Vout signal end is used as the output end of the first PGA.

[0063] The utility model discloses, the conversion chip U43 in first PGA is as DAC1, the conversion chip U43 in second PGA is as DAC2, the main DSP controller is through SPI bus, sets up DAC1 as D_A, sets up DAC2 as D_B, DAC2 carries out digital analog conversion to D_B, and the output V3 of U42A is connected with the reference voltage input end of DAC2, and U42B converts the current output of DAC2 to voltage output V4, and V4=-V3*D_B / 256.

[0064] The output of U41B is connected with the negative input end of U41A, and finally forms a negative feedback, forces the positive and negative input ends of U41A to be equal, that is, Vin=V2=-V1*D_A / 256, that is, V1=Vin*256 / D_A.

[0065] The output of U41B is connected with the positive input end of U42A, and the output of U42B is connected with the negative input end of U42, and finally forms a negative feedback, forces the positive and negative input ends of U42A to be equal, that is, V1=V4=-V3*D_B / 256, that is, Vout=V3=V1*256 / D_B=Vin*65535 / D_A / D_B (wherein 1≤D_A≤255, 1≤D_B≤255).

[0066] The main DSP controller carries out gain control to the voltage signal of first PGA through SPI bus, to realize the multi-range switching of voltage measurement, and increase the dynamic range of voltage measurement.

[0067] The main DSP controller carries out gain control to the current signal of second PGA through SPI bus, to realize the multi-range switching of current measurement, and increase the dynamic range of current measurement.

[0068] Three current sampling circuits are designed in series, which guarantees the continuity of current path. When the main DSP controller selects the first current sampling circuit, SW2 is set to high level, short-circuiting the second current sampling circuit and the third current sampling circuit, to prevent the overcurrent thermal damage of sampling resistor and clamping diode. When the main DSP controller selects the second current sampling circuit, SW1 is set to high level, short-circuiting the third current sampling circuit, to prevent the overcurrent thermal damage of sampling resistor and clamping diode.

[0069] The main DSP controller controls the range selection of voltage and current according to the external input of man-machine interface or host computer software, and can also automatically match the appropriate range according to the actual measurement results of voltage and current, and calculates a series of electrical parameters such as voltage effective value, current effective value and active power according to the measurement results of voltage and current, to complete the detection work of power meter.

[0070] The current of the measured power supply can be adjusted through the electronic load, and the greater the power drawn by the electronic load, the greater the input current of the measured power supply.

[0071] The above only describes the preferred embodiments of the present application, and it should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, can make a number of improvements and refinements, these improvements and refinements should also be considered within the scope of the present application.

Claims

1. A power meter device based on seamless switching of multiple splitters, characterized by: The current sampling circuit includes a first current sampling circuit, a second current sampling circuit and a third current sampling circuit, which are connected in series, connected in series with the input end of the measured power supply, and then connected in parallel with the program-controlled AC source, so that the shunt in the current sampling circuit can sample the current signal. The input end of the voltage conditioning circuit is connected with the program-controlled AC source to complete the sampling of the voltage signal; the output end of the voltage conditioning circuit is connected with the input end of the ADC1, and the output end of the ADC1 is connected with the main DSP controller; the output end of the voltage conditioning circuit is also connected with the input end of the first PGA, the output end of the first PGA is connected with the input end of the ADC2, and the output end of the ADC2 is connected with the main DSP controller. The current conditioning circuit includes a first current conditioning circuit and a second current conditioning circuit; the input end of the first current conditioning circuit is connected with the first current sampling circuit, the output end of the first current conditioning circuit is connected with the input end of the ADC3, and the output end of the ADC3 is connected with the main DSP controller. The input end of the second current conditioning circuit is connected with the output end of the first current channel control circuit, and the output end of the second current conditioning circuit is connected with the input end of the second current channel control circuit. The current channel control circuit includes a first current channel control circuit and a second current channel control circuit; the input end of the first current channel control circuit is connected with the second current sampling circuit and the third current sampling circuit, the output end of the first current channel control circuit is connected with the input end of the second current conditioning circuit; the control end of the first current channel control circuit is connected with the main DSP controller; the input end of the second current channel control circuit is connected with the output end of the first current conditioning circuit and the output end of the second current conditioning circuit, the output end of the second current channel control circuit is connected with the input end of the second PGA, the output end of the second PGA is connected with the input end of the ADC4, and the output end of the ADC4 is connected with the main DSP controller; the control end of the second current channel control circuit is connected with the main DSP controller. The protection circuit includes a first protection circuit and a second protection circuit; the input end of the first protection circuit is connected with the third current sampling circuit, and the control end of the first protection circuit is connected with the main DSP controller; the input end of the second protection circuit is connected with the second current sampling circuit and the third current sampling circuit, and the control end of the second protection circuit is connected with the main DSP controller.

2. The power meter device based on seamless switching of multiple splitters of claim 1, wherein: ​ 3. The power meter device based on seamless switching of multiple splitters of claim 2, wherein: The first protection circuit comprises a relay S1, a diode D9 and a transistor Q3; the relay S1 is a single-pole single-throw relay, the pin 1 of the relay S1 is connected with the output end of the third current sampling circuit, the pin 2 of the relay S1 is connected with the input end of the third current sampling circuit; the pin 3 of the relay S1 is connected with the negative electrode end of the diode D9, the pin 4 of the relay S1 is connected with the positive electrode end of the diode D9, the positive electrode end of the diode D9 is connected with the collector of the transistor Q3, the emitter of the transistor Q3 is grounded, and the base of the transistor Q3 is connected with the main DSP controller; The second protection circuit comprises a relay S2, a diode D10 and a transistor Q4; the relay S2 is a single-pole single-throw relay, the pin 1 of the relay S2 is connected with the output end of the third current sampling circuit, the pin 2 of the relay S2 is connected with the input end of the second current sampling circuit; the pin 3 of the relay S2 is connected with the negative electrode end of the diode D10, the pin 4 of the relay S2 is connected with the positive electrode end of the diode D10, the positive electrode end of the diode D10 is connected with the collector of the transistor Q4, the emitter of the transistor Q4 is grounded, and the base of the transistor Q4 is connected with the main DSP controller.

4. The power meter device based on seamless switching of multiple splitters of claim 1, wherein: The first current sampling circuit, the second current sampling circuit and the third current sampling circuit have the same structure and are connected in series. The first current sampling circuit comprises a resistor R1, a diode D1 and a diode D2; one end of the resistor R1 is connected with the positive electrode end of the diode D1 and the negative electrode end of the diode D2 as the input end of the first current sampling circuit; the other end of the resistor R1 is connected with the negative electrode end of the diode D1 and the positive electrode end of the diode D2 as the output end of the first current sampling circuit; the input end of the first current sampling circuit is connected with the pin N of the measured power supply; the resistor R1 in the first current sampling circuit is used as a large-range shunt, the resistor R2 in the second current sampling circuit is used as a medium-range shunt, and the resistor R3 in the third current sampling circuit is used as a small-range shunt.

5. The power meter device based on seamless switching of multiple splitters of claim 1, wherein: The voltage conditioning circuit comprises an operational amplifier chip U21A, the pin 3 of the operational amplifier chip U21A is connected with the first input end of the voltage conditioning circuit through a resistor R21 and is connected with the pin L of the program-controlled alternating current source; the pin 2 of the operational amplifier chip U21A is connected with the second input end of the voltage conditioning circuit through a resistor R22 and is connected with the pin N of the program-controlled alternating current source; the pin 2 of the operational amplifier chip U21A is connected with the pin 1 of the operational amplifier chip U21A through a resistor R24, the pin 4 of the operational amplifier chip U21A is grounded through a capacitor C22, the pin 8 of the operational amplifier chip U21A is grounded through a capacitor C21, and the pin 1 of the operational amplifier chip U21A is connected with the output end of the voltage conditioning circuit.

6. The power meter device based on seamless switching of multiple splitters of claim 1, wherein: The first current regulating circuit and the second current regulating circuit are of the same structure; the first current regulating circuit comprises an operational amplifier chip U31A, a pin 4 of the operational amplifier chip U31A is connected with a first input end of the first current regulating circuit through a resistor R31, and is connected with an input end of the first current sampling circuit; a pin 1 of the operational amplifier chip U31A is connected with a second input end of the first current regulating circuit through a resistor R32, and is connected with an output end of the first current sampling circuit; a pin 4 of the operational amplifier chip U21A is connected with a pin 1 of the operational amplifier chip U21A through a capacitor C31; the pin 4 of the operational amplifier chip U21A is grounded through a capacitor C32, the pin 4 of the operational amplifier chip U21A is connected with a pin 8 of the operational amplifier chip U21A through the capacitor C32 and a capacitor C34, a pin 1 of the operational amplifier chip U21A is grounded through a capacitor C33, and the pin 1 of the operational amplifier chip U21A is connected with a pin 5 of the operational amplifier chip U21A through the capacitor C33 and a capacitor C35; a pin 2 of the operational amplifier chip U21A is connected with a pin 3 of the operational amplifier chip U21A through a resistor R33, and a pin 7 of the operational amplifier chip U21A serves as an output end of the first current regulating circuit.

7. The power meter device based on seamless switching of multiple splitters of claim 1, wherein: The first current channel control circuit comprises a relay S3, the relay S3 is a double-pole double-throw relay, a pin 1 of the relay S3 is connected with an input end of the second current sampling circuit, a pin 3 of the relay S3 is connected with an output end of the second current sampling circuit; a pin 8 of the relay S3 is connected with an input end of the third current sampling circuit, a pin 6 of the relay S3 is connected with an output end of the third current sampling circuit; a pin 4 of the relay S3 is connected with a positive electrode end of a diode D7, a pin 5 of the relay S3 is connected with a negative electrode end of the diode D7, the pin 4 of the relay S3 is connected with a collector of a transistor Q1, an emitter of the transistor Q1 is grounded, a base of the transistor Q1 is connected with a main DSP controller, and a pin 2 and a pin 7 of the relay S3 serve as two output ends of the first current channel control circuit and are connected with the second current regulating circuit.

8. The power meter device based on seamless switching of multiple splitters of claim 1, wherein: The second current channel control circuit comprises a relay S4, the relay S4 is a double-pole double-throw relay, a pin 1 of the relay S4 is connected with an output end of the first current regulating circuit, a pin 3 of the relay S4 is connected with an output end of the second current regulating circuit; a pin 4 of the relay S4 is connected with a positive electrode end of a diode D8, a pin 5 of the relay S4 is connected with a negative electrode end of the diode D8, the pin 4 of the relay S4 is connected with a collector of a transistor Q2, an emitter of the transistor Q2 is grounded, a base of the transistor Q2 is connected with the main DSP controller, and a pin 2 of the relay S4 serves as an output end of the second current channel control circuit and is connected with the second PGA.

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