Overcurrent protection circuit, LDO circuit and chip

Abstract

The utility model discloses an overcurrent protection circuit, an LDO (Low Dropout Regulator) circuit and a chip. The overcurrent protection circuit comprises a mirror image module, a first current source, a comparison module and an adjusting module, the mirroring module is connected with the second end of the output tube of the LDO circuit and used for mirroring current on the output tube to generate mirroring current. The first current source is used for generating reference current. The comparison module is connected with the mirror image module and the first current source and used for comparing the mirror image current with the reference current to generate a comparison signal. The adjusting module is connected with the comparison module and the output end of the amplifier of the LDO circuit and used for adjusting the output voltage of the amplifier of the LDO circuit based on the comparison signal. According to the overcurrent protection circuit, the LDO circuit and the chip, the function of limiting the output current of the output tube to a certain fixed value during overcurrent or when the output of the LDO is short-circuited is achieved in a current comparison mode, and the chip is prevented from being burnt due to the fact that the current of the output tube is too large.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, specifically relating to an overcurrent protection circuit, an LDO circuit, and a chip. Background Technology

[0002] LDO circuits are power supply chips with stable and reliable power conversion capabilities. They are widely used in various industries due to their small size, low noise, high power supply rejection ratio, and fast transient response.

[0003] An LDO circuit typically includes a voltage reference, an error amplifier, a buffer, an output transistor, a feedback unit, and a protection circuit. The protection circuit should be switched off during normal system operation and consume as little quiescent current as possible. It functions to prevent system malfunctions, allowing the system to recover from the abnormal state and thus improving the reliability of the LDO circuit.

[0004] When an LDO circuit is working, it may face situations such as output short circuit or excessive load current, which may cause the output transistor to burn out. Therefore, the overcurrent protection circuit is particularly important.

[0005] Current overcurrent protection technology converts current into voltage and compares it with a reference voltage to determine whether to perform overcurrent protection. This approach makes the circuit complex and directly shutting down the chip during an overcurrent will affect the chip's restart time.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0007] The purpose of this invention is to provide an overcurrent protection circuit, an LDO circuit, and a chip, which can limit the output current of the LDO's output transistor when the LDO is overcurrent by means of current comparison.

[0008] To achieve the above objectives, the technical solution provided by a specific embodiment of this utility model is as follows:

[0009] An overcurrent protection circuit for an LDO circuit, the overcurrent protection circuit comprising: a mirror module, a first current source, a comparison module, and an adjustment module.

[0010] The mirror module is connected to the second terminal of the output transistor of the LDO circuit to mirror the current on the output transistor of the LDO circuit and generate a mirror current; the first current source is used to generate a reference current; the comparator module is connected to the mirror module and the first current source to compare the mirror current and the reference current and generate a comparison signal; the adjustment module is connected to the comparator module and the output terminal of the amplifier of the LDO circuit to adjust the output voltage of the amplifier of the LDO circuit based on the comparison signal.

[0011] In one or more embodiments of this utility model, the mirror module includes a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a power supply voltage. A second terminal of the first transistor, a control terminal of the first transistor, and a control terminal of the second transistor are connected to a second terminal of the output transistor of the LDO circuit. The second terminal of the second transistor is used to generate a mirror current; or

[0012] The mirror module includes a first transistor, a second transistor, a first resistor, and a second resistor. The first terminals of the first and second resistors are connected to a power supply voltage. The second terminal of the first resistor is connected to the first terminal of the first transistor. The second terminal of the second resistor is connected to the first terminal of the second transistor. The second terminal of the first transistor, the control terminal of the first transistor, and the control terminal of the second transistor are connected to the second terminal of the output transistor of the LDO circuit. The second terminal of the second transistor is used to generate a mirror current; or

[0013] The mirror module includes a common-source cascode current mirror.

[0014] In one or more embodiments of the present invention, the comparison module includes a third transistor, the first terminal of the third transistor is connected to ground voltage, and the second terminal and the control terminal of the third transistor are connected to a mirror module and a first current source to generate a comparison signal.

[0015] In one or more embodiments of the present invention, the comparison module further includes a third resistor, the first end of which is connected to ground voltage, and the second end of which is connected to the first end of a third transistor.

[0016] In one or more embodiments of the present invention, the adjustment module includes a fourth transistor, the first terminal of the fourth transistor is connected to ground voltage, the control terminal of the fourth transistor is connected to a comparison module to receive a comparison signal, and the second terminal of the fourth transistor is connected to the output terminal of the amplifier of the LDO circuit.

[0017] In one or more embodiments of the present invention, the adjustment module further includes a fourth resistor, the first end of which is connected to ground voltage, and the second end of which is connected to the first end of a fourth transistor.

[0018] This utility model also provides an LDO circuit, including an amplifier, an output transistor, a feedback unit, and the aforementioned overcurrent protection circuit. The output terminal of the amplifier is connected to the control terminal of the output transistor, the feedback unit is connected to the first terminal of the output transistor to form the output terminal of the LDO circuit, and the feedback unit is connected to the second input terminal of the amplifier to provide a feedback voltage.

[0019] In one or more embodiments of this utility model, the LDO circuit further includes a buffer stage, the input terminal of which is connected to the output terminal of the amplifier, and the output terminal of which is connected to the control terminal of the output transistor.

[0020] In one or more embodiments of this utility model, the buffer stage includes a fifth transistor and a second current source. The first terminal of the second current source is connected to ground voltage. The second terminal of the second current source and the first terminal of the fifth transistor are connected to the control terminal of the output transistor. The second terminal of the fifth transistor is connected to the power supply voltage. The control terminal of the fifth transistor is connected to the output terminal of the amplifier.

[0021] This utility model also provides a chip, including the overcurrent protection circuit and / or the LDO circuit described above.

[0022] Compared with existing technologies, the overcurrent protection circuit, LDO circuit, and chip of this invention utilize current comparison to limit the output current of the output transistor to a fixed value when there is an overcurrent or when the LDO circuit output is short-circuited, preventing excessive current on the output transistor from burning out the chip. The circuit structure is simple, and the overcurrent threshold and maximum current limit can be precisely adjusted by adjusting parameters. Compared with protection circuits that directly control the gate of the output transistor through a switching transistor after current comparison, the overcurrent protection circuit of this invention contains only one pole, making the circuit easier to stabilize, and the fixed current value is easier to control precisely. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a circuit diagram of an LDO circuit in one embodiment of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0026] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. Indirect connections are those made through an intermediate medium, such as those made through an electrically conductive medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this specification, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0027] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.

[0028] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0029] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0030] Various components and devices may be referred to or shown in the singular (e.g., “MOS transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0031] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0032] like Figure 1 As shown, the LDO circuit in one embodiment of this utility model includes an amplifier 10, a buffer stage 20, an output transistor Q1, a feedback unit 30, and an overcurrent protection circuit.

[0033] The amplifier 10 has a first input terminal for receiving a reference voltage VREF. The output terminal of the amplifier 10 is connected to the input terminal of the buffer stage 20. The output terminal of the buffer stage 20 is connected to the control terminal of the output transistor Q1. The first terminal of the output transistor Q1 is connected to the feedback unit 30 to form the output terminal of the LDO circuit to generate an output voltage VOUT. The feedback unit 30 is connected to the second input terminal of the amplifier 10 to generate a feedback voltage VFB based on the output voltage VOUT.

[0034] like Figure 1 As shown, amplifier 10 includes an input stage and an amplification stage connected together, which together form a folded cascode amplifier.

[0035] Specifically, the input stage includes the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8.

[0036] The first terminal of the sixth transistor M6 is connected to the power supply voltage VDD. The second terminal of the sixth transistor M6 is connected to the second terminals of the seventh transistor M7 and the eighth transistor M8. The control terminal of the sixth transistor M6 is used to receive the first bias voltage VBIAS. The control terminal of the seventh transistor M7 is connected to the feedback unit to form the second input terminal of the amplifier 10. The control terminal of the eighth transistor M8 is used to form the first input terminal of the amplifier 10. The first terminals of the seventh transistor M7 and the eighth transistor M8 are respectively connected to the amplification stage.

[0037] The amplification stage includes the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14.

[0038] The first terminal of the ninth transistor M9 and the first terminal of the tenth transistor M10 are connected to the power supply voltage VDD. The control terminal of the ninth transistor M9, the second terminal of the ninth transistor M9, the control terminal of the tenth transistor M10, and the second terminal of the eleventh transistor M11 are connected to receive the second bias voltage VBP. The second terminal of the tenth transistor M10 is connected to the second terminal of the twelfth transistor M12 to form the output terminal of the amplifier. The control terminal of the eleventh transistor M11 is connected to the control terminal of the twelfth transistor M12 to receive the third bias voltage VBN1. The first terminal of the eleventh transistor M11 and the second terminal of the thirteenth transistor M13 are connected to the first terminal of the eighth transistor M8. The first terminal of the twelfth transistor M12 and the second terminal of the fourteenth transistor M14 are connected to the first terminal of the seventh transistor M7. The control terminal of the thirteenth transistor M13 is connected to the control terminal of the fourteenth transistor M14 to receive the fourth bias voltage VBN2. The first terminal of the thirteenth transistor M13 and the first terminal of the fourteenth transistor M14 are connected to the ground voltage GND.

[0039] In other embodiments, amplifier 10 may also employ other amplification circuit structures.

[0040] like Figure 1 As shown, buffer stage 20 includes a fifth transistor M5 and a second current source I2. The first terminal of the second current source I2 is connected to the ground voltage GND. The second terminal of the second current source I2 and the first terminal of the fifth transistor M5 are connected to the control terminal of the output transistor Q1 to form the output terminal of buffer stage 20. The second terminal of the fifth transistor M5 is connected to the power supply voltage VDD. The control terminal of the fifth transistor M5 is connected to the second terminal of the tenth transistor M10 to form the input terminal of buffer stage 20.

[0041] like Figure 1 As shown, the feedback unit 30 includes a fifth resistor R5 and a sixth resistor R6. The first end of the fifth resistor R5 is connected to the first end of the output transistor Q1, the second end of the fifth resistor R5 and the first end of the sixth resistor R6 are connected to the control terminal of the seventh transistor M7 to generate a feedback voltage VFB, and the second end of the sixth resistor R6 is connected to the ground voltage GND.

[0042] like Figure 1 As shown, the overcurrent protection circuit includes a mirror module 41, a first current source I1, a comparison module 42, and an adjustment module 43.

[0043] The image module 41 is connected to the second terminal of the output transistor Q1 and is used to mirror the current on the output transistor Q1 to generate a mirrored current. The first terminal of the first current source I1 is connected to ground voltage GND, and the second terminal of the first current source I1 is connected to the image module 41. The first current source I1 is used to generate a reference current Iref. The comparison module 42 is connected to the image module 41 and the second terminal of the first current source I1. The comparison module 42 is used to compare the mirrored current and the reference current Iref to generate a comparison signal. The adjustment module 43 is connected to the comparison module 42 and the output terminal of the amplifier 10. The adjustment module 43 is used to adjust the output voltage of the amplifier 10 based on the comparison signal.

[0044] like Figure 1 As shown, the mirror module 41 includes a first transistor M1, a second transistor M2, a first resistor R1, and a second resistor R2.

[0045] The first terminal of the first resistor R1 and the first terminal of the second resistor R2 are connected to the power supply voltage VDD. The second terminal of the first resistor R1 is connected to the first terminal of the first transistor M1, and the second terminal of the second resistor R2 is connected to the first terminal of the second transistor M2. The second terminal of the first transistor M1, the control terminal of the first transistor M1, and the control terminal of the second transistor M2 are connected to the second terminal of the output transistor Q1. The second terminal of the second transistor M2 is used to generate a mirror current.

[0046] In other embodiments, the first resistor R1 and the second resistor R2 may not be provided, and the first terminal of the first transistor M1 and the first terminal of the second transistor M2 may be directly connected to the power supply voltage VDD.

[0047] In other embodiments, the mirror module 41 may also employ a current mirror such as a cascode current mirror or other structures.

[0048] like Figure 1 As shown, the comparison module 42 includes a third transistor M3 and a third resistor R3. The first terminal of the third resistor R3 is connected to the ground voltage GND, and the second terminal of the third resistor R3 is connected to the first terminal of the third transistor M3. The second terminal of the third transistor M3, the control terminal of the third transistor M3, the second terminal of the second transistor M2, the second terminal of the first current source I1, and the adjustment module 43 are connected to generate a comparison signal.

[0049] In other embodiments, the third resistor R3 may be omitted, and the first terminal of the third transistor M3 may be directly connected to the ground voltage GND.

[0050] like Figure 1As shown, the adjustment module 43 includes a fourth transistor M4 and a fourth resistor R4. The first terminal of the fourth resistor R4 is connected to ground voltage GND, and the second terminal of the fourth resistor R4 is connected to the first terminal of the fourth transistor M4. The control terminal of the fourth transistor M4 is connected to the control terminal of the third transistor M3 to receive a comparison signal, and the second terminal of the fourth transistor M4 is connected to the output terminal of the amplifier 10.

[0051] In other embodiments, the fourth resistor R4 may be omitted, and the first terminal of the fourth transistor M4 may be directly connected to the ground voltage GND.

[0052] It can be seen that the third transistor M3, the third resistor R3, the fourth transistor M4 and the fourth resistor R4 form a current mirror. When the mirror current generated by the mirror module 41 is greater than the reference current Iref, this current mirror can replicate the current difference between the mirror current and the reference current Iref.

[0053] In other embodiments, the comparison module 42 and the adjustment module 43 may also form a current mirror with other structures, such as a cascode current mirror.

[0054] In one embodiment, the first transistor M1, the second transistor M2, the sixth transistor M6, the ninth transistor M9, and the tenth transistor M10 are P-channel MOSFETs, and the output transistor Q1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are N-channel MOSFETs.

[0055] The first terminal of the first transistor M1, the first terminal of the second transistor M2, the first terminal of the third transistor M3, the first terminal of the fourth transistor M4, the first terminal of the fifth transistor M5, the first terminal of the sixth transistor M6, the first terminal of the seventh transistor M7, the first terminal of the eighth transistor M8, the first terminal of the ninth transistor M9, the first terminal of the tenth transistor M10, the first terminal of the eleventh transistor M11, the first terminal of the twelfth transistor M12, the first terminal of the thirteenth transistor M13, the first terminal of the fourteenth transistor M14, and the first terminal of the output transistor Q1 are the sources; the second terminals of the first transistor M1, the second terminal of the second transistor M2, the second terminal of the third transistor M3, the second terminal of the fourth transistor M4, the second terminal of the fifth transistor M5, the second terminal of the sixth transistor M6, the second terminal of the seventh transistor M7, and the second terminal of the eighth transistor M8 are the sources. The second terminals of the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the output transistor Q1 are the drains; the control terminals of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the output transistor Q1 are the gates.

[0056] In other embodiments, the first transistor M1, the second transistor M2, the sixth transistor M6, the ninth transistor M9, and the tenth transistor M10 can also be N-channel MOSFETs or other devices, and the output transistor Q1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 can also be P-channel MOSFETs or other devices, and their connection methods are all adapted accordingly.

[0057] like Figure 1 As shown, when the output current on the output transistor Q1 is small, the mirror current generated by the mirror module 41 is less than the reference current Iref. At this time, there is no current on the third transistor M3 and the fourth transistor M4, which does not affect the output voltage of the amplifier 10.

[0058] When the output current on output transistor Q1 exceeds the overcurrent threshold, the mirror current begins to exceed the reference current Iref. The current difference between the mirror current and the reference current Iref flows to the third transistor M3. The current difference is replicated by the current mirror composed of the third transistor M3 and the fourth transistor M4 and the corresponding current is drawn from the output terminal of amplifier 10, which reduces the output voltage of amplifier 10. As a result, the output voltage of buffer stage 20 also decreases, reducing the rate of increase of the output current of output transistor Q1. This continues until the current drawn from the output terminal of amplifier 10 by the fourth transistor M4 is equal to the maximum current that can flow through the tenth transistor M10. At this point, the output current of output transistor Q1 no longer increases and remains at a fixed value.

[0059] Overcurrent threshold I of power transistor Q1 Q1th It can be done through I Q1th =I1*N, where N is the mirror ratio of the current mirror formed by the first transistor M1 and the second transistor M2.

[0060] Assuming the maximum current that can flow through the tenth transistor M10 is I0, then the maximum current limiting value I of the output transistor Q1 is... Q1max For: I Q1max = (I0*M+I1)*N, where M is the mirror ratio of the current mirror formed by the third transistor M3 and the fourth transistor M4.

[0061] By adjusting the values ​​of M, N, and I1 in the above formula, the overcurrent threshold and the maximum current limit of the output tube Q1 can be adjusted, thereby achieving precise adjustment of overcurrent protection.

[0062] This utility model also discloses a chip, including the above-mentioned overcurrent protection circuit or LDO circuit.

[0063] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0064] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An overcurrent protection circuit for an LDO circuit, characterized in that, The over-current protection circuit comprises: The mirror module is connected with the second end of the output tube of the LDO circuit, and is used for mirroring the current on the output tube to generate a mirror current; The first current source is used for generating a reference current; The comparison module is connected with the mirror module and the first current source, and is used for comparing the mirror current and the reference current to generate a comparison signal; and The adjustment module is connected with the comparison module and the output end of the amplifier of the LDO circuit, and is used for adjusting the voltage of the output end of the amplifier based on the comparison signal.

2. The overcurrent protection circuit of claim 1, wherein, The mirror module comprises a first transistor and a second transistor, the first end of the first transistor and the first end of the second transistor are connected with a power supply voltage, the second end of the first transistor, the control end of the first transistor and the control end of the second transistor are connected with the second end of the output tube, and the second end of the second transistor is used for generating the mirror current; Or The mirror module comprises a first transistor, a second transistor, a first resistor and a second resistor, the first end of the first resistor and the first end of the second resistor are connected with a power supply voltage, the second end of the first resistor is connected with the first end of the first transistor, the second end of the second resistor is connected with the first end of the second transistor, the second end of the first transistor, the control end of the first transistor and the control end of the second transistor are connected with the second end of the output tube, and the second end of the second transistor is used for generating the mirror current; or The mirror module comprises a common-source common-gate current mirror.

3. The overcurrent protection circuit of claim 1, wherein, The comparison module comprises a third transistor, the first end of the third transistor is connected with a ground voltage, and the second end of the third transistor and the control end of the third transistor are connected with the mirror module and the first current source to generate the comparison signal.

4. The overcurrent protection circuit of claim 3, wherein, The comparison module further comprises a third resistor, the first end of the third resistor is connected with the ground voltage, and the second end of the third resistor is connected with the first end of the third transistor.

5. The overcurrent protection circuit of claim 1, wherein, The adjustment module comprises a fourth transistor, the first end of the fourth transistor is connected with the ground voltage, the control end of the fourth transistor is connected with the comparison module to receive the comparison signal, and the second end of the fourth transistor is connected with the output end of the amplifier.

6. The overcurrent protection circuit of claim 5, wherein, The adjustment module further comprises a fourth resistor, the first end of the fourth resistor is connected with the ground voltage, and the second end of the fourth resistor is connected with the first end of the fourth transistor.

7. An LDO circuit, characterized by comprising: The LDO circuit further comprises a buffer stage, the input end of the buffer stage is connected with the output end of the amplifier, and the output end of the buffer stage is connected with the control end of the output tube.

8. The LDO circuit of claim 7, wherein, The buffer stage comprises a fifth transistor and a second current source, the first end of the second current source is connected with the ground voltage, the second end of the second current source and the first end of the fifth transistor are connected with the control end of the output tube, the second end of the fifth transistor is connected with the power supply voltage, and the control end of the fifth transistor is connected with the output end of the amplifier.

9. The LDO circuit of claim 8, wherein, ​ 10. A chip, characterized by An overcurrent protection circuit according to any one of claims 1 to 6 and / or an LDO circuit according to any one of claims 7 to 9.

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