Semiconductor device

Abstract

The semiconductor device provided by the embodiment of the utility model comprises a plurality of source / drain regions. The semiconductor device includes a plurality of source / drain contacts disposed over front sides of the source / drain regions, respectively. The source / drain contact is electrically coupled to the source / drain region. The semiconductor device includes a plurality of via holes disposed over a backside of the source / drain contact, respectively. The back side is opposite the front side. The via hole is electrically coupled to the source / drain contact.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have spawned several generations of ICs, each featuring smaller and more complex circuits than the previous one. Throughout IC development, functional density (the number of interconnects per chip area) has generally increased, while geometric dimensions (the smallest components (or lines) that can be created using manufacturing processes) have decreased. This scaling down process typically offers advantages such as increased production efficiency and reduced associated costs.

[0003] As process technology scales down, certain challenges may arise. For example, vias can be formed to provide electrical connections to components within an IC. However, when certain types of vias are formed on epitaxially grown semiconductor regions, they can increase parasitic resistance, which is undesirable. As IC manufacturing advances to newer technology nodes and via sizes continue to shrink, this problem may be exacerbated.

[0004] Therefore, while semiconductor devices and their manufacturing methods are generally sufficient to meet their intended purpose, they are not entirely satisfactory in every aspect. Utility Model Content

[0005] According to one embodiment of the present invention, a semiconductor device includes a plurality of source / drain regions, a plurality of source / drain contacts, and a plurality of vias. The plurality of source / drain contacts are respectively disposed above the front side of the source / drain regions, wherein the source / drain contacts are electrically coupled to the source / drain regions. The plurality of vias are respectively disposed above the back side of the source / drain contacts, wherein the back side is opposite to the front side, and wherein the vias are electrically coupled to the source / drain contacts.

[0006] According to one embodiment of the present invention, a semiconductor device includes a semiconductor substrate, a gate structure, a first epitaxial layer and a second epitaxial layer, a first conductive contact and a second conductive contact, and a via. In a side cross-sectional view, the gate structure is located above a first side of the semiconductor substrate. In the side cross-sectional view, the first epitaxial layer and the second epitaxial layer are each located above the first side of the semiconductor substrate, wherein in the side cross-sectional view, the gate structure is located between the first epitaxial layer and the second epitaxial layer. The first conductive contact and the second conductive contact are respectively located above the first side of the first epitaxial layer and the second epitaxial layer, wherein in the side cross-sectional view, the first conductive contact protrudes into the first epitaxial layer, and wherein in the side cross-sectional view, the second conductive contact protrudes into the second epitaxial layer. The via is located above a second side of the gate structure, the second side being opposite to the first side, wherein a first segment of the via extends vertically through the semiconductor substrate and protrudes into the gate structure, and wherein a second segment of the via extends vertically through the second epitaxial layer and directly contacts the second conductive contact. Attached Figure Description

[0007] This disclosure can be better understood when read in conjunction with the accompanying drawings in the following detailed description. It should be emphasized that, according to industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion. Furthermore, it should be emphasized that the drawings only show typical embodiments of the present invention and should not be considered as limiting the scope of the claim, as the present invention can be equally applied to other embodiments.

[0008] Figure 1A A three-dimensional perspective view of a finned FET device is shown.

[0009] Figure 1B A top view of the finned FET assembly is shown.

[0010] Figure 1C A three-dimensional perspective view of a multichannel gate all-around (GAA) device is shown.

[0011] Figures 2 to 7 A series of Y-cut cross-sectional views of a semiconductor device at various stages or manufacturing locations according to embodiments of this disclosure are shown.

[0012] Figures 8 to 9 A series of X-ray cross-sectional views of a semiconductor device at various stages or manufacturing locations according to embodiments of this disclosure are shown.

[0013] Figure 10 This is a block diagram of a manufacturing system according to various aspects of embodiments of the present disclosure.

[0014] Figure 11 This is a flowchart illustrating a method for manufacturing a semiconductor device according to various aspects of embodiments of the present disclosure. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or instances for implementing various features of this utility model. Specific examples of components and configurations described below are for the purpose of simplifying this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms are used herein to describe the relationship between one component or feature and another, as illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of components during use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0017] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to cover values ​​within a reasonable range, such as within ±10%, taking into account the variations inherent in the manufacturing process as understood by those skilled in the art. This also applies to the numbers described or other values ​​understood by those skilled in the art. For example, the term "about 5 nanometers" covers a size range from 4.5 nanometers to 5.5 nanometers.

[0018] This disclosure generally relates to specific manufacturing processes for forming back-side vias directly on the source / drain contacts. More specifically, the vias may be formed on the back side of an integrated circuit (IC) device. If such back-side vias are formed on epitaxially grown semiconductor regions (e.g., the source / drain regions of a transistor), it can result in higher resistance, which is undesirable as it can adversely affect device performance, such as speed. Therefore, this disclosure describes various manufacturing processes performed to ensure that the back-side vias are formed on the source / drain contacts. Doing so reduces the resistance of the integrated circuit device, thereby improving its performance.

[0019] Now refer to Figure 1A , Figure 1B , Figure 1C , Figures 2 to 11 Various aspects of the embodiments disclosed herein are discussed below. In more detail, Figures 1A to 1B An example finned FET device is shown, and Figure 1C An example GAA device is shown. Figures 2 to 7 The illustration shows a Y-cut sectional side view of an integrated circuit device at various stages or manufacturing locations according to embodiments of this disclosure. Figures 8 to 9 The images show X-ray cross-sectional side views of integrated circuit devices at various stages or manufacturing locations according to embodiments of this disclosure. Figure 10 A semiconductor manufacturing system is shown that can be used to manufacture integrated circuit devices according to embodiments of this disclosure. Figure 11 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure is shown.

[0020] Now for reference Figure 1A and Figure 1B The images show a three-dimensional perspective view and a top view of a portion of an integrated circuit (IC) device 90. The IC device 90 is implemented using field-effect transistors (FETs), such as a three-dimensional fin-wire FET (fin FET). A fin FET device has a semiconductor fin structure that protrudes vertically from the substrate. The fin structure is an active region, forming source / drain regions and / or channel regions. Depending on the context, source / drain regions can refer to the source or drain individually or collectively. Source / drain regions can also refer to regions that provide source and / or drain for multiple device regions. A gate structure partially surrounds the fin structure. In recent years, fin FET devices have gained popularity due to their enhanced performance compared to conventional planar transistors.

[0021] like Figure 1AAs shown, the integrated circuit device 90 includes a substrate 110. The substrate 110 may include elemental (single-element) semiconductors, such as silicon, germanium, and / or other suitable materials; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 may be a single-layer material having a uniform composition. Alternatively, the substrate 110 may include multiple material layers having similar or different compositions suitable for manufacturing integrated circuit devices. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source / drain regions, may be formed in or on the substrate 110. The doped region can be doped with n-type dopants, such as phosphorus or arsenic, and / or p-type dopants, such as boron, depending on the design requirements. The doped region can be formed directly on the substrate 110, in a p-well structure, an n-well structure, a double-well structure, or using a bump structure. The doped region can be formed by implanting dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0022] A three-dimensional active region 120 is formed on a substrate 110. The active region 120 may include an elongated, fin-like structure projecting upward from the substrate 110. Therefore, the active region 120 may be interchangeably referred to below as fin structure 120 or fin 120. The fin structure 120 may be fabricated using a suitable process including photolithography and etching processes. The photolithography process may include forming a photoresist layer covering the substrate 110, exposing the photoresist to form a pattern, performing a post-exposure baking process, and developing the photoresist to form a masking assembly (not shown) including the photoresist. The substrate 110 is then etched indented using a photomask assembly, leaving the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed by a dual-patterning or multi-patterning process. Generally, dual-patterning or multi-patterning processes combine photolithography and self-aligned processes to create patterns, for example, with a smaller pitch than that obtained using direct photolithography with a single photolithography process. As an example, layers can be formed over a substrate and patterned using photolithography. Spacers are formed along the patterned layers using a self-aligned process. The layers are then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 120.

[0023] The integrated circuit device 90 also includes source / drain members 122 formed over the fin structure 120. Depending on the context, the source / drain member 122 (also referred to as a source / drain region) may refer individually or collectively to the source or drain of a transistor. The source / drain member 122 may include an epitaxial layer epitaxially grown on the fin structure 120. The integrated circuit device 90 also includes an isolation structure 130 formed over the substrate 110. The isolation structure 130 electrically isolates the various components of the integrated circuit device 90. The isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-dielectric-constant dielectric materials, and / or other suitable materials. In some embodiments, the isolation structure 130 may include shallow trench isolation (STI) features. In one embodiment, the isolation structure 130 is formed by etching trenches in the substrate 110 during the formation of the fin structure 120. The trenches can then be filled with the isolation material described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structures (such as field oxides, localized oxidation of silicon (LOCOS), and / or other suitable structures) can also be implemented as isolation structure 130. Alternatively, isolation structure 130 may include a multilayer structure, for example, having one or more thermal oxide substrates.

[0024] The integrated circuit device 90 also includes a gate structure 140 formed over and engaged with the fin structures 120, the gate structure 140 being located on three sides of the channel region of each fin 120. In other words, each gate structure 140 surrounds a plurality of fin structures 120. The gate structures 140 may be dummy gate structures (e.g., comprising an oxide gate dielectric layer and a polysilicon gate), or they may be high-k dielectric metal gate (HKMG) structures comprising a high-k dielectric gate dielectric layer and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not depicted herein, the gate structure 140 may include additional material layers, such as interface layers, capping layers, other suitable layers, or combinations thereof on the fin structures 120.

[0025] refer to Figures 1A to 1B The plurality of fin structures 120 are each longitudinally oriented along the X direction, and the plurality of gate structures 140 are each longitudinally oriented along the Y direction, i.e., substantially perpendicular to the fin structures 120. In many embodiments, the integrated circuit device 90 includes additional features such as gate gap walls along the sidewalls of the gate structures 140, a hard mask layer disposed above the gate structures 140, and many other features.

[0026] Figure 1C A three-dimensional perspective view of an example multichannel gate-all-around (GAA) device 150 is shown. The GAA device has multiple elongated nanostructured channels that can be realized as nanotubes, nanosheets, or nanowires. For reasons of consistency and clarity, Figure 1C and Figures 1A to 1B Similar components will be labeled with the same symbols. For example, active regions such as fin structure 120 rise vertically upwards from substrate 110 in the Z direction. Isolation structure 130 provides electrical separation between fin structures 120. Gate structure 140 is located above fin structure 120 and isolation structure 130. Layer 155 is located above gate structure 140, and gate spacer structure 160 is located on the sidewall of gate structure 140. Capping layer 165 is formed above fin structure 120 to protect fin structure 120 from oxidation during the formation of isolation structure 130.

[0027] Multiple nanostructures 170 are disposed above each of the fin structures 120. The nanostructures 170 may include nanosheets, nanotubes, or nanowires, or other types of nanostructures extending horizontally in the X direction. A portion of the nanostructures 170 below the gate structure 140 may serve as a channel for the GAA device 150. Dielectric internal spacer walls 175 may be disposed between the nanostructures 170. Additionally, although not shown for simplicity, each stack of nanostructures 170 may be circumferentially surrounded by a gate dielectric layer and a gate electrode. In the illustrated embodiment, a portion of the nanostructures 170 outside the gate structure 140 may serve as a source / drain feature of the GAA device 150. However, in some embodiments, continuous source / drain features may be epitaxially grown over a portion of the fin structure 120 outside the gate structure 140. Regardless, conductive power / drain contacts 180 may be formed above the source / drain features to provide electrical connection. An interlayer dielectric (ILD) 185 is formed over the isolation structure 130 to surround the gate structure 140 and the source / drain contacts 180. ILD 185 may be referred to as an ILD0 layer. In some embodiments, ILD 185 may comprise silicon oxide, silicon nitride, or a low-dielectric-constant dielectric material.

[0028] Figures 1A to 1B Fin-type FET devices and Figure 1C GAA devices can be used to implement electrical circuits with various functions, such as storage devices (e.g., static random access memory (SRAM) devices), logic circuits, input / output (I / O) devices, application-specific integrated circuit (ASIC) devices, radio frequency (RF) circuits, drivers, microcontrollers, central processing units (CPUs), image sensors, etc., as non-limiting examples.

[0029] Figures 2 to 7 Schematic fragment cross-sectional views of portions of an integrated circuit device 200 at various stages or manufacturing locations according to embodiments of this disclosure are shown. More specifically, Figures 2 to 7 A cross-sectional view along the YZ plane is shown, which is along... Figures 1A to 1C The tangent A-A' is shown in the diagram. Therefore, Figures 2 to 7It can be called a Y-cut or Y-cut sectional view.

[0030] Now for reference Figure 2 The integrated circuit device 200 has a side 210 and a side 211 opposite to the side 210. In the illustrated embodiment, side 210 is the front side, and may be interchangeably referred to as front side 210 below. Side 211 is the back side, and may be interchangeably referred to as back side 211 below.

[0031] Integrated circuit device 200 may include a plurality of transistors, such as those referred to above in some embodiments. Figure 1A and Figure 1B The fin FET transistor discussed, or in some embodiments referred to above, is... Figure 1C The gate-all-around (GAA) transistor is discussed. Figure 2 The side cross-sectional view shows multiple source / drain regions 220, 221, 222, and 223 of various transistors. Source / drain regions 220-223 can be referenced above. Figures 1A to 1C The embodiments of the source / drain component 122 discussed are described below. Similarly, depending on the context, each source / drain region 220-223 may individually or collectively refer to the source or drain of a transistor. Source / drain regions 220-223 may include epitaxial layers epitaxially grown on upper semiconductor materials 230, 231, 232, and 233, respectively, which may include silicon. In some embodiments, semiconductor materials 230-233 may include portions of a semiconductor substrate, such as active regions. For example, active regions may include those referenced above. Figures 1A to 1C The portion of fin structure 120 discussed.

[0032] Conductive contacts may be formed above the front side 210 of the source / drain regions 220-223 to provide electrical connections to the source / drain regions 220-223. For example, multiple source / drain contacts 250, 251, and 252 may be formed. Source / drain contact 250 is formed above the front side 210 of the source / drain regions 220, source / drain contact 251 is formed above the front side 210 of the source / drain regions 221 and 222, and source / drain contact 253 is formed above the front side 210 of the source / drain region 223. The source / drain contacts 250, 251, and 253 may be formed by etching to expose openings in the front side 210 of the source / drain regions 220-223, and then filling the etched openings with one or more conductive materials (e.g., cobalt or tungsten).

[0033] Source / drain regions 220 and 221 are electrically and physically isolated from each other by a shallow trench isolation (STI) structure 260, source / drain regions 221 and 222 are electrically and physically isolated from each other by an STI structure 261, and source / drain regions 222 and 223 are electrically and physically isolated from each other by a shallow trench isolation (STI) structure 262. Note that STI 261 is formed above the back side 211 of source / drain contact 251. Source / drain contacts 250 and 251 are electrically and physically isolated from each other by STI structure 260 and interlayer dielectric (ILD) 270. Source / drain contacts 251 and 253 are electrically and physically isolated from each other by STI structure 262 and interlayer dielectric 272.

[0034] STI structures 260-262 and interlayer dielectric layers 270-272 may comprise silicon oxide or another suitable type of dielectric material. In some embodiments, STI structures 260-262 and interlayer dielectric layers 270-272 have different material compositions. In other embodiments, STI structures 260-262 and interlayer dielectric layers 270-272 may contain the same type of dielectric material. It should be understood that the formation of source / drain contacts 250, 251, and 253 may involve etching at least partially through openings in interlayer dielectric layers 270-272 and / or STI structures 260-262, such that the etched openings expose source / drain regions 220-223 to the front side 210. These etched openings are then filled with a conductive material to form source / drain contacts 250, 251, and 253.

[0035] Despite Figure 2While not directly visible in the Y-section view, it is understood that the transistors of the integrated circuit device 200 also include gate structures. In some embodiments, the gate structure may be implemented as a high-dielectric-constant metal gate (HKMG) structure. For example, each HKMG structure may partially surround one of the active regions (e.g., surround a fin structure). As described above, HKMG structures are formed by replacing dummy gate structures, and they may each include a high-dielectric-constant gate dielectric layer and a metal-containing gate electrode. Examples of high-dielectric-constant gate dielectric layer materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or combinations thereof. The metal-containing gate may include one or more work function metal layers and one or more filler metal layers. The work function metal layers may be configured to adjust the work function of the corresponding transistor. Examples of materials for the work function metal layer may include titanium nitride (TiN), titanium aluminum nitride (TiAl), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminum nitride (TiAlN), zirconium aluminum nitride (ZrAl), tungsten aluminum nitride (WAl), tantalum aluminum nitride (TaAl), hafnium aluminum nitride (HfAl), or combinations thereof. The filler metal layer may serve as the main conductive portion of the gate layer. The gate structure may include additional material layers, such as an interface layer between the active region and the gate dielectric layer.

[0036] Still referencing Figure 2 Interconnection structure 300 is formed on the front side 210 of integrated circuit device 200 to provide electrical connections to various components of integrated circuit device 200. More specifically, interconnection structure 300 includes multiple electrically insulating layers, such as etch stop layer 310, interlayer dielectric layer 320, and dielectric layer 330. Each of these layers 310, 320, or 330 may include an electrically insulating material of a suitable type, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, fluoride-doped silicate glass (FSG), low dielectric constant dielectric material, or combinations thereof.

[0037] The interconnect structure 300 also includes multiple electrically conductive members. For example, the interconnect structure 300 may include a via 350 embedded in and extending vertically through the etch stop layer 310 and the interlayer dielectric layer 320. The via 350 is also electrically coupled to the front side 210 of the source / drain contact 251; therefore, the via 350 may also be referred to as a source / drain via 350. The interconnect structure 300 also includes multiple metal lines, such as metal lines 360 and 370. Metal line 360 ​​is a metal line of the metal-0 (also referred to as M0) metal layer, and metal line 370 is a metal line of the metal-1 (also referred to as M1) metal layer. Metal lines 360 and 370 may be embedded in the dielectric layer 330, which provides electrical isolation between each metal line 360 ​​and 370 and its adjacent metal lines. Note that some of metal lines 360 and some of metal lines 370 are electrically coupled together.

[0038] It should be understood that after the source / drain contacts 250, 251, and 253 are formed, the interconnect structure 300 is formed as part of the integrated circuit device 200. In other words, the interconnect structure 300 can be formed over the front side 210 of the integrated circuit device 200 using a stacked method, such that the components of the interconnect structure 300 (e.g., source / drain vias 350) are at least partially electrically connected to the source / drain regions 220-223 through the source / drain contacts 250, 251, and 253 (from the front side 210).

[0039] Still referencing Figure 2 One or more thinning processes 400 can be performed on the back side 211 of the integrated circuit device 200. Therefore, the one or more thinning processes 400 can also be referred to as back-side thinning processes. In some embodiments, the one or more thinning processes 400 may include one or more chemical etching processes and / or one or more mechanical polishing processes to reduce the thickness of the integrated circuit device 200 by partially removing its material. For example, the chemical etching process and / or mechanical polishing process may etch or grind away portions of the substrate in the integrated circuit device 200, which in some embodiments may be portions of a silicon substrate.

[0040] It should be understood that the thinning process 400 can be performed simultaneously with the attachment of the front side 210 of the integrated circuit device 200 to the support substrate, which provides mechanical strength and support to the integrated circuit device 200 while performing the thinning process 400. After the thinning process 400 is completed, the support substrate can be removed from the integrated circuit device 200. For simplicity, such a support substrate is not shown in the image. Figure 2 As shown in the image.

[0041] Now for reference Figure 3Multiple deposition processes 420 are performed on the integrated circuit device 200 to form one or more mask layers on the back side 211 of the integrated circuit device 200. For example, a first deposition process of deposition process 420 may be performed to deposit mask layer 440 on the back side 211 of the integrated circuit device 200, wherein the integrated circuit device 200 has already been thinned at this stage of manufacturing. Subsequently, a second deposition process of deposition process 420 may be performed to deposit mask layer 450 over the back side 211 of mask layer 440. In some embodiments, the first deposition process and / or the second deposition process may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. The deposition materials of mask layer 440 and mask layer 450 may be different types of materials in some embodiments, or the same type of materials in other embodiments. In some embodiments, mask layer 440 is deposited to contain silicon nitride as its material, and mask layer 450 is deposited to contain silicon oxide as its material. Mask layer 440 and mask layer 450 may also be deposited such that mask layer 450 is thicker than mask layer 440. In some embodiments, the thickness of mask layer 440 is in the range of about 5 nanometers to about 15 nanometers, and the thickness of mask layer 450 is in the range of about 15 nanometers to about 45 nanometers.

[0042] Now for reference Figure 4 One or more etching processes 500 are performed on the integrated circuit device 200 to form a plurality of openings in the integrated circuit device 200. For example, one or more of the etching processes 500 may etch openings 510, 511, and 513 in the integrated circuit device 200. Opening 510 is etched to extend vertically (in the Z direction) through mask layers 450 and 440, and through semiconductor material 230 and source / drain region 220, such that source / drain contact 250 is exposed to back side 211. Opening 511 is etched to extend vertically (in the Z direction) through mask layers 450 and 440 and STI 261, such that source / drain contact 251 is exposed to back side 211. Opening 513 is etched to extend vertically (in the Z direction) through mask layers 450 and 440, semiconductor material 233, and source / drain region 223, such that source / drain contact 253 is exposed to back side 211.

[0043] In some embodiments, one or more etching processes 500 may include the same etching process to simultaneously etch all openings 510, 511, and 513. Such etching processes may be wet etching or dry etching. Since different types of materials will be etched (e.g., silicon material used to form openings 510 and 513 compared to the dielectric material (e.g., silicon oxide) used to form opening 511), the etching process can be tailored to have etch selectivity for these materials. For example, the etching rates of silicon and dielectric materials can be configured to be higher than those of other materials in the integrated circuit device 200 (e.g., metals or other types of dielectric materials). In this way, silicon material can be removed during the formation of openings 510 and 513, and dielectric material (e.g., silicon oxide) can be removed during the formation of opening 511 without substantially affecting the rest of the integrated circuit device 200.

[0044] In other embodiments, two different etching processes can be performed as part of one or more etching processes 500. For example, a first etching process can be performed to etch openings 510 and 513, while the source / drain contact 251 (and the STI structure 261 disposed thereon) remains unetched. Subsequently, a second etching process can be performed to etch opening 511, while protecting openings 510 and 513 from further etching by the second etching process. This can be achieved by adjusting the etch selectivity between the silicon material 230 and the STI structure 261 in the second etching process, or by protecting openings 510 and 513 by using a protective mask that can be removed later. Of course, the order in which openings 510, 511, and 513 are etched is not important. In other words, opening 511 can be etched by the first etching process, and openings 510 and 513 can be etched by the second etching process.

[0045] Regardless of whether one or more etching processes 500 are implemented, the end result is that opening 510 exposes the face-back surface of source / drain contact 250, opening 511 exposes the face-back surface of source / drain contact 251, and opening 513 exposes the face-back surface of source / drain contact 253.

[0046] Now for reference Figure 5A substrate formation process 530 is performed to form a substrate 550 in opening 510, a substrate 551 in opening 511, and a substrate 553 in opening 513. For example, the substrate formation process 530 may include a deposition process, such as a CVD process, a PVD process, or an ALD process, to form a substrate on the back side 211 deposited on the integrated circuit device 200. Such a substrate is formed on the surface of the mask layer 450 and partially fills openings 510, 511, and 513, including the sidewalls and bottom surfaces of openings 510, 511, and 513. In some embodiments, the deposited substrate comprises a dielectric material, such as silicon nitride. In some embodiments, the deposited substrate may have a thickness in the range of about 2 nanometers to about 3 nanometers.

[0047] Subsequently, one or more etching processes can be performed as part of the substrate formation process 530. This etching process is configured to have sufficiently high etch selectivity between the deposited substrate and another component of the integrated circuit device 200 (e.g., silicon, silicon oxide, or metal). In other words, the material of the substrate can be etched away at a substantially faster rate than other components of the integrated circuit device 200. Since the etching is primarily performed in a vertically downward direction (e.g., towards the front side 210), portions of the substrate located on the sidewalls of openings 510, 511, and 513 remain substantially intact, while the remainder of the substrate is removed. For example, portions of the substrate formed on the surface of the mask layer 450 are removed, just as portions of the substrate formed on the surfaces of the source / drain contacts 250, 251, and 253 and exposed by openings 510, 511, and 513, respectively.

[0048] The result of the substrate formation process 530 is that substrates 550, 551, and 553 are formed on the sidewalls of openings 510, 511, and 513, respectively, while openings 510, 511, and 513 still expose portions of source / drain contacts 250, 251, and 253, respectively. It should be understood that substrates 550, 551, and 553 help prevent vias subsequently formed in openings 510, 511, and 513 from short-circuiting with other components of the integrated circuit device 200 (e.g., gate structures).

[0049] Now for reference Figure 6One or more deposition processes 580 are performed on the integrated circuit device 200 to deposit one or more conductive materials in openings 510, 511, and 513. In some embodiments, one or more deposition processes 580 include CVD, PVD, ALD, or combinations thereof. In some embodiments, the deposited conductive material may include a single type of metallic material, such as tungsten. In other embodiments, the deposited conductive material may contain different metallic atomic elements, such as metal compounds or metal alloys. It is understood that the conductive material deposited by deposition process 580 may be the same type of material as the source / drain contacts 250, 251, and 253 in some embodiments, or may be a different type of material in other embodiments.

[0050] One or more planarization processes may be performed after deposition process 580 to remove excess portions of the deposited conductive material outside of openings 510, 511, and 513, and to planarize the exposed surfaces of the conductive material deposited in openings 510, 511, and 513 (e.g., exposed on the back side 211) with the surface of mask layer 450. Therefore, vias 600, 601, and 603 are formed in openings 510, 511, and 513, respectively. As described above, substrates 550, 551, and 553 are disposed on opposite sides of vias 600, 601, and 603, and they serve to mitigate the risk of unwanted short circuits between vias 600, 601, and 603 and other components of the integrated circuit device 200 (e.g., gate structures).

[0051] Note that vias 600 and 603 are formed to a greater depth than via 601. For example, vias 600 and 603 are formed to depths of 620 and 623, respectively, while via 601 is formed to a depth of 621. Depths 620, 621, and 623 are measured in the vertical direction of the Z-axis, and depths 620 and 623 are substantially greater than depth 621. This difference in depth 621 and 620 / 623 is because via 601 is formed above the uppermost protrusion of the source / drain contact 251 (e.g., protruding toward the back side 211 in the vertical Z-axis), while vias 600 / 603 are each formed on different portions of the source / drain contacts 250 / 253 that do not protrude as much toward the back side 211. In some embodiments, depth 620 is in the range of about 90 nanometers to about 120 nanometers, and depth 621 is in the range of about 50 nanometers to about 80 nanometers. In some embodiments, the ratio of depth 620 to depth 621 is in the range of about 1.125:1 to about 2.4:1.

[0052] As an inherent result of the specific manufacturing process performed herein, a specific physical characteristic of the integrated circuit device 200 is that vias 600, 601, and 603 are formed in direct physical contact with source / drain contacts 250, 251, and 253, respectively, wherein vias 600, 601, and 603 are formed above the backside 211 of the source / drain contacts 250, 251, and 253. Vias 600, 601, and 603 can be used to facilitate electrical wiring from the backside 211 of the integrated circuit device 200. In contrast, integrated circuit devices not manufactured according to the unique manufacturing process described herein have vias formed directly on the epitaxial layer (as opposed to directly on the source / drain contacts 250, 251, and 253) to achieve backside electrical wiring, or may not have these vias formed at all. While forming vias directly on the epitaxial layer may introduce increased parasitic resistance (e.g., because the epitaxial layer is less conductive than a metallic material), the metal-to-metal interfaces formed by the vias 600, 601, and 603 and their respective source / drain contacts 250, 251, and 253 produce substantially lower resistance. As a result, the integrated circuit device 200 of this disclosure can achieve back-side electrical wiring with significantly lower resistance. Furthermore, the lower resistance translates into improved device performance of the integrated circuit device 200, including but not limited to: faster speed, lower power consumption, less heat generation, and potentially longer device lifetime.

[0053] Figure 6 The embodiments illustrate an architecture in which some vias (e.g., vias 600 and 603) of the integrated circuit device 200 are formed to extend vertically through semiconductor material (e.g., semiconductor material 230 / 233 and source / drain regions 220 / 223), while some other vias (e.g., via 601) are formed to extend vertically through dielectric material (e.g., STI structure 261). However, while such an architecture is perfectly capable of facilitating backside electrical wiring of the integrated circuit device 200, it is not intended as a limitation. Other possible architectures correspond to... Figure 7-9 The embodiments are shown. For consistency and clarity, Figures 2 to 6 and Figure 7-9 Similar components will be marked as identical.

[0054] For example, refer to Figure 7 A schematic partial side cross-sectional view of an embodiment of the integrated circuit device 200 is shown. Figure 7In the illustrated embodiment, via 601 is still formed to directly contact the back side 211 of the source / drain contact 251. Additionally, via 602 is also formed to extend from the back side 211 to the front side 210 of the integrated circuit device 200. Specifically, via 602 extends into and directly contacts the semiconductor material 232. As described above, the semiconductor material 232 may be part of the active region of the integrated circuit device 200. In some embodiments, via 602 may be formed using the same process as that used to form via 601. For example, the etching process 500 discussed above (see...) Figure 4 This can be used to simultaneously etch opening 511 (for via 601) and another opening (for via 602). The deposition process 580 discussed above can be used (see [link]). Figure 6 These openings are filled with a conductive material to form vias 601 and 602.

[0055] Please note that in this embodiment, the liner 551 is still formed on the opposite side surface of the via 601 to mitigate the risk of short circuits. Similarly, the liner 552 is formed on the opposite side surface of the via 602 to mitigate the risk of short circuits between the via 602 and another component of the integrated circuit device 200. Additionally, a conductive pad 650 is formed over the back side 211 of the integrated circuit device 200 to electrically couple the vias 601 and 602 together. That is, a portion of the conductive pad 650 is in direct contact with the back side surface of the via 601, while another portion of the conductive pad 650 is in direct contact with the back side surface of the via 602. Therefore, the via 602 can be considered as providing another electrical path in parallel with the via 601 for back-side electrical wiring. Furthermore, this parallel electrical path can provide a reduced total resistance and can tolerate larger current / voltage values ​​in certain IC applications.

[0056] Now for reference Figure 8 This shows a schematic partial side cross-sectional view of another embodiment of the integrated circuit device 200. Note that... Figures 2 to 7 It is a Y-section view, and Figure 8 This is an X-ray cut side profile. For example, Figure 8 The sectional view is along the tangent line B-B' (also in...) Figure 1C (As shown in the image) It is obtained by taking a cross-section. Figure 8 In the illustrated embodiment, the integrated circuit device 200 is a gate-all-around (GAA) device. More specifically, the integrated circuit device 200 includes a gate structure 700, which may be as described above. Figure 1C An embodiment of the gate structure 140 is discussed. The integrated circuit device 200 also includes a vertically stacked nanostructure 710, which may be as described above. Figure 1CAn embodiment of the nanostructure 170 is discussed. The nanostructure 710 may include nanosheets, nanoplates, nanotubes, nanowires, etc., which can serve as channels for a GAA device. A gate structure 700 circumferentially surrounds each nanostructure 710, which is shown in the side cross-sectional view as a portion of the gate structure 700 intersecting with... Figure 8 The nanostructures in the vertical Z direction are 710 interlaced.

[0057] The integrated circuit device 200 also includes a gate via 730 located above the front side 210 of the gate structure 700. The gate via 730 is vertically disposed between the gate structure 700 and the metal line 360 ​​of the interconnect structure 300, and extends vertically through the ILD 275, the etch stop layer 310, and the ILD 320. Therefore, electrical access to the gate structure 700 can be obtained at least partially through the gate via 730. The integrated circuit device 200 also includes source / drain regions 225 and 226 disposed on opposite sides of the gate structure 700 (e.g., in the X direction). Source / drain regions 225 and 226 are similar to the source / drain regions 220-223 discussed above and can be formed using similar processes (e.g., epitaxial growth). Source / drain contacts 255 and 256 are formed above the front side 210 of the source / drain regions 225 and 226, respectively. Source / drain contacts 255 and 256 extend into (e.g., protrude toward the back side 211) source / drain regions 225 and 226, respectively. Electrical access to source / drain regions 225-226 can also be obtained at least partially through interconnect structure 300. For example, via 740 may be formed above the front side 210 of source / drain contact 256. Via 740 is also electrically coupled to metal line 360. Thus, source / drain contacts 256, via 740, and metal line 360 ​​together provide electrical connection to source / drain region 226.

[0058] According to various aspects of the embodiments disclosed herein, a via 750 is formed above the back side 211 of the source / drain contact 256. The via 750 can use the methods discussed above for forming... Figure 6 Similar processes to those used for 600-603 vias (e.g., Figure 4 process 500 and Figure 6 The process 580 is used to form the via. For example, an inverted L-shaped opening can be etched into the semiconductor material 235 and the source / drain region 226 by performing one or more etching processes, exposing the source / drain contact 256 to the back side 211. Thereafter, a conductive material can be deposited to fill such an opening to form a via 750. Note that a liner 760 can also be formed on the opposite side surface of the via 750. The liner 760 may include a dielectric material and can use the method described above. Figure 5The process for forming the liner 550-553 is discussed.

[0059] like Figure 8 As shown, via 750 may include segments 750A and 750B. Segment 750A extends vertically through semiconductor material 235 and partially extends into gate structure 700. In other words, segment 750A is in direct contact with and electrically connected to gate structure 700 via backside 211. Meanwhile, segment 750B extends vertically through source / drain region 226. In other words, segment 750B is in direct contact with and electrically connected to source / drain contact 256 via backside 211. Segment 750A is substantially wider than segment 750B, which results in… Figure 8 The side cross-sectional view shows a similar inverted L-shaped profile of the through hole 750.

[0060] Please note that because via 750 is electrically coupled to both gate structure 700 and source / drain contact 256, two parallel electrical paths are established: one corresponding to segment 750A of via 750, gate structure 700, and gate via 730, and the other corresponding to segment 750B of via 750, source / drain contact 256, and via 740. Furthermore, this parallel electrical path can provide reduced overall resistance and tolerate larger currents / voltages in certain IC applications.

[0061] Now for reference Figure 9 This shows a schematic partial side cross-sectional view of another embodiment of the integrated circuit device 200. Figure 8 similar, Figure 9 Also shown is an X-cut side cross-sectional view; the integrated circuit device 200 is also a gate-all-around (GAA) device. Figure 9 In this embodiment, source / drain contact 258 is implemented to extend vertically through source / drain regions 225 and ILD 275, and source / drain contact 259 is implemented to extend vertically through source / drain regions 226 and ILD 275. Vias 748 and 749 are formed as part of interconnect structure 300, wherein vias 748 and 749 are electrically coupled to the front side 210 of source / drain contacts 258 and 259, respectively. Vias 748 and 749 may also be coupled to a metal line of interconnect structure 300, such as metal line 360.

[0062] According to various aspects of the embodiments disclosed herein, a via 800 is formed above the back side 211 of the source / drain contact 258. The via 800 can use the methods discussed above for forming... Figure 6 Similar processes to those used for 600-603 vias (e.g., Figure 4 process 500 and Figure 6The via 800 is formed using process 580. For example, one or more etching processes can be performed to etch openings through the semiconductor material 235 and the source / drain region 225, exposing the source / drain contact 258 to the back side 211. A conductive material can then be deposited to fill such openings to form the via 800. Note that a liner 810 can also be formed on the opposite side surface of the via 800 in this embodiment. The liner 810 can comprise a dielectric material and can be formed using similar processes for forming the liners 550-553 discussed above. In any case, the fact that the via 800 forms direct contact with the back side 211 of the source / drain contact 258 means that... Figure 9 The embodiments can also achieve reduced resistance, which translates into improved device performance as discussed above.

[0063] Figure 10 An integrated circuit manufacturing system 900 according to an embodiment of this disclosure is shown, which can be used to manufacture the integrated circuit device 200 of this disclosure embodiment. The manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916…, N connected via a communication network 918. The network 918 can be a single network or can be various different networks, such as an internal network and the Internet, and can include both metal wires and wireless communication channels.

[0064] In this embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring products of interest; entity 906 represents an engineer, such as a processing engineer controlling processes and related formulations, or an equipment engineer monitoring or adjusting the settings and conditions of a detector processing tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool used to perform lithography processes to define various components of the integrated circuit device herein; entity 912 represents a virtual metrology module associated with processing tool 910; entity 914 represents a high-level processing control module associated with processing tool 910 and other processing tools; and entity 916 represents a sampling module associated with processing tool 910.

[0065] Each entity can interact with other entities and can provide integrated circuit manufacturing, processing control interaction, and / or computing power, and / or receive such capabilities from other entities. Each entity may also include one or more computer systems for performing computations and performing automation. For example, the advanced processing control module of entity 914 may include multiple computer hardware components with software instruction encoding therein. The computer hardware may include hard drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., detectors), and input / output devices (e.g., mice and keyboards). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0066] The integrated circuit manufacturing system 900 enables interaction between entities to achieve advanced processing control in integrated circuit (IC) manufacturing. In an embodiment, advanced processing control includes adjusting processing conditions, settings, and / or formulations of a processing tool applicable to the relevant wafer based on metrological results.

[0067] In another embodiment, metrological results are measured from a subset of the processed wafers based on an optimal sampling rate determined by process quality and / or product quality. In yet another embodiment, metrological results are measured from selected fields and points of a subset of the processed wafers based on an optimal sampling field / point determined based on various characteristics of process quality and / or product quality.

[0068] One of the functions provided by the IC manufacturing system 900 is to enable collaboration and information access in areas such as design, engineering and processing, metrology, and advanced processing control. Another function provided by the IC manufacturing system 900 is to integrate the system between facilities such as metrology tools and processing tools. This integration enables facilities to coordinate their activities. For example, integrating metrology tools and processing tools allows manufacturing information to be incorporated into the manufacturing process more effectively, and allows wafer data from in-line or field measurements to be integrated with metrology tools in the relevant processing tools.

[0069] Figure 11 This is a flowchart illustrating a method 1000 for manufacturing a semiconductor device. Method 1000 includes step 1010, to reduce the thickness of a wafer from the back side. The wafer includes source / drain regions and a plurality of source / drain contacts disposed above the front side of the plurality of source / drain regions.

[0070] Method 1000 includes step 1020, performed after the thickness of the wafer has been reduced, wherein step 1020 forms one or more mask layers over the back side of the wafer.

[0071] Method 1000 includes step 1030, to etch one or more openings from the back side of the wafer. The openings expose at least some of the openings to the back side.

[0072] Method 1000 includes step 1040, filling one or more openings with one or more vias such that the one or more vias are electrically coupled to at least some of the source / drain contacts.

[0073] In some embodiments, etching includes etching at least some openings through a semiconductor material or a shallow trench isolation (STI) structure.

[0074] In some embodiments, etching includes simultaneously etching a first opening through the semiconductor material and etching a second opening through the shallow trench isolation (STI) structure. The first opening exposes a first of the source / drain contacts. The second opening exposes a second of the source / drain contacts. The first opening is etched to be substantially deeper than the second opening.

[0075] In some embodiments, etching includes simultaneously etching through a first opening in the semiconductor material and etching through a second opening in the shallow trench isolation (STI) structure. The first opening exposes one of the source / drain regions. The second opening exposes one of the source / drain contacts.

[0076] In some embodiments, the wafer includes a gate structure. In some embodiments, etching is performed such that the gate structure, together with one of the source / drain contacts, is exposed to the back side through a first opening in one or more openings. In some embodiments, filling is performed such that a first via in one or more vias filling the first opening is simultaneously electrically coupled to one of the gate structure and the source / drain contacts.

[0077] It should be understood that method 1000 may also include steps performed before, during, or after steps 1010-1040. For example, method 1000 may include a step performed after etching one or more openings but before forming one or more vias, wherein an electrically insulating liner is formed on the sidewalls of one or more openings. Other steps may include the formation of additional metallization features, packaging, and wafer acceptance testing, etc. For simplicity, these additional steps are not discussed in detail here.

[0078] In summary, the embodiments disclosed herein directly form vias on the back side of the source / drain contacts. More specifically, the source / drain contacts can be formed above the front side of the source / drain region (which may be an epitaxial layer). An opening can then be etched from the back side to expose the source / drain contacts. A conductive material is then deposited into the opening to form conductive contacts that directly contact the back side of the source / drain contacts. By implementing vias in this manner, the embodiments disclosed herein offer advantages over conventional devices. However, it should be understood that specific advantages are not required, other embodiments may offer different advantages, and not all advantages need to be disclosed herein. One advantage is improved device performance. For example, by forming vias to directly contact the source / drain contacts, the integrated circuit device of this invention can achieve substantially lower resistance compared to other integrated circuit devices that form vias on an epitaxial layer. This is because the metal-to-metal interface (e.g., the interface between a via and a source / drain contact) in this disclosed embodiment has a substantially lower resistance than the metal-to-epitaxy layer interface (e.g., the interface in an integrated circuit device where a via is formed on an epitaxial layer). Lower resistance can translate to faster device speeds, reduced power consumption, less heat generation, and potentially longer device lifetime. Yield may also be increased, which could be reflected in wafer acceptance testing performance. Other advantages may include ease of manufacturing and compatibility with existing manufacturing processes.

[0079] The advanced photolithography processes, methods, and materials described above can be used in many applications, including integrated circuit devices using fin field-effect transistors (fin FETs). For example, fins can be patterned to create relatively tight spacing between features, as disclosed in this embodiment. Additionally, the spacer walls or mandrels used to form the fins of the fin FET can be processed according to the above disclosure. It should also be understood that the various aspects of the disclosed embodiments discussed above can be applied to multichannel devices such as gate-all-around (GAA) devices. This disclosure refers to the fin structure of a fin FET device; such discussions may also apply to GAA devices.

[0080] One aspect of this disclosure relates to a semiconductor device. The semiconductor device includes a plurality of source / drain regions. Each semiconductor device includes a plurality of source / drain contacts disposed above the front side of each source / drain region, wherein the source / drain contacts are electrically coupled to the source / drain regions. The semiconductor device also includes a plurality of vias disposed above the back side of each source / drain contact, wherein the back side is opposite to the front side, and wherein the vias are electrically coupled to the source / drain contacts.

[0081] In some embodiments, an interconnect structure is further included, disposed above the front side of the source / drain contact.

[0082] In some embodiments, at least one of the vias extends vertically through the semiconductor material.

[0083] In some embodiments, at least one of the vias extends vertically through the shallow trench isolation (STI) structure.

[0084] In some embodiments, at least one of the vias is a first via, and the semiconductor device further includes a second via disposed above the back side of one of the source / drain regions; wherein: the second via is electrically coupled to one of the source / drain regions; and the first via and the second via are electrically coupled together.

[0085] In some embodiments, wherein: the first via of the via extends vertically through the semiconductor material and is electrically coupled to the first source / drain contact of the source / drain contact; and the second via of the via extends vertically through the shallow trench isolation (STI) structure and is electrically coupled to the second source / drain contact of the source / drain contact.

[0086] In some embodiments, the first via is substantially longer than the second via.

[0087] In some embodiments, a gate structure is further included, wherein at least one of the vias is electrically coupled to the gate structure and one of the source / drain contacts.

[0088] In some embodiments, at least one of the vias has a side profile resembling the letter "L".

[0089] In some embodiments, the semiconductor device includes a gate-all-around (GAA) transistor.

[0090] Another aspect of this disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor substrate. In a side cross-sectional view, the semiconductor device includes a gate structure located above a first side of the semiconductor substrate. In the side cross-sectional view, the semiconductor device includes a first epitaxial layer and a second epitaxial layer, each located above the first side of the semiconductor substrate, wherein, in the side cross-sectional view, the gate structure is located between the first epitaxial layer and the second epitaxial layer. The semiconductor device includes a first conductive contact and a second conductive contact, respectively located above the first side of the first epitaxial layer and the second epitaxial layer, wherein, in the side cross-sectional view, the first conductive contact protrudes into the first epitaxial layer, and wherein, in the side cross-sectional view, the second conductive contact protrudes into the second epitaxial layer. The semiconductor device includes a via located above a second side of the gate structure, the second side opposite to the first side, wherein a first segment of the via extends vertically through the semiconductor substrate and protrudes into the gate structure, and wherein a second segment of the via extends vertically through the second epitaxial layer and directly contacts the second conductive contact.

[0091] In some embodiments, the gate structure is the gate structure of a gate-all-around (GAA) transistor.

[0092] In some embodiments, an interconnect structure is further included, located on the first side of the gate structure, above the first conductive contact and the second conductive contact.

[0093] Another aspect of this disclosure relates to a method of manufacturing a semiconductor device. The thickness of a wafer is reduced from a back side, wherein the wafer includes a plurality of source / drain regions and a plurality of source / drain contacts disposed above the front side of the source / drain regions. After the thickness of the wafer is reduced, one or more mask layers are formed above the back side of the wafer. One or more openings are etched from the back side of the wafer, wherein the one or more openings expose at least some of the source / drain contacts to the back side. The one or more openings are filled with one or more vias, such that the one or more vias are electrically coupled to the at least some of the source / drain contacts.

[0094] In some embodiments, the method further includes forming an electrically insulating liner on the sidewalls of the one or more openings after etching the one or more openings and before forming the one or more vias.

[0095] In some embodiments, the etching includes etching through at least some of the openings through the semiconductor material or through the shallow trench isolation (STI) structure.

[0096] In some embodiments, the etching includes simultaneously etching a first opening through the semiconductor material and a second opening through the shallow trench isolation (STI) structure; the first opening exposes a first of the source / drain contacts; and the second opening exposes a second of the source / drain contacts.

[0097] In some embodiments, the first opening is etched to have a depth substantially deeper than the second opening.

[0098] In some embodiments, the etching includes simultaneously etching a first opening through the semiconductor material and a second opening through the shallow trench isolation (STI) structure; the first opening exposes one of the source / drain regions; and the second opening exposes one of the source / drain contacts.

[0099] In some embodiments, wherein: the wafer includes a gate structure; the etching is performed such that the gate structure is exposed to the back side through a first opening of one or more of the openings together with one of the source / drain contacts; and the filling is performed such that a first via of one or more of the vias filling the first opening is simultaneously electrically coupled to the gate structure and one of the source / drain contacts.

[0100] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by Comprising: a plurality of source / drain regions; a plurality of source / drain contacts disposed over a front side of the source / drain regions, respectively, wherein the source / drain contacts are electrically coupled to the source / drain regions; and a plurality of vias disposed over a back side of the source / drain contacts, respectively, wherein the back side is opposite the front side, and wherein the vias are electrically coupled to the source / drain contacts.

2. The semiconductor device according to claim 1, wherein Further comprising an interconnect structure disposed over the front side of the source / drain contacts.

3. The semiconductor device according to claim 1, wherein Wherein at least one of the vias extends vertically through semiconductor material.

4. The semiconductor device according to claim 1, wherein Wherein at least one of the vias extends vertically through shallow trench isolation.

5. The semiconductor device according to claim 1, wherein Wherein: a first via of the vias extends vertically through semiconductor material and is electrically coupled to a first source / drain contact of the source / drain contacts; and a second via of the vias extends vertically through shallow trench isolation and is electrically coupled to a second source / drain contact of the source / drain contacts.

6. The semiconductor device according to claim 1, wherein Further comprising a gate structure, wherein at least one of the vias is electrically coupled to the gate structure and one of the source / drain contacts.

7. The semiconductor device according to claim 1, wherein Wherein the semiconductor device comprises a wrap-around gate transistor.

8. A semiconductor device, characterized by Comprising: a semiconductor substrate; a gate structure over a first side of the semiconductor substrate in a side cross-sectional view; a first epitaxial layer and a second epitaxial layer each over the first side of the semiconductor substrate in the side cross-sectional view, wherein the gate structure is between the first epitaxial layer and the second epitaxial layer in the side cross-sectional view; a first conductive contact and a second conductive contact over the first side of the first epitaxial layer and the second epitaxial layer, respectively, wherein the first conductive contact protrudes into the first epitaxial layer in the side cross-sectional view, and wherein the second conductive contact protrudes into the second epitaxial layer in the side cross-sectional view; and a via over a second side of the gate structure, the second side being opposite the first side, wherein a first segment of the via extends vertically through the semiconductor substrate and protrudes into the gate structure, and wherein a second segment of the via extends vertically through the second epitaxial layer and is in direct contact with the second conductive contact.

9. The semiconductor device according to claim 8, wherein Wherein the gate structure is a gate structure of a wrap-around gate transistor.

10. The semiconductor device according to claim 8, wherein Further comprising an interconnect structure over the first side of the gate structure, the first conductive contact, and the second conductive contact.

Images