Semiconductor device

Abstract

The semiconductor device provided by the embodiment of the utility model comprises the interconnection structure. The interconnect structure includes a first conductive line in the first dielectric layer, a via hole in the second dielectric layer, and a second conductive line in the third dielectric layer. And the second dielectric layer is arranged between the first dielectric layer and the third dielectric layer. The dielectric constant of the second dielectric layer is smaller than the dielectric constant of the first dielectric layer and the dielectric constant of the third dielectric layer.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more smaller components to be integrated into a given area. These smaller electronic components may require smaller packages that occupy less area than previous packages. Currently, integrated fan-out packages are becoming increasingly popular due to their compactness. Ensuring the reliability of integrated fan-out packages has become a challenge in this field. Utility Model Content

[0003] This utility model provides a semiconductor device including an interconnect structure. The interconnect structure includes a first conductive line in a first dielectric layer, a via in a second dielectric layer, and a second conductive line in a third dielectric layer, wherein the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer, and the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer and the dielectric constant of the third dielectric layer.

[0004] This invention provides a semiconductor device including an interconnect structure. The interconnect structure includes: a conductive feature located in a first dielectric layer; and a via located in a second dielectric layer above the first dielectric layer and electrically connected to the conductive feature. The second dielectric layer includes a plurality of air gaps, and the air gaps laterally surround the via. Attached Figure Description

[0005] This disclosure can be better understood when read in conjunction with the accompanying drawings in the following detailed description. It should be emphasized that, according to industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion. Furthermore, it should be emphasized that the drawings only show typical embodiments of the present invention and should not be considered as limiting the scope of the claim, as the present invention can be equally applied to other embodiments.

[0006] Figures 1A to 1G This is a schematic cross-sectional view of each layer segment in a method for forming a semiconductor device according to some embodiments.

[0007] Figure 2 This is a schematic cross-sectional view of a semiconductor device according to some embodiments.

[0008] Figures 3A to 3JThis is a schematic cross-sectional view of each layer segment in a method for forming a semiconductor device according to some embodiments.

[0009] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to some embodiments.

[0010] Figures 5A to 5G This is a schematic cross-sectional view of each layer segment in a method for forming a semiconductor device according to some embodiments.

[0011] Figure 6A and Figure 6B Top views of semiconductor devices according to some embodiments of this disclosure are shown.

[0012] Figure 7 A flowchart of a method for forming a semiconductor device according to some embodiments is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of this utility model. Specific examples of components and configurations described below are for the purpose of simplifying this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms are used herein to describe the relationship between one component or feature and another, as illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of components during use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0015] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed on redistribution layers or substrates, which allow for testing of 3D packages or 3DICs, probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0016] Figures 1A to 1G This is a schematic cross-sectional view of each layer segment in a method for forming a semiconductor device according to some embodiments.

[0017] refer to Figure 1A A substrate 102 is provided. The substrate 102 may be a doped or undoped silicon substrate. In some embodiments, the substrate 102 includes other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. For example, the substrate 102 includes packaging regions. In other embodiments, the substrate 102 is a wafer substrate and includes multiple packaging regions that will be segmented in subsequent processing. In some embodiments, the substrate 102 typically does not include active components, although the substrate 102 may include passive components formed in and / or on the front surface of the substrate 102. In other embodiments, active components (e.g., transistors, diodes, etc.), capacitors, resistors, etc., or combinations thereof, are formed in and / or on the front surface of the substrate 102.

[0018] Then, a plurality of through-holes 104 are formed in the substrate 102. The through-holes 104 can be formed by a single damascene process. This can be achieved by first forming the via openings in the substrate 102 through etching, machining, laser technology, or combinations thereof. A thin barrier material can be conformally deposited in the via openings, for example, by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, or combinations thereof. The barrier material can be formed from oxides, nitrides, carbides, or combinations thereof. A conductive material can be deposited over the barrier material and in the via openings. The conductive material can be formed by electrochemical plating, CVD, ALD, PVD, or combinations thereof. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, or combinations thereof. For example, excess conductive and barrier materials are removed from the surface of the substrate 102 by CMP. The remaining portions of the barrier and conductive materials form the through-holes 104.

[0019] Then, a dielectric layer 112 (e.g., 112-1) is formed over the substrate 102 and the via 104. The dielectric layer 112 (e.g., 112-1) is formed on the substrate 102 along direction D1 (e.g., the z-direction), and the dielectric layer 112 (e.g., 112-1) extends, for example, in a direction D2 (e.g., the x-direction) substantially perpendicular to direction D1. The thickness T1 of the dielectric layer 112 (e.g., 112-1) is, for example, in the range of 1 μm to 3 μm. In some embodiments, the material of the dielectric layer 112 (e.g., 112-1) includes undoped silicate glass (USG) or doped silicate glass, such as fluorinated silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), silicon oxide, etc., or combinations thereof. The dielectric constant (k) of the dielectric layer 112 (e.g., 112-1) can be in the range of 3.5 to 4.5. For example, the material of dielectric layer 112 (e.g., 112-1) includes USG or FSG. Dielectric layer 112 (e.g., 112-1) can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on dielectric (SOD) processes, or combinations thereof. The stress of the formed dielectric layer 112 (e.g., 112-1) can be controlled by adjusting the RF power (e.g., 100W to 2000W) and / or the gas ratio (e.g., the N+2 to N+2O ratio in the range of 0.1 to 0.25) of the deposition process such as CVD. For example, increasing the RF power increases the stress of the formed dielectric layer 112 (e.g., 112-1), and decreasing the N+2 to N+2O ratio increases the stress of the formed dielectric layer 112 (e.g., 112-1). In some embodiments, an etch stop layer 111 is formed directly beneath a dielectric layer 112 (e.g., 112-1) and between a substrate 102 and a dielectric layer 112 (e.g., 112-1). The etch stop layer 111 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having an etch rate different from that of the material of the overlying dielectric layer 112 (e.g., 112-1).

[0020] Subsequently, a plurality of conductive features 122 (e.g., 122-1) are formed in the dielectric layer 112 (e.g., 112-1). The conductive features 122 (e.g., 122-1) (e.g., wires) may be electrically connected to underlying conductive features (e.g., to via 104). The conductive features 122 (e.g., 122-1) may be formed by a single damascene process. A first trench opening may be formed in the dielectric layer 112 (e.g., 112-1) first by means of etching, machining, laser technology, or combinations thereof. A thin barrier material may be conformally deposited in the trench opening, for example by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, or combinations thereof. The barrier material may be formed of oxides, nitrides, carbides, combinations thereof, etc. Conductive material may be deposited over the barrier material and in the trench opening. The conductive material may be formed by electrochemical plating processes, CVD, ALD, PVD, or combinations thereof. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, or combinations thereof. For example, excess conductive and barrier materials are removed from the surface of dielectric layer 112 (e.g., 112-1) by CMP. The remaining portions of the barrier and conductive materials form conductive feature 122 (e.g., 122-1). In some embodiments, conductive feature 122 (e.g., 122-1) comprises copper and is a copper wire.

[0021] In some embodiments, the first surface (e.g., bottom surface) of the conductive feature 122 (e.g., 122-1) is substantially coplanar with the first surface (e.g., bottom surface) of the dielectric layer 112 (e.g., 112-1), and the second surface (e.g., top surface) of the conductive feature 122 (e.g., 122-1) opposite to the first surface is substantially coplanar with the second surface (e.g., top surface) of the dielectric layer 112 (e.g., 112-1) opposite to the first surface. Therefore, the conductive feature 122 (e.g., 122-1) may have a thickness substantially the same as the thickness T1 of the dielectric layer 112 (e.g., 112-1). For example, the thickness of the conductive feature 122 (e.g., 122-1) is in the range of 1 μm to 3 μm. Figure 1A As shown, in an embodiment where the etch stop layer 111 is located below the dielectric layer 112 (e.g., 112-1), the first surface (e.g., bottom surface) of the conductive feature 122 (e.g., 122-1) is substantially coplanar with the first surface (e.g., bottom surface) of the etch stop layer 111, and the conductive feature 122 (e.g., 122-1) may have a thickness substantially the same as the total thickness of the dielectric layer 112 (e.g., 112-1) and the thickness of the etch stop layer 111.

[0022] refer to Figure 1BA dielectric layer 114 (e.g., 114-1) is formed over dielectric layer 112-1 and conductive feature 122 (e.g., 122-1). Dielectric layer 114 (e.g., 114-1) may have a thickness T2 smaller than the thickness T1 of dielectric layer 112-1. For example, the thickness T2 of dielectric layer 114 (e.g., 114-1) is in the range of 0.5 μm to 1.5 μm. The material of dielectric layer 114 (e.g., 114-1) may be different from the material of dielectric layer 112-1. For example, the dielectric constant (k) of dielectric layer 114 (e.g., 114-1) is lower than the dielectric constant (k) of dielectric layer 112-1. For example, the difference between the dielectric constant of dielectric layer 112-1 and the dielectric constant of dielectric layer 114 (e.g., 114-1) is not less than 0.5. In some embodiments, dielectric layer 114 (e.g., 114-1) comprises a low-k dielectric material (e.g., carbon-doped oxide or fluorosilicate-glass (FGS)), an extremely low-k dielectric material (e.g., porous carbon-doped silicon dioxide), a polymer such as polyimide, or a combination thereof. The low-k dielectric material may have a k value below 3.9. In some embodiments, the k value of dielectric layer 114 (e.g., 114-1) is in the range of 2.5 to 3.5. Dielectric layer 114 (e.g., 114-1) may have a stress below 100 MPa. Dielectric layer 114 (e.g., 114-1) may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on dielectric (SOD) processes, or combinations thereof. In some embodiments, an etch stop layer 111 is formed directly beneath dielectric layer 114 (e.g., 114-1) and between dielectric layer 112-1 and dielectric layer 114 (e.g., 114-1). The etch stop layer 111 may comprise a dielectric material, such as silicon carbide, silicon nitride, silicon oxide, silicon oxynitride, or the like, having an etch rate different from that of the material of the overlying dielectric layer 114 (e.g., 114-1).

[0023] Subsequently, at least one conductive feature 124 (e.g., 124-1) is formed in the dielectric layer 114 (e.g., 114-1). The conductive feature 124 (e.g., 124-1), such as a via, may be electrically connected to the underlying conductive feature 122 (e.g., 122-1). For example, the conductive feature 124 (e.g., 124-1) may directly contact the underlying conductive feature 122 (e.g., 122-1), such as a wire. The conductive feature 124 (e.g., 124-1) may be formed by a single damascene process. The via opening may be first formed in the dielectric layer 114 (e.g., 114-1) by, for example, etching, machining, laser technology, or combinations thereof. A thin barrier material may be conformally deposited in the via opening, for example, by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, or combinations thereof. The barrier material may be formed of oxides, nitrides, carbides, combinations thereof, etc. The conductive material may be deposited over the barrier material and in the via opening. Conductive materials can be formed by electrochemical plating processes, CVD, ALD, PVD, or combinations thereof. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, or combinations thereof. For example, excess conductive and barrier materials are removed from the surface of dielectric layer 114 (e.g., 114-1) by CMP. The remaining portions of the barrier and conductive materials form conductive feature 124 (e.g., 124-1). In some embodiments, conductive feature 124 (e.g., 124-1) comprises copper and is a copper via.

[0024] The first surface (e.g., bottom surface) of conductive feature 124 (e.g., 124-1) is substantially coplanar with the first surface (e.g., bottom surface) of dielectric layer 114 (e.g., 114-1), and the second surface (e.g., top surface) of conductive feature 124 (e.g., 124-1) opposite to the first surface is also substantially coplanar with the second surface (e.g., top surface) of dielectric layer 114 (e.g., 114-1). Therefore, conductive feature 124 (e.g., 124-1) may have a thickness substantially the same as the thickness T2 of dielectric layer 114 (e.g., 114-1), and conductive feature 124 (e.g., 124-1) may have a thickness smaller than the thickness T1 of conductive feature 122 (e.g., 122-1). For example, the thickness of conductive feature 124 (e.g., 124-1) is in the range of 0.5 μm to 1.5 μm. Figure 1B In the embodiment where the etch stop layer 111 is below the dielectric layer 114 (e.g., 114-1), the first surface (e.g., the bottom surface) of the conductive feature 124 (e.g., 124-1) is substantially coplanar with the first surface (e.g., the bottom surface) of the etch stop layer 111, and the conductive feature 124 (e.g., 124-1) may have a thickness substantially the same as the total thickness of the dielectric layer 114 (e.g., 114-1) and the thickness of the etch stop layer 111.

[0025] refer to Figure 1C A dielectric layer 112 (e.g., 112-2) is formed over a dielectric layer 114 (e.g., 114-1) and a conductive feature 124 (e.g., 124-1). The material, thickness, and forming method of the dielectric layer 112-2 are the same as or similar to those of the dielectric layer 112-1. The dielectric layer 112 (e.g., 112-2) may have a thickness T1 greater than the thickness T2 of the dielectric layer 114 (e.g., 114-1). The thickness T1 of the dielectric layers 112 (e.g., 112-1 and 112-2) may be the same or different. The material of the dielectric layers 112 (e.g., 112-1 and 112-2) may be the same or different. The material of the dielectric layers 112 (e.g., 112-1 and 112-2) may be different from the material of the dielectric layer 114 (e.g., 114-1). The dielectric constant (k) of dielectric layer 112 (e.g., 112-1 and 112-2) can be greater than the dielectric constant (k) of dielectric layer 114 (e.g., 114-1). For example, the difference between the dielectric constant (k) of dielectric layer 112 (e.g., 112-1 and 112-2) and the dielectric constant (k) of dielectric layer 114 (e.g., 114-1) is not less than 0.5. The dielectric constant (k) of dielectric layer 112 (e.g., 112-1 and 112-2) can be in the range of 3.5 to 4.5. For example, the material of dielectric layer 112 (e.g., 112-1 and 112-2) includes USG or FSG, and dielectric layer 114 (e.g., 114-1) includes a low-k dielectric material. In some embodiments, an etch stop layer 111 is formed directly beneath dielectric layer 112 (e.g., 112-2). The etch stop layer 111 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride or the like, which has a different etch rate than the material of the upper dielectric layer 112 (e.g., 112-2).

[0026] Subsequently, a plurality of conductive features 122 (e.g., 122-2) are formed in the dielectric layer 112 (e.g., 112-2). The conductive features 122 (e.g., 122-2) (e.g., wires) may be electrically connected to the underlying conductive feature 124 (e.g., 124-1) (e.g., vias). The conductive features 122 (e.g., 122-2) may be formed by a single damascene process, and the formation method is similar to or the same as the formation method of the conductive feature 122-1. In an alternative embodiment, the conductive features 122 (e.g., 122-2) and the underlying conductive feature 124 (e.g., 124-1) are formed by the same process (e.g., a dual damascene process). For example, conductive feature 122 (e.g., 122-2) and underlying conductive feature 124 (e.g., 124-1) are formed by forming via openings in dielectric layer 114 (e.g., 114-1) and trench openings connecting the via openings in dielectric layer 112 (e.g., 112-2), depositing barrier material and conductive material into the via openings and trench openings, and removing excess conductive and barrier material outside the via openings and trench openings. In some embodiments, conductive feature 122 (e.g., 122-2) comprises copper and is a copper wire.

[0027] In some embodiments, the first surface (e.g., bottom surface) of the conductive feature 122 (e.g., 122-2) is substantially coplanar with the first surface (e.g., bottom surface) of the dielectric layer 112 (e.g., 112-2), and the second surface (e.g., top surface) of the conductive feature 122 (e.g., 122-2) opposite to the first surface is substantially coplanar with the second surface (e.g., top surface) of the dielectric layer 112 (e.g., 112-2). Therefore, the conductive feature 122 (e.g., 122-2) may have a thickness substantially the same as the thickness T1 of the dielectric layer 112 (e.g., 112-2). For example, the thickness of the conductive feature 122 (e.g., 122-2) is in the range of 1 μm to 3 μm. Figure 1C In the embodiment where the etch stop layer 111 is located below the dielectric layer 112 (e.g., 112-2), the first surface (e.g., bottom surface) of the conductive feature 122 (e.g., 122-2) is substantially coplanar with the first surface (e.g., bottom surface) of the etch stop layer 111, and the conductive feature 122 (e.g., 122-2) may have a thickness substantially the same as the total thickness of the dielectric layer 112 (e.g., 112-2) and the thickness of the etch stop layer 111.

[0028] See Figure 1DIn some embodiments, after forming dielectric layers 112-1, 114-1, 112-2 and conductive features 122-1, 124-1, 122-2, dielectric layers 114-2 (not shown), 112-3 (not shown)...112-(n+1), 114-(n+1), 112-(n+2) and conductive features 124-2 (not shown), 122-3 (not shown)...122-(n+1), 124-(n+1), 122-(n+2) formed therein can be sequentially formed on dielectric layer 112-2. Thus, the interconnect structure 110 of the intermediate 100 can be formed. The dielectric layers 114-2 (not shown), 112-3 (not shown)...112-(n+1), 114-(n+1), 112-(n+2) and the conductive features 124-2 (not shown), 122-3 (not shown)...122-(n+1), 124-(n+1), 122-(n+2) can be derived from the reference. Figures 1A to 1C The dielectric layer 114 can be formed using the same or similar process as described. Figure 1B The dielectric layer 112 can be formed by the process described above, and the dielectric layer 112 can be made from... Figure 1A or Figure 1C The process is formed.

[0029] In some embodiments, the interconnect structure 110 may include a metal 1 interconnect layer (M1 level), a via 1 interconnect layer (V1 level), a metal 2 interconnect layer (M2 level), a via 2 interconnect layer (V2 level), a metal 3 interconnect layer (M3 level)... a metal (n+1) interconnect layer (M(n+1) level), a via (n+1) interconnect layer (V(n+1) level), and a metal (n+2) interconnect layer (M(n+2) level). However, this disclosure is not limited thereto. Each of the M1 level, V1 level, M2 level, V2 level, M3 level... M(n+1) level, V(n+1) level, and M(n+2) level may be referred to as a metal level. The conductive feature 122-1 formed on the M1 level may be referred to as an M1 metal line. Similarly, the conductive features 122 or 124 formed at layers V1, M2, M3...M(n+1), V(n+1), and M(n+2) can be referred to as M1 metal lines, V1 vias, M2 metal lines, V2 vias, M3 metal lines...M(n+1) metal lines, V(n+1) vias, and M(n+2) metal lines. In some embodiments, n represents a positive integer, and the total number of interconnect layers is 2n+3. In some embodiments, conductive features 122 at the same layer are formed simultaneously. In some embodiments, conductive features 122 or 124 at the same layer have top surfaces that are substantially coplanar with each other and / or bottom surfaces that are substantially coplanar with each other. In some embodiments, vias 124 have vertical sidewalls. However, this disclosure is not limited thereto. Vias 124 may have substantially vertical sidewalls or inclined sidewalls. It is worth noting that the interconnect structure 110 may have any suitable number of interconnect layers and is composed of... Figures 1A to 1C The process shown forms at least two dielectric layers 114, 112 (e.g., dielectric layers 114-(n+1), 112-(n+2)). In some embodiments, since dielectric layer 114 is disposed between dielectric layers 112 and separates the conductive features 122 in two adjacent dielectric layers 112, dielectric layer 114 may also be referred to as an intermetallic dielectric layer.

[0030] refer to Figure 1E After forming the interconnect structure 110, conductive connectors 126 electrically connected thereto are formed on the interconnect structure 110 to provide external electrical connectivity. In some embodiments, the conductive connectors 126 are ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. For example, the conductive connectors 126 are formed in and / or on a dielectric layer 125 above the interconnect structure 110. The material of the dielectric layer 125 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), oxides, nitrides, etc., or any other suitable dielectric material.

[0031] For example, the conductive connector 126 includes a bump base metal (UBM) 126a and a solder area 126b above the bump base metal 126a. The bump base metal 126a may be a conductive pillar, pad, etc. In some embodiments, the bump base metal 126a may be formed by forming a seed layer over the interconnect structure 110. The seed layer may be a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed, for example, by PVD, etc. A photoresist layer is then formed on the seed layer and patterned. The photoresist layer may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist layer corresponds to the bump base metal 126a. Patterning forms openings through the photoresist layer to expose the seed layer. A conductive material is then formed in the openings of the photoresist layer and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, nickel, etc. Then, the photoresist layer and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist layer can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. After removing the photoresist layer, the exposed portion of the seed layer can be removed, for example, by using an acceptable etching process. The remaining portion of the seed layer and the conductive material forms the bump base metal 126a.

[0032] In some embodiments, the bump base metal 126a comprises three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. Other materials and other arrangements of layers can be used to form the bump base metal 126a, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement. The scope of this application is intended to include any suitable material or layer of materials that can be used for the bump base metal 126a.

[0033] Solder region 126b may include solder material and may be formed over bump base metal 126a by dipping, printing, electroplating, etc. Solder material may include, for example, lead-based solders and lead-free solders, such as Pb-Sn compositions for lead-based solders; lead-free solders including InSb; tin, silver, and copper (SAC) compositions; and other eutectic materials having a common melting point and forming conductive solder connections in electrical applications. For lead-free solders, SAC solders with different compositions may be used, such as SAC105 (Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC305, and SAC405. Lead-free solders may also include SnCu compounds that do not use silver (Ag). Lead-free solders may also contain tin and silver that do not use copper, such as Sn-Ag. In some embodiments, a reflow process may be performed to give solder region 126b a partially spherical shape in some embodiments. In other embodiments, solder area 126b may have other shapes, such as non-spherical shapes.

[0034] refer to Figure 1G Multiple integrated circuits 130a and 130b are bonded to the interposer 100. For example, the integrated circuits 130a and 130b are stacked on the interposer 100 along direction D1 (e.g., the z-direction), and the integrated circuits 130a and 130b and the interposer 100 extend in direction D2, respectively. In some embodiments, direction D1 is also referred to as the stacking direction of the integrated circuits 130a and 130b and the interposer 100.

[0035] Integrated circuits 130a and 130b may be the same or different. Each integrated circuit 130a and 130b may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die)), or a combination thereof. Integrated circuits 130a and 130b may be stacked devices comprising multiple semiconductor substrates (not shown). For example, integrated circuits 130a and 130b may be memory devices comprising multiple memory dies, such as hybrid memory cube (HMC) devices, high-bandwidth memory (HBM) devices, etc. In such embodiments, integrated circuits 130a and 130b include multiple semiconductor substrates interconnected via substrate through-holes (TSVs), such as through-silicon vias (not shown). Each semiconductor substrate may (or may not) have a separate interconnect structure. Integrated circuits 130a and 130b may have high bandwidth, I / O count, and / or high speed requirements. In some embodiments, integrated circuits 130a and 130b are SoC and HBM devices.

[0036] In some embodiments, integrated circuits 130a and 130b have different or the same dimensions (e.g., different heights and / or surface areas). For example, integrated circuits 130a and 130b have different widths along direction D2. In some embodiments, integrated circuits 130a and 130b have the same or different heights along direction D1.

[0037] Integrated circuits 130a and 130b may include a semiconductor substrate (not shown), a device layer (not shown), and interconnect structures (not shown). The semiconductor substrate may be an active layer of a doped or undoped silicon substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may contain other semiconductor materials, such as germanium; compound semiconductors comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0038] The device layer may include active components (e.g., transistors, diodes, etc.), capacitors, resistors, etc., or combinations thereof, and an interlayer dielectric (ILD) surrounding and covering the device. The ILD may include one or more dielectric layers formed of materials such as phosphorus-silicate glass (PSG), borosilicate glass (BSG), boron-doped phosphorus-silicate glass (BPSG), undoped silicate glass (USG), etc. Conductive plugs (not shown separately) may extend through the ILD to electrically and physically couple the device. For example, when the device is a transistor, the conductive plug connects the gate and source regions and the drain region of the transistor. The conductive plug may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or combinations thereof.

[0039] Interconnect structures are located above device layers and are used for electrically connecting devices to a semiconductor substrate. Interconnect structures may be located above the ILD and conductive plugs. Interconnect structures may include one or more dielectric layers and corresponding metallization layers within the dielectric layers. Acceptable dielectric materials for dielectric layers include low-k dielectric materials such as PSG, BSG, BPSG, USG, etc. Acceptable dielectric materials for dielectric layers also include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; similar materials; or combinations thereof, such as silicon oxynitride, silicon carbide oxide, silicon carbide nitride, silicon carbide nitride, etc. Other dielectric materials may also be used, such as polymers like polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, etc. Metallization layers may include vias and / or wires for devices interconnecting the semiconductor substrate. Metallization layers may be formed from conductive materials, such as metals, such as copper, cobalt, aluminum, gold, combinations thereof, etc. Interlocking structures can be formed by inlay techniques, such as single inlay or double inlay.

[0040] In some embodiments, integrated circuits 130a and 130b include a plurality of conductive connectors 132 at their outermost surfaces (e.g., bottom surfaces). The conductive connectors 132 are similar to the conductive connectors 126 described above and will not be repeated here. In the illustrated embodiment, the conductive connectors 132 include a bump base metal and solder areas on the bump base metal. However, the conductive connectors 132 may have other suitable configurations. In some embodiments, the conductive connectors 132 are in physical contact with corresponding conductive connectors 126 of the intermediate 100, such that solder areas 126b of the conductive connectors 126 are in physical contact with the corresponding conductive connectors 132 and solder joints 134 are formed therebetween. The solder joints 134 electrically and mechanically couple the integrated circuits 130a and 130b to the intermediate 100.

[0041] In some embodiments, a primer 136 is formed around the solder joints 134 and in the gap between the integrated circuits 130a, 130b and the interposer 100. The primer 136 can reduce stress and protect the solder joints 134. The primer 136 can be formed from a primer material such as molding compound, epoxy resin, etc. The primer 136 can be formed by a capillary flow process after the integrated circuits 130a, 130b are attached to the interposer 100, or by a suitable deposition method before the integrated circuits 130a, 130b are attached to the interposer 100. The primer 136 can be applied in liquid or semi-liquid form and then cured. In some embodiments, the primer 136 extends along the sidewalls of the integrated circuits 130a, 130b. However, this disclosure is not limited thereto. In other embodiments, the primer 136 is omitted. In some embodiments, the surface of the primer 136 (e.g., the top surface) is lower than the surface (e.g., the top surface) of the integrated circuits 130a, 130b. However, this disclosure is not limited thereto. In other embodiments, the surface (e.g., top surface) of the adhesive 136 is substantially coplanar with the surface (e.g., top surface) of the integrated circuits 130a, 130b.

[0042] refer to Figure 1G The substrate 102 of the intermediate 100 is thinned to expose the via 104. Exposure of the via 104 can be achieved through a thinning process, such as polishing, CMP, etch-back, or a combination thereof. In some embodiments, the thinning process for exposing the via 104 includes CMP. Subsequently, a conductive connection 128 is formed on the exposed surface of the intermediate 100, as referenced above. Figure 1E The conductive connector 126 described herein will not be repeated here. In the illustrated embodiment, the conductive connector 128 includes a bump base metal 128a and a solder area 128b on the bump base metal 128a. The bump base metal 128a and the solder area 128b can be used respectively with the above-referenced Figure 1E The bump base metal 126a and solder area 126b described herein are formed using similar materials and methods, and will not be repeated here. In another embodiment, an encapsulation is also formed to encapsulate integrated circuits 130a, 130b and base adhesive 136. In other embodiments providing an interposer wafer, a dicing process is performed after the formation of conductive interconnects 128. The dicing process is performed on the package assembly by cutting along a dicing track area (e.g., beside the package area). The dicing process may include sawing, etching, dicing, etc., or combinations thereof. In such an embodiment, the dicing process includes sawing the interconnect structure 110 and the substrate 102. The dicing process separates adjacent package areas to form such as Figure 1G The discrete semiconductor device is shown. The monomerized semiconductor device originates from the packaging area. The die-cutting process forms the intermediate 110 from the monomerized portion of the intermediate wafer. Furthermore, as... Figure 1GThe semiconductor device formed shown can be bonded to another circuit substrate via the conductive connector 128 of the intermediate 100.

[0043] In some embodiments, the interposer 100 has a composite dielectric comprising dielectric layers 112 and 114. Since dielectric layer 114 can have a large thickness and low k, parasitic capacitances (e.g., intra-layer parasitic capacitances) formed between conductive features (e.g., conductive features 122-1 and 122-2) can be reduced, and crosstalk can be lowered. Furthermore, the thick conductive feature 122 can provide low resistance. Therefore, the interconnect structure 110 of the interposer 100 can have low parasitic capacitance, a reduced effective dielectric constant, and low resistance, and thus can provide low insertion loss and improved signal integrity and / or electrical performance for integrated circuits 130a, 130b (such as HBM and SoC). Therefore, the interposer is suitable for semiconductor devices, such as HPC (High-Performance Computing) devices in 3DIC applications requiring high-speed and / or frequency electrical performance. Furthermore, stress can be modulated through dielectric layer 112, thus preventing warpage caused by the interposer, thereby obtaining reliable semiconductor devices, such as package structures.

[0044] Figure 2 This is a schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 2 semiconductor devices and Figure 1G Similar to semiconductor devices, the difference lies in the formation of the interconnect structure 110 of the intermediate 100. In some embodiments, at least one dielectric layer 114 (e.g., 114-1…114-(n+1)) and an upper dielectric layer 112 (e.g., 112-2…112-(n+2)) and the corresponding conductive features 124, 122 therein can be formed by… Figures 3A to 3J The method shown is used to form it.

[0045] refer to Figure 3A A dielectric layer 112 is provided on top of structure S, wherein a plurality of conductive features 122 are formed in the dielectric layer 112. Structure S may be Figure 2 The substrate 102 or any dielectric layer 114. In other words, the dielectric layer 112 can be... Figure 2 Any one of the dielectric layers 112. Then, a dielectric layer 114 is formed on the dielectric layer 112 along direction D1 (e.g., the z direction), and a dielectric layer 112 is formed on the dielectric layer 114. The dielectric layer 114 and the upper dielectric layer 112 can be... Figure 2Any two directly adjacent dielectric layers 114, 112 (e.g., 114-1 and 112-2… or 114-(n+1) and 112-(n+2)). In some embodiments, the materials of dielectric layers 112, 114 include undoped silicate glass (USG) or doped silicate glass, such as fluorinated silicate glass (FSG), phosphide silicate glass (PSG), borosilicate glass (BSG), boron-doped phosphide silicate glass (BPSG), silicon oxide, etc., or combinations thereof. Dielectric layers 112, 114 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on dielectric (SOD) processes, etc., or combinations thereof. The material and formation method of conductive feature 122 can be compared with reference to the reference. Figure 1A The description is similar, therefore its detailed description is omitted here. In some embodiments, etch stop layers 111 are formed directly beneath dielectric layers 112 and 114, respectively. The material and formation method of etch stop layers 111 are the same as those described in the reference. Figure 1A The description is similar, so its detailed description is omitted here. In some embodiments, the thickness T1 of dielectric layer 114 is greater than the thickness T2 of the upper dielectric layer 112. The ratio of thickness T1 to thickness T2 can be greater than 1.25. For example, the thickness T1 ranges from 2.5 μm to 3 μm, and the thickness T2 ranges from 0.5 μm to 1.5 μm.

[0046] refer to Figure 3B A patterned photoresist layer PR1 is formed on the dielectric layer 112. First, a photoresist layer (not shown) can be formed on the dielectric layer 112 by spin coating or the like. The photoresist layer can be a photosensitive material containing organic materials, and can be a positive or negative photosensitive material. Then, the photoresist layer can be exposed to be patterned to form the patterned photoresist layer PR1. In some embodiments, the patterned photoresist layer PR1 includes at least one opening, such as openings OP1 and OP2. In some embodiments, the width of opening OP1 is larger than the width of each opening OP2.

[0047] See Figure 3CAt least one opening, such as openings OP3 and OP4, is formed in dielectric layer 112 by using a patterned photoresist layer PR1 as a mask. Openings OP3 and OP4 can be formed by removing portions of dielectric layer 112 and the underlying etch stop layer 111. Removal methods can include etching processes, such as dry etching or wet etching. In some embodiments, opening OP3 has a width W1 along direction D2 (e.g., the x-direction), which is greater than the width W2 of each opening OP4. The aspect ratio of opening OP3 is, for example, in the range of 2.5 to 4.5. Opening OP3 may also be referred to as a trench opening. The width W2 of openings OP4 can be substantially the same or different. For example, opening OP3 is located directly above conductive feature 122 in the underlying dielectric layer 112, and opening OP4 is disposed adjacent to opening OP3. After forming openings OP3 and OP4 in dielectric layer 112, the patterned photoresist layer PR1 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma.

[0048] See Figure 3D A non-photosensitive material NPR is formed on dielectric layer 112 to fill openings OP3 and OP4. The non-photosensitive material NPR can cover and completely fill the openings OP3 and OP4 of dielectric layer 112. The material of the non-photosensitive material NPR contains polymers such as amorphous carbon, and is formed, for example, by spin coating or the like. The non-photosensitive material NPR can also be a bottom anti-reflective coating (BARC) layer or an ashing removal dielectric (ARD) layer (e.g., amorphous carbon). The non-photosensitive material NPR on dielectric layer 112 can have a thickness in the range of 1 μm to 1.5 μm. In some embodiments, after forming the non-photosensitive material NPR, a planarization process such as chemical mechanical planarization (CMP) can be performed to planarize the surface (e.g., top surface) S1 of the non-photosensitive material NPR. After the planarization process, the non-photosensitive material NPR can have a substantially flat surface S1. For example, the surface S1 of the non-photosensitive material NPR has good uniformity. In some embodiments, the non-photosensitive material NPR is also referred to as a non-photosensitive photoresist layer.

[0049] refer to Figure 3EA photoresist layer PR2 is formed on a non-photosensitive material NPR. The photoresist layer PR2 can be a photosensitive material containing organic materials, and can be a positive or negative photosensitive material. The photoresist layer PR2 can be formed by spin coating or the like. In some embodiments, since the non-photosensitive material NPR has a substantially flat surface S1, the photoresist layer PR2 formed thereon also has a substantially flat surface S2. Conversely, in embodiments where the photoresist layer PR2 is formed directly on a dielectric layer 112 including openings OP3 and OP4, due to the loading effect, the surface S2 of the photoresist layer PR2 may have poor uniformity, thus affecting subsequent patterning processes of the dielectric layer 112.

[0050] refer to Figure 3F The photoresist layer PR2 is patterned to form an opening OP5. The patterning process includes exposure and development processes. In some embodiments, the opening OP5 in the photoresist layer PR2 exposes the photosensitive material NPR in the opening OP3, while the photosensitive material NPR in the opening OP4 is covered by the photoresist layer PR2. The opening OP5 may be located directly on the opening OP3 or directly on the conductive feature 122 in the underlying dielectric layer 112. For example, the center line of the opening OP5 substantially overlaps with the center line of the opening OP3. The opening OP5 may have a width W1' smaller than the width W1 of the opening OP3, and the width W1' of the opening OP5 may be substantially equal to the desired width W1' of the conductive feature 124 to be formed (e.g., ...). Figure 3J (As shown).

[0051] See Figure 3G Using the photoresist layer PR2 as a mask, a portion of the non-photosensitive material NPR is removed, thereby forming an opening OP6 in the non-photosensitive material NPR. The removal method may include exposure and etching processes, such as dry etching or wet etching. In some embodiments, the portion of the non-photosensitive material NPR exposed by opening OP5 is removed to form opening OP6, which exposes the underlying dielectric layer 114. Figure 3G As shown, opening OP6 is a non-photosensitive material NPR set inside opening OP3, and the width W1' of opening OP6 is smaller than the width W1 of opening OP3.

[0052] refer to Figure 3HThe opening OP7 is formed by removing a portion of the dielectric layer 114 using a non-photosensitive material NPR with an opening OP6 as a mask. In some embodiments, the opening OP7 is formed by removing a portion of the dielectric layer 114 and the underlying etch stop layer 111 using an etching process such as a dry etching process or a wet etching process. The opening OP7 may expose the underlying conductive feature 122 in the underlying dielectric layer 112. The opening OP7 is, for example, having a width W1' corresponding to the width W1' of the opening OP6.

[0053] refer to Figure 3I The remaining photoresist layer PR2 and the remaining non-photosensitive material NPR are removed. For example, the non-photosensitive material NPR remaining in openings OP3 and OP4 and the photoresist layer PR2 remaining on the non-photosensitive material NPR are completely removed. The non-photosensitive material NPR and the photoresist layer PR2 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. The non-photosensitive material NPR and the photoresist layer PR2 can be removed simultaneously by the same process. After removal, opening OP7 is disposed in dielectric layer 114, and openings OP3 and OP4 are disposed in dielectric layer 112. In some embodiments, opening OP7 is a via opening, and opening OP3 is a trench opening connected to opening OP7. The width W1 of opening OP3 is larger than the width W1' of opening OP7.

[0054] refer to Figure 3JConductive feature 124 is formed in opening OP7, and conductive feature 122 is formed in opening OP3. In some embodiments, conductive feature 122 and the lower conductive feature 124 are formed by the same process, such as a dual damascene process. For example, a barrier material is formed on the sidewalls and bottom surfaces of openings OP3 and OP7, and then a conductive material is formed to fill openings OP3 and OP7. Subsequently, excess conductive and barrier materials outside openings OP3 and OP7 can be removed by a planarization process such as CMP to form conductive feature 124 in opening OP7 and conductive feature 122 in opening OP3. For example, conductive feature 124 (e.g., via) is in direct contact with the upper conductive feature 122 (e.g., wire) and the lower conductive feature 122 (e.g., wire). In some embodiments, conductive feature 124 and conductive feature 122 each include a conductive layer 121a and a barrier layer 121b surrounding the conductive layer 121a. The surface (e.g., top surface) of conductive feature 122 is substantially coplanar with the surface (e.g., top surface) of dielectric layer 112. For example, the surfaces (e.g., top surfaces) of conductive layer 121a and barrier layer 121b are substantially coplanar with the surface (e.g., top surface) of dielectric layer 112. The height H1 of conductive feature 124 is substantially equal to the thickness T1 of dielectric layer 114 (e.g., the total thickness of dielectric layer 114 and the underlying etch stop layer 111), and the height H2 of the upper conductive feature 122 is, for example, substantially equal to the thickness T2 of the upper dielectric layer 112 (e.g., the total thickness of dielectric layer 112 and the underlying etch stop layer 111). In some embodiments, the ratio of the height H1 of conductive feature 124 to the height H2 of upper conductive feature 122 can be greater than 1.25. It should be noted that conductive feature 124 and upper conductive feature 122 (as well as dielectric layer 114 and upper dielectric layer 112) can be disposed on... Figure 2 Any appropriate location of the intermediary 100 within the connecting structure 110.

[0055] In some embodiments, the thickness T1 of dielectric layer 114 is greater than the thickness T2 of the upper dielectric layer 112. Therefore, the ratio of the height H1 of the conductive feature 124 in dielectric layer 114 to the height H2 of the upper conductive feature 122 can be higher. Since dielectric layer 114 can have a greater thickness, parasitic capacitances (e.g., intra-layer parasitic capacitances) formed between conductive features 122 (e.g., conductive features 122-1 and 122-2) can be reduced. Therefore, the interposer 100 can provide low insertion loss and improved signal integrity and / or electrical performance for integrated circuits 130a, 130b (such as HBM and SoC (System-on-Integrated Circuit)). Therefore, the interposer is suitable for semiconductor devices in 3DIC applications requiring high-speed and / or frequency-based electrical performance, such as HPC devices. Furthermore, warpage caused by the interposer can be prevented, thus resulting in reliable semiconductor devices, such as package structures.

[0056] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 2 semiconductor devices and Figure 1G Similar to semiconductor devices, the difference lies in the formation of the interconnect structure 110 of the intermediate 100. In some embodiments, at least one dielectric layer 114 (e.g., 114-1…114-(n+1)) and an upper dielectric layer 112 (e.g., 112-2…112-(n+2)) and the corresponding conductive features 124, 122 therein can be derived from [see...]. Figures 5A to 5G The method shown is used to form it.

[0057] refer to Figure 5A A dielectric layer 112 is disposed above structure S, and multiple conductive features 122 are formed in the dielectric layer 112. Structure S can be... Figure 4 The substrate 102 or any dielectric layer 114. In other words, the dielectric layer 112 can be... Figure 4 Any one of the dielectric layers 112. Then, a dielectric layer 114 is formed on the dielectric layer 112 along direction D1 (e.g., the z-direction). For example, the dielectric layer 114 may have a thickness T1 in the range of 1 μm to 2 μm. In some embodiments, the materials of the dielectric layers 112, 114 include undoped silicate glass (USG) or doped silicate glass, such as fluorinated silicate glass (FSG), phosphorus-silicate glass (PSG), borosilicate glass (BSG), boron-doped phosphorus-silicate glass (BPSG), silicon oxide, etc., or combinations thereof. The dielectric layers 112, 114 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on dielectric (SOD) processes, etc., or combinations thereof. In some embodiments, an etch stop layer 111 is formed directly below the dielectric layers 112, 114, respectively. The materials and formation methods of the etch stop layer 111 are referenced. Figure 1A The description is similar, so its detailed description is omitted here.

[0058] refer to Figure 5B A patterned photoresist layer PR1 is formed on the dielectric layer 114. First, a photoresist layer (not shown) can be formed on the dielectric layer 114 by spin coating or the like. The photoresist layer can be a photosensitive material containing organic materials, and can be a positive or negative photosensitive material. Then, the photoresist layer can be exposed to be patterned to form the patterned photoresist layer PR1. In some embodiments, the patterned photoresist layer PR1 includes at least one opening OP1 and a plurality of openings OP2 laterally surrounding the opening OP1. In some embodiments, the size (e.g., width and / or length) of the opening OP1 is greater than the width of each opening OP2.

[0059] See Figure 5C The dielectric layer 114 is patterned using a patterned photoresist layer PR1 as a mask to form a plurality of openings OP3 and OP4 in the dielectric layer 114. The openings OP3 and OP4 can be formed by removing portions of the dielectric layer 114. Removal methods may include etching processes, such as dry etching or wet etching. For example, opening OP3 is formed directly on the conductive feature 122 in the underlying dielectric layer 112. In some embodiments, such as... Figure 5C and Figure 6A As shown, opening OP3 is laterally surrounded by opening OP4. Openings OP3 and OP4 may be substantially arranged in an array. The dimensions of opening OP3 are larger than those of opening OP4. For example, opening OP3 has a width W1 along direction D2 (e.g., the x-direction) and a width W2 along direction D3 (e.g., the y-direction), and opening OP4 has a width W1' smaller than width W1 along direction D2 and a width W2' smaller than width W2 along direction D3. For example, directions D1, D2, and D3 are substantially perpendicular to each other. In some embodiments, widths W1 and W2 are in the range of 0.7 μm to 1 μm, and widths W1' and W2' are less than 0.5 μm and may be in the range of 0.3 μm to 0.35 μm. The spacing SP between opening OP3 and opening OP4, or between opening OP4, is, for example, in the range of 0.4 μm to 0.6 μm. In some embodiments, opening OP3 is also referred to as a functional through-hole opening, and opening OP4 is also referred to as a virtual through-hole opening. After the openings OP3 and OP4 are formed in the dielectric layer 114, the patterned photoresist layer PR1 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma.

[0060] refer to Figure 5D A dielectric layer 112 is formed above dielectric layer 114 to seal openings OP3 and OP4, and multiple air gaps AG1 and AG2 are formed between dielectric layers 114 and 112. For example, dielectric layer 112 directly contacts and bonds to the underlying dielectric layer 114. The thickness T2 of dielectric layer 112 is, for example, in the range of 0.8 μm to 2 μm. In some embodiments, the material of dielectric layer 112 is formed on dielectric layer 112 by a deposition process such as CVD. The material of dielectric layer 112 can be... Figure 5AThe dielectric layer 112 described is similar to or the same as, and may be the same as or different from, dielectric layer 114. The deposited material of dielectric layer 112 may be suspended on top of openings OP3, OP4, thus sealing openings OP3, OP4 to form air gaps AG1, AG2. Air gaps AG1, AG2 may also be referred to as gaps (if no air is present), trenches, holes, etc., or combinations thereof. Air gaps AG1, AG2 are partially disposed in dielectric layer 114 and partially disposed in the upper dielectric layer 112. That is, the lower portion of air gaps AG1, AG2 is disposed in dielectric layer 114 (e.g., surrounded), and the upper portion of air gaps AG1, AG2 is disposed in the upper dielectric layer 112 (e.g., surrounded). For example, air gaps AG1, AG2 are exposed to and in direct contact with etch stop layer 111. Figure 5D As shown, since the dielectric layer 112 partially fills the openings OP3 and OP4, the shapes of air gaps AG1 and AG2 can be trapezoidal or trapezoidal. In other words, air gaps AG1 and AG2 can have a top width larger than the bottom width, and the width of air gaps AG1 and AG2 can decrease as air gaps AG1 and AG2 become closer to the surface (e.g., the top surface) of the upper dielectric layer 112. However, this disclosure is not limited to this. Air gaps AG1 and AG2 can have any suitable shape. In some embodiments, the height H1' of air gap AG1 is greater than the height H1 of opening OP3 (i.e., the thickness of dielectric layer 114), the height H2' of air gap AG2 is greater than the height H2 of opening OP4, and the height H1' of air gap AG1 is greater than the height H2' of air gap AG2. For example, air gap AG1 has a height H1' greater than 2.5 μm, and the height H2' of air gap AG2 is greater than 2 μm. In some embodiments, such as Figure 5D As shown, an interface IN may exist between dielectric layer 114 and the upper dielectric layer 112. Interface IN is shown as a straight line; however, depending on the deposited material of the upper dielectric layer 112, the interface IN between dielectric layer 114 and the upper dielectric layer 112 may be curved or similar. In other embodiments where dielectric layer 114 and the upper dielectric layer 112 are made of the same material, there may be no interface or an unobservable interface between dielectric layer 114 and the upper dielectric layer 112. It should be noted that dielectric layer 114 and the upper dielectric layer 112 are represented by dots to clearly show the air gap therein and are not intended to indicate that the materials of dielectric layer 114 and dielectric layer 112 are the same or different.

[0061] In some embodiments, Figure 5DThe heights SH1 and SH2 shown can also be referred to as sealing heights. Height SH1 can be controlled by the widths W1 and W2 of the opening OP3 in dielectric layer 114, and similarly, height SH2 can be controlled by the widths W1' and W2' of the opening OP4 in dielectric layer 114. For example, controlling heights SH1 and SH2 ensures that the conductive feature 124 (e.g., a functional via) to be formed... Figure 5G (As shown) has a height H11 that is larger than the height H2' of the air gap AG2 (e.g., a dummy through hole).

[0062] refer to Figure 5E A patterned photoresist layer PR2 with openings OP5 and OP6 is formed on dielectric layer 114. For example, opening OP5 is formed directly above air gap AG1, and opening OP6 is formed next to opening OP5 and directly above air gap AG2. Both openings OP5 and OP6 have a corresponding conductive feature 122 (such as a wire). Figure 5G The width of the opening OP5 (as shown). In some embodiments, the width of the opening OP5 is larger than the width of the air gap AG1.

[0063] refer to Figure 5F By using a photoresist layer PR2 as a mask, portions of dielectric layers 114 and 112 are removed to form openings OP7, OP8, and OP9 in dielectric layer 112. Openings OP7, OP8, and OP9 can be formed by removing portions of dielectric layers 114 and 112, as well as etch stop layer 111, using an etching process such as dry etching or wet etching. In some embodiments, opening OP7 exposes air gap AG1, thus forming opening OP8 from and connecting to opening OP7. Opening OP7 can be formed in dielectric layer 112, and opening OP8 can be formed in both dielectric layers 112 and 114. Opening OP8 may expose underlying conductive feature 122 in the underlying dielectric layer 112. In some embodiments, opening OP9, corresponding to opening OP6, is formed next to opening OP7 in dielectric layer 112, and opening OP9 is formed above air gap AG2. The depth of opening OP9 can be substantially the same as the depth of opening OP7. In some embodiments, openings OP7 and OP9 are also referred to as trench openings, and opening OP8 is also referred to as through-hole openings.

[0064] refer to Figure 5GConductive feature 124 is formed in opening OP8, and conductive feature 122 is formed in opening OP7. In some embodiments, conductive feature 122 and the lower conductive feature 124 are formed by the same process, such as a dual damascene process. For example, a barrier material is formed on the sidewalls and bottom surfaces of openings OP7 and OP8, and then a conductive material is formed to fill openings OP7 and OP8. Subsequently, excess conductive and barrier materials outside openings OP7 and OP8 can be removed by a planarization process such as CMP to form conductive feature 124 in opening OP8 and conductive feature 122 in opening OP7. For example, conductive feature 124 (e.g., via) is in direct contact with the upper conductive feature 122 (e.g., wire) and the lower conductive feature 122 (e.g., wire). In some embodiments, conductive feature 124 and conductive feature 122 each include a conductive layer 121a and a barrier layer 121b surrounding the conductive layer 121a. The surface (e.g., top surface) of the upper conductive feature 122 is substantially coplanar with the surface (e.g., top surface) of the upper dielectric layer 112. For example, the surfaces (e.g., top surfaces) of conductive layer 121a and barrier layer 121b are substantially coplanar with the surface (e.g., top surface) of dielectric layer 112. The height H1 of conductive feature 124 is greater than the thickness T1 of dielectric layer 114; in other words, conductive feature 124 is, for example, partially disposed in dielectric layer 114 and partially disposed in the upper dielectric layer 112. For example, the height H1 of conductive feature 124 is also greater than the height H2' of air gap AG2. That is, the surface (e.g., top surface) of conductive feature 124 is higher than the surface (e.g., top surface) of air gap AG2. As air gap AG2 becomes closer to the upper conductive feature 122, the width of air gap AG1 can be reduced. For example, the height H2 of upper conductive feature 122 is less than the thickness T2 of upper dielectric layer 112.

[0065] like Figure 6B As shown in the top view, air gaps AG2 can be arranged laterally around conductive feature 124 (e.g., via). Air gaps AG2 can also be arranged laterally around conductive feature 122 (e.g., wire) in the underlying dielectric layer 112. For example, air gaps AG2 are substantially arranged in an array. In some embodiments, conductive feature 124 can also be referred to as a functional feature (e.g., functional via), and air gaps AG2 can also be referred to as virtual features (e.g., virtual vias). In some embodiments, dielectric layer 114 has multiple air gaps AG2, so dielectric layer 114 can also be referred to as a porous structure. In some embodiments, dielectric layer 114 and the upper dielectric layer 112 can also be collectively referred to as a composite dielectric layer, which has a large total thickness. In some embodiments, it should be noted that there is no etch stop layer between dielectric layer 114 and the upper dielectric layer 112.

[0066] In some embodiments, the dielectric layer 114 has multiple air gaps AG2, which can effectively reduce the dielectric constant. For example, the dielectric constant of a dielectric layer 114 without air gaps AG2 (e.g., USG) is approximately 4.3, and the dielectric constant of a dielectric layer 114 with air gaps AG2 (e.g., USG) is in the range of 2.1 to 4.2. Therefore, parasitic capacitances (e.g., intra-layer parasitic capacitances) formed between conductive features (e.g., conductive features 122-1 and 122-2) can also be reduced. Thus, the dielectric 100 can provide low insertion loss and improved signal integrity and / or electrical performance for integrated circuits 130a, 130b (such as HBM (High Bandwidth Memory) and SoC (System on Integrated Circuit)). Therefore, the dielectric is suitable for semiconductor devices in 3DIC applications requiring high-speed and / or frequency-based electrical performance, such as HPC (High-Performance Computing) devices. Furthermore, warpage caused by the dielectric can be prevented, thus resulting in reliable semiconductor devices, such as package structures.

[0067] In the above embodiments, the dielectric layer 114 and the upper dielectric layer 112 are utilized Figures 1A to 1C , Figures 3A to 3J and Figures 5A to 5G The dielectric layer 114, the upper dielectric layer 112, and the conductive features 122 and 124 may be formed by one of the methods shown. However, this disclosure is not limited thereto. Figures 1A to 1C , Figures 3A to 3J , Figures 5A to 5G The methods shown are combined. In other words, it can be achieved using methods such as... Figures 1A to 1C , Figures 3A to 3J as well as Figures 5A to 5G The different methods shown form the interconnecting structure 110 of the intermediary 100. Furthermore, although... Figures 1A to 1C , Figures 3A to 3J as well as Figures 5A to 5G The method shown is for forming the internal structure of the intermediary, but the present invention is not limited thereto. In other words, Figures 1A to 1C , Figures 3A to 3J as well as Figures 5A to 5G The method shown can be used to form interconnect structures in a die, redistribution layer structures in a semiconductor package, or any other interconnect structure.

[0068] Figure 7A flowchart of a method for forming a semiconductor device according to some embodiments is shown. Although the method is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the shown sequence or actions. Therefore, in some embodiments, actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0069] At action S202, the first dielectric layer is formed. Figure 3A Views corresponding to some embodiments of action S202 are shown.

[0070] At action S204, a second dielectric layer is formed on the first dielectric layer, and the second dielectric layer has a first opening. Figure 3B and Figure 3C Views corresponding to some embodiments of action S204.

[0071] At action S206, a non-photosensitive material is formed in the first opening. Figure 3D Views corresponding to some embodiments of action S206 are shown.

[0072] At action S208, a second opening is formed in the non-photosensitive material within the first opening, wherein the second opening has a width smaller than that of the first opening and exposes the first dielectric layer. Figures 3E to 3G Views corresponding to some embodiments of action S208 are shown.

[0073] At action S210, a portion of the first dielectric layer is removed by using a non-photosensitive material as a mask to form a third opening, which connects to the first opening. Figure 3H Views corresponding to some embodiments of action S210 are shown.

[0074] During action S212, the remaining non-photosensitive material in the first opening is removed. Figure 3I Views corresponding to some embodiments of action S212 are shown.

[0075] At action S214, a through hole is formed in the third opening and a wire is formed in the first opening. Figure 2 and Figure 3J Views corresponding to some embodiments of action S214 are shown.

[0076] According to some embodiments, a semiconductor device includes an interconnect structure. The interconnect structure includes a first conductive line in a first dielectric layer, a via in a second dielectric layer, and a second conductive line in a third dielectric layer, wherein the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer, and the dielectric constant of the second dielectric layer is less than the dielectric constants of the first dielectric layer and the third dielectric layer.

[0077] According to some embodiments, the difference between the dielectric constants of the first dielectric layer and the second dielectric layer is not less than 0.5, and the difference between the dielectric constants of the third dielectric layer and the second dielectric layer is not less than 0.5.

[0078] According to some embodiments, the dielectric constant of the second dielectric layer is in the range of 2.5 to 3.5, the dielectric constant of the first dielectric layer is in the range of 3.5 to 4.5, and the dielectric constant of the third dielectric layer is in the range of 3.5 to 4.5.

[0079] According to some embodiments, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer and the thickness of the third dielectric layer, respectively.

[0080] According to some embodiments, it also includes etch stop layers located directly below the first dielectric layer, the second dielectric layer, and the third dielectric layer, respectively.

[0081] According to some embodiments, a semiconductor device includes an interconnect structure. The interconnect structure includes: a conductive feature located in a first dielectric layer; and a via located in a second dielectric layer above the first dielectric layer and electrically connected to the conductive feature. The second dielectric layer includes a plurality of air gaps, and the air gaps laterally surround the via.

[0082] According to some embodiments, the air gaps are substantially arranged in an array.

[0083] According to some embodiments, the height of the through hole is greater than the height of each of the air gaps.

[0084] According to some embodiments, a conductor is also included, located in the second dielectric layer and physically connected to the via, wherein the via is located between the conductive feature and the conductor, and the first surface of the conductor is substantially coplanar with the first surface of the second dielectric layer.

[0085] According to some embodiments, the second dielectric layer includes a third dielectric layer and a fourth dielectric layer in direct contact with the third dielectric layer, and the air gap is formed between the third dielectric layer and the fourth dielectric layer.

[0086] According to some embodiments, the lower part of the air gap is located in the third dielectric layer, and the upper part of the air gap is located in the fourth dielectric layer.

[0087] According to some embodiments, a conductor is also included, the conductor being located in the second dielectric layer and physically connected to the via, wherein the width of one of the air gaps decreases as the one of the air gaps becomes closer to the conductor.

[0088] According to some embodiments, an etch stop layer is also included directly beneath the second dielectric layer, wherein the air gap is exposed to the etch stop layer.

[0089] According to some embodiments, the system also includes a plurality of integrated circuits, wherein the integrated circuits are coupled to the interconnect structure to be electrically connected to each other through the interconnect structure.

[0090] According to some embodiments, a method for forming a semiconductor device includes the following steps: forming a first dielectric layer; forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a first opening; forming a non-photosensitive material in the first opening; forming a second opening in the non-photosensitive material within the first opening, wherein the second opening has a width smaller than the first opening and exposes the first dielectric layer; using the non-photosensitive material as a mask, removing a portion of the first dielectric layer to form a third opening, the third opening connecting to the first opening; removing the remaining non-photosensitive material in the first opening; forming a via in the third opening and forming a wire in the first opening.

[0091] According to some embodiments, the non-photosensitive material is also formed on the second dielectric layer and has a substantially flat surface.

[0092] According to some embodiments, the second opening is formed by: forming a photoresist layer on the non-photosensitive material on the second dielectric layer; patterning the photoresist layer; and removing a portion of the non-photosensitive material by using the patterned photoresist layer as a mask.

[0093] According to some embodiments, the method also includes removing the remaining photoresist layer over the remaining non-photosensitive material.

[0094] According to some embodiments, the remaining non-photosensitive material and the remaining photoresist layer are removed by the same process.

[0095] According to some embodiments, the remaining non-photosensitive material and the remaining photoresist layer are removed by the same process.

[0096] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: an interconnect structure including a first wire in a first dielectric layer, a via in a second dielectric layer, and a second wire in a third dielectric layer, wherein the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer, and a dielectric constant of the second dielectric layer is less than a dielectric constant of the first dielectric layer and a dielectric constant of the third dielectric layer.

2. The semiconductor device of claim 1, wherein a difference between the dielectric constant of the first dielectric layer and the second dielectric layer is not less than 0.5, and a difference between the dielectric constant of the third dielectric layer and the second dielectric layer is not less than 0.

5.

3. The semiconductor device of claim 1, wherein the dielectric constant of the second dielectric layer is in a range of 2.5 to 3.5, the dielectric constant of the first dielectric layer is in a range of 3.5 to 4.5, and the dielectric constant of the third dielectric layer is in a range of 3.5 to 4.

5.

4. The semiconductor device of claim 1, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer and a thickness of the third dielectric layer, respectively.

5. A semiconductor device, comprising: an interconnect structure including: a conductive feature in a first dielectric layer; and a via in a second dielectric layer over the first dielectric layer and electrically connected to the conductive feature, wherein the second dielectric layer includes a plurality of air gaps, and the air gaps laterally surround the via.

6. The semiconductor device of claim 5, wherein the air gaps are substantially arranged in an array.

7. The semiconductor device of claim 5, wherein a height of the via is greater than a height of each of the air gaps.

8. The semiconductor device of claim 5, further comprising a wire in the second dielectric layer and physically connected to the via, wherein the via is between the conductive feature and the wire, and a first surface of the wire is substantially coplanar to a first surface of the second dielectric layer.

9. The semiconductor device of claim 5, wherein the second dielectric layer includes a third dielectric layer and a fourth dielectric layer directly contacting the third dielectric layer, and the air gaps are formed between the third dielectric layer and the fourth dielectric layer.

10. The semiconductor device of claim 5, further comprising a wire in the second dielectric layer and physically connected to the via, wherein a width of one of the air gaps decreases as the one of the air gaps becomes closer to the wire.

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