SSD test board

Abstract

The utility model discloses an SSD test board, which is used for testing an MI function and an MCTP function of an SSD and comprises a mainboard, a PCH, a BMC and a switch chip, the PCH, the BMC and the switch chip are integrated on the mainboard, the PCH and the BMC are simultaneously connected with the switch chip, the switch chip is connected with the SSD, the BMC is provided with an IO pin, and the IO pin is connected with the switch chip; when the MI function of the SSD needs to be tested, controlling the level of the IO pin through the BMC so as to control the switch chip to be communicated with the PCH; and when the MCTP function of the SSD needs to be tested, controlling the level of the IO pin through the BMC so as to control the switch chip to be communicated with the BMC. According to the utility model, the same test board not only can test the MI function of the SSD, but also can test the MCTP function of the SSD.

Description

TECHNICAL FIELD

[0001] The utility model relates to SSD test technical field, especially relate to a kind of SSD test board. BACKGROUND

[0002] SSD test board is mainly used for the test equipment of SSD, and the SSD hard disk customer of server needs to test MCTP function, but the SMBus pulled out by bridge piece only supports normal MI function, cannot support MCTP, only BMC can support MCTP, but BMC cannot carry out normal MI function test, thus cannot achieve the scheme of both compatible. UTILITY MODEL CONTENT

[0003] In view of the deficiencies of prior art, the utility model provides a kind of SSD test board, realize the MI function of same test board that can test SSD, also can test the MCTP function of SSD.

[0004] The utility model is realized by the following technical schemes:

[0005] A kind of SSD test board for testing the MI function and MCTP function of SSD, including mainboard and the PCH, BMC and switch chip integrated on the mainboard, the PCH and BMC are simultaneously connected with the switch chip, the switch chip is connected with the SSD, and the BMC has IO pin, and the IO pin is connected with the switch chip;

[0006] When the MI function of the SSD needs to be tested, the IO pin level is controlled by the BMC in turn to control the switch chip to connect the PCH;

[0007] When the MCTP function of the SSD needs to be tested, the IO pin level is controlled by the BMC in turn to control the switch chip to connect the BMC.

[0008] Further, the switch chip is connected with the SSD by SMBus bus.

[0009] Further, the GPIO pin on the BMC is connected with the SSD.

[0010] Further, the backboard is further provided with a plurality of second communication interfaces and a plurality of SSD slots for inserting the SSDs, the plurality of second communication interfaces are connected with the plurality of SSD slots one by one, the mainboard is further provided with a CPU and a plurality of first communication interfaces connected with the CPU, and the plurality of first communication interfaces are connected with the plurality of second communication interfaces one by one, the switch chip is connected with the first communication interface, wherein the first communication interface and the second communication interface both support at least PCIe protocol.

[0011] Further, the plurality of first communication interfaces are arranged along the same edge of the mainboard.

[0012] Further, the CPU is arranged close to the first communication interface.

[0013] Further, the plurality of second communication interfaces are arranged along the same edge of the backboard.

[0014] Further, the first communication interface and the second communication interface both adopt MCIO interface, the MCIO interface is provided with buckles, and the buckles are used for fixing high-speed lines for leading out PCIe signals.

[0015] Further, the CPU is connected with a plurality of groups of independent PCIe 4X signal lines, and the plurality of groups of PCIe 4X signal lines are connected with the plurality of first communication interfaces one by one.

[0016] Further, the PCIe 4X signal line is provided with four groups, and the four groups of PCIe 4X signal lines are all independent and respectively control the plurality of SSD slots.

[0017] Compared with the prior art, the utility model has the advantages that:

[0018] 1. The switch chip is connected with the PCH and the BMC, the switch chip is connected with the SSD, the BMC is provided with IO pins, the IO pins are connected with the switch chip, when the MI function of the SSD needs to be tested, the IO pin level is controlled by the BMC to control the switch chip to be connected with the PCH, when the MCTP function of the SSD needs to be tested, the IO pin level is controlled by the BMC to control the switch chip to be connected with the BMC, the same test board can test the MI function and the MCTP function of the SSD, the customer can test two functions by purchasing only one device, and the satisfaction of the customer is improved.

[0019] 2. By integrating multiple primary communication interfaces directly onto the motherboard, the PCIe on the CPU is transferred to the backplane, and then transferred to the SSD through the backplane. The PCIe signal transfer only occurs twice, effectively reducing signal loss caused by the transfer. The PCIe signal quality is effectively improved, which is far superior to Intel's design standard, laying a solid foundation for the company's test platform.

[0020] 3. This application utilizes a custom-developed BIOS to maximize the splitting of PCIe signals in the CPU. One CPU can output multiple sets of PCIe signal lines, and each set of PCIe 4X signal lines is independent and controls multiple SSD slots independently. This allows for simultaneous testing of multiple PCIe 5.0 SSDs, maximizing the use of PCIe signals in the CPU. More SSDs can be connected during testing, reducing the cost per port and greatly improving testing efficiency, thus meeting customers' needs for large-volume SSD testing.

[0021] 4. By adopting MCIO interfaces for both the first and second communication interfaces, the MCIO interface can transmit high-speed signals. It is not only compatible with PCIe signals, but also has a latch to fix the high-speed line leading out the PCIe signal, preventing the high-speed line from becoming loose and ensuring stable signal transmission.

[0022] 5. By placing the first communication interface on the edge of the motherboard and placing multiple second communication interfaces on the same edge of the backplane, the high-speed cable connecting the first and second communication interfaces can be shortened to the maximum extent, effectively reducing signal attenuation and enhancing signal quality.

[0023] 6. By placing the CPU close to the first communication interface, the PCIe signal trace from the CPU to the MCIO interface is minimized and optimized, thus reducing trace length to the greatest extent, effectively reducing signal attenuation, and enhancing signal quality. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the SSD test board structure;

[0025] Figure 2 This is a schematic diagram of the MCIO interface distribution on the SSD test board.

[0026] Figure 3 A schematic diagram of the CPU splitting PCIe architecture;

[0027] Figure 4 This is a schematic diagram of a single / dual channel system.

[0028] Figure 5 This is a schematic diagram of the MCIO interface.

[0029] 1. SSD; 2. Motherboard; 20. First communication interface; 3. PCH; 4. BMC; 40. IO pins; 5. Switch chip; 6. Backplane; 60. Second communication interface; 7. CPU; 9. Clip. Detailed Implementation

[0030] The following detailed, non-limiting description of the utility model's technical solution, in conjunction with preferred embodiments and accompanying drawings, is provided. In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0031] like Figure 1 As shown, an embodiment of this utility model discloses an SSD test board for testing the MI and MCTP functions of an SSD 1. The board includes a motherboard 2 and a PCH 3, BMC 4, and switch chip 5 integrated on the motherboard 2. The PCH 3 and BMC 4 are both connected to the switch chip 5, which is connected to the SSD 1. The BMC 4 has an I / O pin 40 connected to the switch chip 5. When testing the MI function of the SSD 1, the BMC 4 controls the level of the I / O pin 40, thereby controlling the switch chip 5 to connect to the PCH 3. When testing the MCTP function of the SSD 1, the BMC 4 controls the level of the I / O pin 40, thereby controlling the switch chip 5 to connect to the BMC 4. This allows the same test board to test both the MI and MCTP functions of the SSD, enabling customers to complete both functions at the cost of purchasing only one device, thus improving customer satisfaction.

[0032] Switch chip 5 is connected to SSD 1 via SMBus bus.

[0033] like Figure 2As shown, the SSD test board further comprises a backboard 6, the backboard 6 is integrated with a plurality of second communication interfaces 60 and a plurality of SSD slots for inserting the SSD 1, the plurality of second communication interfaces 60 are connected in one-to-one correspondence with the plurality of SSD slots, the mainboard 2 is further integrated with a CPU 7 and a plurality of first communication interfaces 20 connected with the CPU 7, and the plurality of first communication interfaces 20 are connected in one-to-one correspondence with the plurality of second communication interfaces 60, and the switch chip 5 is connected with the first communication interface 20, wherein the first communication interface 20 and the second communication interface 60 both support at least PCIe protocol. In this application, by directly integrating a plurality of first communication interfaces 20 on the mainboard 2, the PCIe signal on the CPU is connected to the backboard 6, and then connected to the SSD through the backboard 6, the number of times of connecting the PCIe signal is only twice, effectively reducing the signal loss caused by connection, effectively improving the quality of the PCIe signal, which is much better than the intel design standard, and lays a solid foundation for the company's test platform.

[0034] In this embodiment, referring to Figure 2 , the plurality of first communication interfaces 20 are arranged in sequence along the same edge of the mainboard 2, and the plurality of second communication interfaces 60 are arranged in sequence along the same edge of the backboard 6, the first communication interface 20 in this application can be flexibly adjusted in position and is not limited by the position of the PCIe interface on the mainboard 2, and by arranging the first communication interface 20 on the edge of the mainboard 2 and arranging the plurality of second communication interfaces 60 on the same edge of the backboard 6, the high-speed line connected by the first communication interface 20 and the second communication interface 60 can be shortened to the maximum extent, effectively reducing signal attenuation and enhancing signal quality.

[0035] In addition, the CPU 7 is arranged close to the first communication interface 20, by adjusting the position of the CPU 7 in the mainboard 2, the PCIe signal wiring from the CPU to the MCIO interface is the shortest and the best, which can shorten the wiring length to the maximum extent, effectively reducing signal attenuation and enhancing signal quality.

[0036] As shown in Figure 5 , the first communication interface 20 and the second communication interface 60 both adopt MCIO interface, the MCIO interface has a buckle 9 for fixing the high-speed line leading out the PCIe signal. Specifically, the multi-channel PCIe signal in the CPU 7 is pulled into the MCIO interface, the MCIO interface can transmit high-speed signals, not only can it be compatible with PCIe signals, but also the MCIO interface has a buckle 9 for fixing the high-speed line leading out the PCIe signal, avoiding the problem of loosening of the high-speed line, and ensuring stable signal transmission.

[0037] As shown in Figure 3As shown, in the present application, the PCIe signals in the CPU can be maximally split by custom development of the BIOS, one CPU pulls out multiple groups of PCIe signal lines, in the embodiment, the CPU 7 is connected with multiple independent PCIe 4X signal lines, and the multiple PCIe 4X signal lines are connected one by one with the multiple first communication interfaces 20. The PCIe 4X signal line is provided with four groups, and the four groups of PCIe 4X signal lines are all independent and respectively control multiple SSD slots. Four PCIe 5.0 SSDs can be supported for simultaneous testing, the PCIe signals in the CPU are maximally utilized, more SSDs can be connected during testing, the cost of the unit port is reduced, the test efficiency is greatly improved, and the large batch SSD test demand of customers is met.

[0038] As shown in the figure, Figure 4 As shown, the GPIO pin on the BMC 4 is connected with the SSD 1, and by custom development of the BIOS, the PCIe signals in the CPU can be further split, and the PCIe 4X signals can be further split into PCIe 2X signals. During testing, the GPIO signal emitted by the GPIO pin of the BMC 4, the BMC 4 can send a control signal to the SSD 1 by controlling the level state of the GPIO pin, when the BMC 4 sets the GPIO pin to low level, the SSD enters the dual-channel mode, otherwise, when the GPIO pin is set to high level, the SSD enters the single-channel mode. The function of normally recognizing the disk and normally testing the SSD dual-channel in one motherboard is realized, so that all types of hard disks can be directly tested by one set of system in the future test, which is convenient for customers to use. The motherboard designed by the scheme can normally work in dual-channel and single-channel mode, the customer only needs to purchase one device to complete the test of two types of SSDs, and the satisfaction of customers is improved.

[0039] The above-described embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it cannot be understood as limiting the scope of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An SSD test board for testing the MI function and MCTP function of an SSD (1), characterized in that, Includes a motherboard (2) and a PCH (3), BMC (4) and switch chip (5) integrated on the motherboard (2). The PCH (3) and BMC (4) are connected to the switch chip (5). The switch chip (5) is connected to the SSD (1). The BMC (4) has IO pins (40) that are connected to the switch chip (5). When it is necessary to test the MI function of the SSD (1), the BMC (4) controls the level of the IO pin (40) and thus controls the switch chip (5) to connect to the PCH (3); When it is necessary to test the MCTP function of the SSD (1), the level of the IO pin (40) is controlled by the BMC (4), thereby controlling the switch chip (5) to connect to the BMC (4).

2. The SSD test board according to claim 1, characterized in that, The switch chip (5) is connected to the SSD (1) via the SMBus bus.

3. An SSD test board according to claim 1, characterized in that, The GPIO pins on the BMC (4) are connected to the SSD (1).

4. An SSD test board according to claim 1, characterized in that, It also includes a backplate (6), on which multiple second communication interfaces (60) and multiple SSD slots for inserting the SSD (1) are integrated. The multiple second communication interfaces (60) are connected to the multiple SSD slots one by one. The motherboard (2) also integrates a CPU (7) and multiple first communication interfaces (20) connected to the CPU (7). The multiple first communication interfaces (20) are connected to the multiple second communication interfaces (60) one by one. The switch chip (5) is connected to the first communication interface (20). The first communication interface (20) and the second communication interface (60) both support at least the PCIe protocol.

5. An SSD test board according to claim 4, characterized in that, Multiple first communication interfaces (20) are arranged sequentially along the same edge of the motherboard (2).

6. An SSD test board according to claim 5, characterized in that, The CPU (7) is positioned close to the first communication interface (20).

7. An SSD test board according to claim 4, characterized in that, Multiple second communication interfaces (60) are arranged sequentially along the same edge of the backplate (6).

8. An SSD test board according to claim 4, characterized in that, Both the first communication interface (20) and the second communication interface (60) adopt the MCIO interface. The MCIO interface has a latch (9) for fixing the high-speed line that leads out the PCIe signal.

9. An SSD test board according to claim 4, characterized in that, The CPU (7) is connected to multiple independent PCIe 4X signal lines, and the multiple PCIe 4X signal lines are connected one-to-one with multiple first communication interfaces (20).

10. An SSD test board according to claim 4, characterized in that, The PCIe 4X signal lines are provided in four groups, and each of the four groups of PCIe 4X signal lines is independent and controls multiple SSD slots independently.

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