CMOS device and integrated circuit
By introducing a radiation hardening buffer surrounding the source and drain regions in CMOS devices, the leakage path problem caused by total dose irradiation is solved, improving the radiation resistance of the devices while maintaining the basic stability and cost-effectiveness of the device structure and process.
Patent Information
- Application Number
- CN202520006928.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2035-01-02
AI Technical Summary
Existing CMOS devices are insufficient in terms of total dose irradiation resistance. Conventional hardening methods can alter the device structure or increase costs, and cannot effectively solve the leakage path problem caused by total dose irradiation.
In CMOS devices, a radiation hardening buffer is introduced around the source and drain regions. By setting a P-type radiation hardening buffer and an isolation region to isolate the source and drain regions, the main structure and process of the device remain basically unchanged. The same process is used to form a lightly doped buffer to prevent the formation of leakage channels.
Without altering the main structure and process of the device, the radiation resistance of CMOS devices is effectively improved, the impact of total dose radiation on the device is reduced, the adverse effects on device performance are minimized, and costs are lowered.
Smart Images
Figure CN223786401U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of semiconductor technology, concretely relates to a CMOS device and integrated circuit. BACKGROUND
[0002] Good anti-radiation capability is the most basic requirement for electronic systems used in special scenarios such as spaceflight, aviation and space station, and the comprehensive anti-radiation capability of components (including integrated circuits) applied to the electronic systems is a decisive factor for meeting this requirement. In terms of electronic components, the radiation effects are most typical in total dose radiation effects and single particle effects. Among them, the total dose radiation effect is mainly the charge accumulation effect caused by the destruction of SiO2 chemical bonds in the isolation region in the device by cosmic rays.
[0003] The conventional total dose anti-radiation reinforcement method is divided into three categories of system level, device level and process level anti-radiation reinforcement. The system level anti-radiation reinforcement is mainly based on redundant design, which can greatly improve the anti-radiation performance, but occupies a large chip space and has a high cost. The device level anti-radiation reinforcement is mainly through special design of the device structure to enhance the anti-total dose radiation capability. In the conventional CMOS device, the typical anti-radiation device design includes ring gate, large head gate, inverse proportional gate and P+ protection ring reinforcement design. Although this method can effectively improve the anti-radiation capability of the components, the above method strictly limits the channel size of the device, and also makes the shape of the gate more complex, which brings great restriction to design, process and parameter modeling. The process level anti-radiation reinforcement, such as silicon surface layer high concentration injection at the bottom of the isolation region, improves the difficulty of being inverted and thus improves the anti-radiation capability. Although this method can improve the anti-radiation capability to a certain extent, it cannot fundamentally solve the problem of total dose radiation effect.
[0004] Therefore, how to solve the total dose radiation problem without changing the device main body structure and size and process as much as possible is an urgent problem in the anti-radiation field. UTILITY MODEL CONTENT
[0005] In order to overcome the above defects, the utility model is provided to solve the total dose radiation problem without changing the device main body structure and size and process as much as possible.
[0006] In the first aspect, the utility model provides a CMOS device, which comprises:
[0007] a substrate;
[0008] a well region extending from the surface of the substrate into the substrate;
[0009] a gate structure located on the side of the well region away from the substrate, the gate structure comprising a gate dielectric layer and a gate electrode stacked.
[0010] a source-drain implant region inside the well region, the source-drain implant region comprising a source region and a drain region, and the source region and the drain region are located at two sides of the gate structure respectively;
[0011] a radiation-hardened buffer region inside the well region, and surrounding the source region and the drain region; wherein the substrate, the well region and the radiation-hardened buffer region are of a first doping type, and the source-drain implant region is of a second doping type different from the first doping type;
[0012] an isolation region on the surface of the substrate, and a projection of the isolation region on the substrate surface surrounds a projection of the radiation-hardened buffer region on the substrate surface.
[0013] Further, in the CMOS device as described above, the doping concentration of the radiation-hardened buffer region is the same as the doping concentration of the well region, and the radiation-hardened buffer region and the well region are formed by the same process.
[0014] Further, in the CMOS device as described above, the doping concentration of the radiation-hardened buffer region and the doping concentration of the well region are both light doping concentrations.
[0015] The doping concentration of the source region and the doping concentration of the drain region are both heavy doping concentrations.
[0016] Further, in the CMOS device as described above, the width of the radiation-hardened buffer region is between 0.1um and 1um.
[0017] Further, in the CMOS device as described above, the source-drain implant region comprises a first sub-implant region surrounding the source region, a second sub-implant region surrounding the drain region, and a third sub-implant region corresponding to the gate structure; wherein the first sub-implant region and the second sub-implant region are connected through the third sub-implant region.
[0018] The first sub-implant region comprises a first edge along the gate width direction, a second edge along the gate width direction, and a third edge along the gate length direction, and the projection of the first edge and the second edge on the substrate surface extends into the projection of the gate on the substrate surface; and / or
[0019] The second sub-implant region comprises a fourth edge along the gate width direction, a fifth edge along the gate width direction, and a sixth edge along the gate length direction, and the projection of the fourth edge and the fifth edge on the substrate surface extends into the projection of the gate on the substrate surface.
[0020] Further, in the CMOS device described above, the distance d1, at which the orthogonal projection of the first side and the second side on the substrate surface extends into the orthogonal projection of the gate on the substrate surface, satisfies the following condition:
[0021] 10 < d1 < 100 nm.
[0022] Further, in the CMOS device described above, the distance d2, at which the orthogonal projection of the fourth side and the fifth side on the substrate surface extends into the orthogonal projection of the gate on the substrate surface, satisfies the following condition:
[0023] 10 < d2 < 100 nm.
[0024] Further, in the CMOS device described above, the isolation region adopts a dielectric isolation.
[0025] Further, the CMOS device described above further comprises:
[0026] a lightly doped drain region, which is located between the drain region and the channel region.
[0027] In a second aspect, the utility model provides a kind of integrated circuit, comprising at least one CMOS device as described in any of the above.
[0028] The CMOS device and integrated circuit provided by the utility model isolate the source-drain region from the isolation region by setting the anti-radiation reinforcement buffer region around the source-drain region, which changes the main structure of the original CMOS device relatively less and has relatively simple process, and under the premise of ensuring the channel length between the source region and the drain region, even if the total dose irradiation effect causes the silicon surface layer under the well region and the entire isolation region to be inverted, the anti-radiation reinforcement buffer region prevents the formation of a leakage channel between the source region and the drain region, which theoretically completely solves the influence of total dose irradiation on the device and improves the anti-radiation capability. BRIEF DESCRIPTION OF DRAWINGS
[0029] The disclosure of the utility model will become more easily understood with reference to the accompanying drawings. Those skilled in the art will readily understand that these drawings are merely intended to illustrate, and are not intended to limit the scope of protection of the utility model. In addition, similar numbers in the drawings are used to represent similar structures or regions, wherein:
[0030] Figure 1 is a schematic diagram of an NMOS structure in an existing CMOS device;
[0031] Figure 2 is Figure 1 a sectional view along the AA line in
[0032] Figure 3is another schematic diagram of an NMOS structure in a prior CMOS device;
[0033] Figure 4 is another schematic diagram of an NMOS structure in a prior CMOS device;
[0034] Figure 5 is a schematic diagram of an NMOS structure in a CMOS device according to an embodiment of the present application;
[0035] Figure 6 is Figure 5 a cross-sectional view along the BB line. DETAILED DESCRIPTION
[0036] In order to make the above objectives, characteristics and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in a number of ways other than those specifically described herein, and it is to be understood that the present application is not limited to the specific embodiments described below.
[0037] In the description of the present application, the terms "first", "second", and the like are used only for the purpose of description and differentiation, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. In addition, in the present application, unless otherwise explicitly specified and limited, the terms "connected", "connected" and the like should be understood in a broad sense, for example, it can be directly connected, or indirectly connected through an intermediate medium, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0038] Total ionizing dose effect (TID) refers to the cumulative dose absorbed by the sample during irradiation, which is the ionizing radiation effect of the cumulative dose, and is a cumulative effect that causes device failure. The most sensitive area of total dose irradiation effect is the area covered by the isolation region on the substrate surface. For conventional CMOS processes, STI (Shallow Trench Isolation) or LOCOS (Local Oxidation of Silicon) isolation technology is often used due to the need for physical isolation. The area where STI or LOCOS is located is the isolation region in direct contact with the Si substrate, and thus is most sensitive to total dose irradiation. The total dose irradiation effect has a more prominent impact on the NMOS structure in the CMOS device, Figures 1-2 Taking the NMOS structure with LOCOS isolation process as an example, the total dose irradiation effect is described.
[0039] As shown in Figure 1 , a conventional NMOS structure includes an active region 1 and an isolation region 2, wherein the isolation region 2 is implemented by a dielectric isolation. The active region 1 forms the main structure of the device, including an N+ source region 11, an N+ drain region 12, a channel region defined by a gate structure 7, and the N+ source region 11 and the N+ drain region 12 are located on both sides of the channel region. The region outside the active region 1 is the isolation region 2, which is covered with a thick oxide layer on the silicon surface to form a physical isolation region between devices. As known by those skilled in the art, the NMOS device can also include a P-type substrate 3, a P-well region 4, and an N+ source / drain implant region 5'. The P-well region 4 extends from the surface of the P-type substrate 3 into the P-type substrate 3. The N+ source / drain implant region 5' is located in the P-well region 4 and is only used for the implantation of the N+ source region 11 and the N+ drain region 12. Due to the blocking of the thick oxide layer, the N+ source / drain implant cannot actually implant into the substrate 3 below. The P-type can be used as the first doping type and the N-type can be used as the second doping type.
[0040] As shown in Figure 2 , after total dose irradiation, a large number of electron-hole pairs are generated in the thick oxide layer. Due to the light mass of the electrons, they escape from the silicon oxide layer through the surface potential barrier of the SiO2 / Poly gate under the action of the electric field. The holes, due to their heavy mass and high interface potential barrier, cannot cross the SiO2 / Si interface and gradually accumulate at the interface under the action of the electric field, forming a concentrated positive charge. The thicker the oxide layer, the more significant the charge accumulation effect, i.e., the more serious the damage of the irradiation rays to the oxide layer. When the charge accumulates to a certain extent, the positive electric field formed will cause the surface layer of the P-well region 4 near the interface to be inverted, causing a potential leakage channel between the source and the drain (indicated by the arrow), and further leading to device leakage. Figure 2
[0041] Therefore, for NMOS devices, total dose irradiation mainly causes the inversion of the well region 4 at the bottom of the field region due to the accumulation of positive charges, thereby forming a potential leakage channel, and ultimately weakening the isolation effect of the field region.
[0042] In the prior art, there are several ways to improve the total dose irradiation resistance:
[0043] The first way is to make there be no path for the LOCOS connection between the source region and the drain region, which can be achieved by designing a ring gate, a big head gate, and an inverse proportional gate, as shown in Figure 3 . This technical solution can largely solve the problem of total dose irradiation, but because the shape of the gate directly determines the device channel size of the NMOS device, the channel width of the device is significantly changed compared to the conventional NMOS device structure as shown in Figure 1 and Figure 2 , which brings greater constraints to the designers.
[0044] The second method does not change the device structure, but only... Figure 2 The method involves adding an implantation layer to the Si surface layer beneath the field region to increase the concentration of the P-well region 4 at the interface, thereby increasing the electric field strength required for surface inversion and improving the device's resistance to total dose radiation. However, this approach requires additional ion implantation, increasing costs, and it only improves resistance to total dose radiation without fundamentally solving the problem.
[0045] The third method involves forming a P+ type isolation ring 8 in the active region 1 (e.g., ...). Figure 4 As shown), the source / drain region is isolated from the isolation region by a P+ type isolation ring 8, which is similar to adding an "isolation strip" between the source / drain region and the isolation region to prevent leakage current channels from forming between the source and drain due to irradiation through the thick oxide layer. Although this scheme can effectively improve the radiation resistance of the device, it also has obvious shortcomings: (1) The isolation region includes the outer buffer N+ active region 9 and the P+ type isolation ring 8, which occupies a large device area. (2) The P+ type isolation ring 8 directly contacts the N+ source / drain to form a double-sided abrupt PN junction, which has a significant impact on the device's withstand voltage, especially for the drain region 12, which requires high voltage withstand.
[0046] It should be noted that, Figure 4 Due to the presence of the P+ type isolation ring 8, the N+ source-drain injection region 5' is actually the region excluding the P+ type isolation ring 8.
[0047] In summary, existing radiation hardening technologies have significant shortcomings. To address these technical problems, this utility model adopts the following technical solution.
[0048] Figure 5 This is a schematic diagram of the NMOS structure in a CMOS device according to an embodiment of the present invention. Figure 6 yes Figure 5 A cross-sectional view along line BB. (See attached image.) Figures 5-6 As shown, this CMOS device in Figure 1 Based on the CMOS device shown, the mask layout of the N+ source / drain injection region 5' is optimized to obtain the following result: Figure 5The shape of the mask layout of the N+ source-drain implantation region 5 in the embodiment is such that after implantation of the N+ source region 11 and the N+ drain region 12, the N+ source region 11 and the N+ drain region 12 are no longer in direct contact with the isolation region 2, but a P-type ring 6, i.e. a radiation-hardened buffer region 6, is formed between them. The P-type radiation-hardened buffer region 6 surrounds the N+ source region 11 and the N+ drain region 12, and the orthographic projection of the isolation region 2 on the surface of the P-type substrate 3 surrounds the orthographic projection of the radiation-hardened buffer region 6 on the surface of the P-type substrate 3. In this way, when the charge accumulates to a certain extent, the positive electric field formed will cause the surface layer of the P-well region 4 near the interface to be inverted, but due to the presence of the P-type radiation-hardened buffer region 6, a leakage channel cannot be formed between the N+ source region 11 and the N+ drain region 12.
[0049] With reference to the foregoing Figure 1 , Figure 3 and Figure 5 , the gate, source region and drain region of the CMOS device of the embodiment remain substantially unchanged relative to the CMOS device shown in Figure 1 , so the design of the CMOS device does not bring about a major constraint.
[0050] The CMOS device of the embodiment isolates the source-drain region from the isolation region 2 by providing the radiation-hardened buffer region 6 surrounding the source-drain region, and the change to the main structure of the original CMOS device is relatively small and the process is relatively simple. On the premise of ensuring the channel length between the source region and the drain region, even if the total dose irradiation effect causes the surface layer of the well region 4 and the entire isolation region 2 to be inverted, due to the presence of the radiation-hardened buffer region 6, a leakage channel cannot be formed between the source region and the drain region, greatly reducing the impact of total dose irradiation on the device.
[0051] In a specific implementation process, the P-type radiation-hardened buffer region 6 is of a P-doped type, which can make the doping concentration of the radiation-hardened buffer region 6 the same as the doping concentration of the well region 4, so that the P-type radiation-hardened buffer region 6 and the P-well region 4 can be formed using the same process, and Figure 1 compared with the process of the prior art, no additional process is required. That is, after the P-well region 4 is formed, the N+ source-drain implantation region 5 according to the present scheme is used for implantation, and the P-well region 4 between the N+ source region 11 and the N+ drain region 12 and the isolation region 2 serves as the P-type radiation-hardened buffer region 6.
[0052] In a specific implementation process, since the doping concentration of the radiation-hardened buffer region 6 is a light doping concentration, and the doping concentration of the source region and the doping concentration of the drain region are both heavy doping concentrations, this can ensure that the depletion region between the P-type radiation-hardened buffer region 6 and the N+ source region 11 and the N+ drain region 12 is relatively wide, thereby ensuring that the withstand voltage capability of the drain region 12 is not affected by the provision of the radiation-hardened buffer region 6.
[0053] In a specific implementation, the wider the P-irradiation buffer, the better. However, considering the actual chip area limitations, the width of the P-irradiation buffer can be set between 0.1µm and 1µm depending on the different technology nodes.
[0054] See also Figure 4 and Figure 5 The CMOS device in this embodiment and Figure 4 Compared to the CMOS device shown, the parasitic PN junctions in the source and drain regions are changed from double-sided abrupt junctions to single-sided abrupt junctions. The concentration gradient in the P-type region is more gradual, and the breakdown voltage is stronger. This not only enhances the radiation resistance but also reduces the adverse effects on device performance. Furthermore, no additional processing is required, resulting in lower costs.
[0055] In one specific implementation, the CMOS device also includes a lightly doped drain region (LDD) (not shown in the figure). The conventional LDD region covers all active regions of the device, which is called general injection. When such a lightly doped drain region is injected, there is a risk that it may neutralize or even invert the P-buffer in this invention. Therefore, the injection of the lightly doped drain region in this invention is changed from the general injection in the active region of the prior art to injection based on the mask layout of the optimized N+ source-drain injection region 5.
[0056] See also Figure 5 The N+ source / drain injection region 5 includes a first sub-injection region 51 surrounding the N+ source region 11, a second sub-injection region 52 surrounding the N+ drain region 12, and a third sub-injection region 53 corresponding to the gate structure 7; wherein the first sub-injection region 51 and the second sub-injection region 52 are connected through the third sub-injection region 53, so that the N+ source / drain injection region 5 forms a closed region.
[0057] like Figure 5As shown, the first sub-injection region 51 includes a first edge 511 along the gate width direction, a second edge 512 along the gate width direction, and a third edge 513 along the gate length direction, the first edge 511 and the second edge 512 project into the projection of the gate on the substrate 3 surface, wherein the penetration distance d1 satisfies the condition: 10 < d1 < 100 nm; and / or, the second sub-injection region 52 includes a fourth edge 521 along the gate width direction, a fifth edge 522 along the gate width direction, and a sixth edge 523 along the gate length direction, the fourth edge 521 and the fifth edge 522 project into the projection of the gate on the substrate 3 surface, wherein the penetration distance d1 satisfies the condition: 10 < d1 < 100 nm. Such arrangement is to ensure that at least one of the N+ source region 11 and / or the N+ drain region 12 does not directly contact the isolation region 2 even if there is a fluctuation in the lithography alignment of the N+ source / drain injection in mass production, so as to ensure that there is no leakage channel between the N+ source region 11 and the N+ drain region 12.
[0058] In the description of the embodiments, the gate width direction refers to the direction from the source region to the drain region or from the drain region to the source region (corresponding to the horizontal direction in the figure), i.e., the gate width direction is consistent with the channel length direction; the gate width direction is perpendicular to the gate length direction (corresponding to the vertical direction in the figure).
[0059] In a specific implementation process, the CMOS device of the above embodiments can be obtained according to the following preparation process flow:
[0060] S1, forming the active region 1;
[0061] Specifically, a P-type substrate 3 can be provided, and the isolation region and the active region 1 located between the isolation regions can be formed on the P-type substrate 3 by an isolation process.
[0062] S2, forming the P-well region 4;
[0063] Specifically, the P-well region 4 is defined in the active region 1.
[0064] S3, forming the gate oxide;
[0065] S4, forming the polycrystalline gate;
[0066] A thin gate oxide layer is formed on the P-well region 4, and a polycrystalline silicon layer is formed on the thin gate oxide layer to form the polycrystalline gate. The specific formation process can refer to the related art, and will not be described here.
[0067] S5, performing NLDD region injection;
[0068] The mask plate of the NLDD region and the N+ source / drain injection region 5 Figure 1 That is, the NLDD region injection in the present embodiment is different from the general injection in the active region in the prior art.
[0069] S6, forming a side wall;
[0070] The forming process of the side wall can refer to the prior art, and will not be described here.
[0071] S7, performing N+ source region 11 and N+ drain region 12 implantation, and simultaneously forming a P- anti-radiation reinforcement buffer region 6;
[0072] Because the implantation dose of the N+ source region 11 and the N+ drain region 12 is much larger than the P-well region 4, in order to prevent the P-well region 4 from being inverted by the general implantation of the prior art, according to the optimized mask layout of the N+ source and drain implantation region 5 in the prior art, the N+ source region 11 and the N+ drain region 12 are implanted, and the P-well region 4 between the N+ source region 11 and the N+ drain region 12 and the isolation region 2 is taken as the P-anti-radiation reinforcement buffer region 6. Figure 5
[0073] S8, metal silicide process;
[0074] S9, contact hole process;
[0075] S10, metal interconnection process.
[0076] The forming processes of S8 to S10 can refer to the prior art, and will not be described here.
[0077] The technical scheme of the present application has been described in combination with the preferred embodiments shown in the drawings, but it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. Those skilled in the art can make equivalent changes or replacements to the related technical features without deviating from the principles of the present application, and the technical schemes after the changes or replacements will all fall within the protection scope of the present application.
Claims
1. A CMOS device, characterized by, The CMOS device comprises: a substrate; a well region extending from a surface of the substrate into the substrate; a gate structure located on a side of the well region away from the substrate, the gate structure comprising a gate dielectric layer and a gate electrode stacked together; a source-drain implant region located inside the well region, the source-drain implant region comprising a source region and a drain region, a channel region being formed between the source region and the drain region, and the source region and the drain region being located on two sides of the gate structure respectively; a radiation-hardened buffer region located inside the well region and surrounding the source region and the drain region; wherein the substrate, the well region and the radiation-hardened buffer region are of a first doping type, and the source-drain implant region is of a second doping type different from the first doping type; an isolation region located on the surface of the substrate, and a projection of the isolation region on the surface of the substrate surrounding a projection of the radiation-hardened buffer region on the surface of the substrate.
2. The CMOS device of claim 1, wherein: a doping concentration of the radiation-hardened buffer region is the same as a doping concentration of the well region, and the radiation-hardened buffer region and the well region are formed by using a same process.
3. The CMOS device of claim 2, wherein: the doping concentration of the radiation-hardened buffer region and the doping concentration of the well region are both light doping concentrations; the doping concentration of the source region and the doping concentration of the drain region are both heavy doping concentrations.
4. The CMOS device of claim 1, wherein: a width of the radiation-hardened buffer region is between 0.1 um and 1 um.
5. The CMOS device of any one of claims 1 to 4, wherein: the source-drain implant region comprises a first sub-implant region surrounding the source region, a second sub-implant region surrounding the drain region, and a third sub-implant region corresponding to the gate structure; wherein the first sub-implant region and the second sub-implant region are connected through the third sub-implant region; the first sub-implant region comprises a first edge along a gate width direction, a second edge along the gate width direction, and a third edge along a gate length direction, projections of the first edge and the second edge on the surface of the substrate extending into a projection of the gate electrode on the surface of the substrate; and / or the second sub-implant region comprises a fourth edge along the gate width direction, a fifth edge along the gate width direction, and a sixth edge along the gate length direction, projections of the fourth edge and the fifth edge on the surface of the substrate extending into the projection of the gate electrode on the surface of the substrate.
6. The CMOS device of claim 5, wherein: a distance d1 at which the projections of the first edge and the second edge on the surface of the substrate extend into the projection of the gate electrode on the surface of the substrate satisfies the following condition: 10 < d1 < 100 nm.
7. The CMOS device of claim 5, wherein: a distance d2 at which the projections of the fourth edge and the fifth edge on the surface of the substrate extend into the projection of the gate electrode on the surface of the substrate satisfies the following condition: 10 < d2 < 100 nm.
8. The CMOS device of any one of claims 1 to 4, wherein: The isolation region employs dielectric isolation.
9. The CMOS device of any one of claims 1 to 4, wherein, Also included are: A lightly doped drain region between the drain region and the channel region.
10. An integrated circuit, characterized by At least one CMOS device as claimed in any one of claims 1 to 9.