Display device

Abstract

The utility model discloses a display device. The pixel circuits may be symmetrically arranged about boundaries between adjacent pixels. Adjacent pixels may have pixel circuits symmetrical to each other and may share at least one transistor and at least one contact region. Accordingly, a high-resolution display device that can be implemented by improving integration efficiency of a pixel circuit and improving pixel density is provided.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2023-0172734, filed on December 1, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a pixel and a display device including the pixel. Background Technology

[0003] Recently, display devices have been used in a wider variety of ways. In addition, as display devices have become thinner and lighter, their applications have broadened.

[0004] Because display devices can be used in a variety of ways, various methods can be used to design the form of display devices, and the number of functions that can be connected or linked to display devices is constantly increasing. Utility Model Content

[0005] One or more embodiments provide a high-resolution display device. However, such technical problems are examples, and one or more embodiments are not limited thereto.

[0006] Other aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0007] According to one or more embodiments, a display device includes a plurality of pixels, wherein each of the plurality of pixels includes: a first transistor; a second transistor connected to a data line; a third transistor connected to the gate of the first transistor and a second terminal of the first transistor; a fourth transistor connected to the gate of the first transistor and a first initialization voltage line; a fifth transistor connected to the second transistor and a reference voltage line, wherein the fifth transistor includes a first sub-transistor; and a capacitor connected to the gate of the first transistor and the second transistor. The plurality of pixels includes a first pixel and a second pixel adjacent to the first pixel. The fifth transistor included in the first pixel and the fifth transistor included in the second pixel further include a second sub-transistor shared by the first pixel and the second pixel. The second sub-transistor shared by the first pixel and the second pixel is connected in series with the first sub-transistor of the fifth transistor of the first pixel and is closer to the reference voltage line than the first sub-transistor of the fifth transistor of the first pixel. The second sub-transistor shared by the first pixel and the second pixel is connected in series with the first sub-transistor of the fifth transistor of the second pixel and is closer to the reference voltage line than the first sub-transistor of the fifth transistor of the second pixel.

[0008] According to one or more embodiments, the first pixel and the second pixel may share a contact area where the second sub-transistor is connected to the reference voltage line.

[0009] According to one or more embodiments, the second sub-transistor may be arranged at the boundary between the first pixel and the second pixel, wherein the arrangement of transistors of the first pixel other than the second sub-transistor and the arrangement of transistors of the second pixel other than the second sub-transistor may be symmetrical about the boundary between the first pixel and the second pixel.

[0010] According to one or more embodiments, the first pixel and the second pixel may share a sixth transistor connected to the driving voltage line, and the sixth transistor shared by the first pixel and the second pixel may be connected to a first terminal of the first transistor of the first pixel and a first terminal of the first transistor of the second pixel.

[0011] According to one or more embodiments, a sixth transistor shared by a first pixel and a second pixel may be arranged at the boundary between the first pixel and the second pixel, wherein the arrangement of transistors of the first pixel other than the sixth transistor and the arrangement of transistors of the second pixel other than the sixth transistor may be symmetrical about the boundary between the first pixel and the second pixel.

[0012] According to one or more embodiments, the first pixel and the second pixel may share a seventh transistor connected to a bias voltage line, and the seventh transistor shared by the first pixel and the second pixel may be connected to a first terminal of the first transistor of the first pixel and a first terminal of the first transistor of the second pixel.

[0013] According to one or more embodiments, a seventh transistor shared by a first pixel and a second pixel may be arranged at the boundary between the first pixel and the second pixel, wherein the arrangement of transistors of the first pixel other than the seventh transistor and the arrangement of transistors of the second pixel other than the seventh transistor may be symmetrical about the boundary between the first pixel and the second pixel.

[0014] According to one or more embodiments, the fourth transistor may include a first sub-transistor, wherein the plurality of pixels may further include a third pixel adjacent to the second pixel, wherein the fourth transistor included in the second pixel and the fourth transistor included in the third pixel may further include a second sub-transistor shared by the second pixel and the third pixel. The second sub-transistor shared by the second pixel and the third pixel may be connected in series with the first sub-transistor of the fourth transistor of the second pixel, and is closer to the first initialization voltage line than the first sub-transistor of the fourth transistor of the second pixel. The second sub-transistor shared by the second pixel and the third pixel may be connected in series with the first sub-transistor of the fourth transistor of the third pixel, and is closer to the first initialization voltage line than the first sub-transistor of the fourth transistor of the third pixel.

[0015] According to one or more embodiments, the second sub-transistor of the fourth transistor may be arranged at the boundary between the second pixel and the third pixel, wherein the arrangement of transistors of the second pixel other than the second sub-transistor of the fourth transistor and the arrangement of transistors of the third pixel other than the second sub-transistor of the fourth transistor may be symmetrical about the boundary between the second pixel and the third pixel.

[0016] According to one or more embodiments, each of the plurality of pixels may further include: an eighth transistor connected to a second terminal of the first transistor and a light-emitting element; and a ninth transistor connected to the light-emitting element and a second initialization voltage line, wherein the plurality of pixels may further include a third pixel adjacent to the second pixel, and wherein the second pixel and the third pixel may share a contact area where the ninth transistor of the second pixel and the ninth transistor of the third pixel are connected to the second initialization voltage line.

[0017] According to one or more embodiments, a display device includes a plurality of pixels, wherein each of the plurality of pixels includes: a first transistor; a second transistor connected to a data line; a third transistor connected to the gate of the first transistor and a second terminal of the first transistor; a fourth transistor connected to the gate of the first transistor and a first initialization voltage line; a fifth transistor connected to the second transistor and a reference voltage line; and a capacitor connected to the gate of the first transistor and the second transistor. The plurality of pixels includes a first pixel and a second pixel adjacent to the first pixel, wherein the first pixel and the second pixel share a sixth transistor connected to a bias voltage line, and wherein the sixth transistor shared by the first pixel and the second pixel is connected to a first terminal of the first transistor of the first pixel and a first terminal of the first transistor of the second pixel.

[0018] According to one or more embodiments, a sixth transistor shared by a first pixel and a second pixel may be arranged at the boundary between the first pixel and the second pixel, wherein the arrangement of transistors of the first pixel other than the sixth transistor and the arrangement of transistors of the second pixel other than the sixth transistor may be symmetrical about the boundary between the first pixel and the second pixel.

[0019] According to one or more embodiments, a first pixel and a second pixel share a seventh transistor connected to a driving voltage line, wherein the seventh transistor shared by the first pixel and the second pixel can be connected to a first terminal of a first transistor of the first pixel and a first terminal of a first transistor of the second pixel.

[0020] According to one or more embodiments, a seventh transistor shared by a first pixel and a second pixel may be arranged at the boundary between the first pixel and the second pixel, wherein the arrangement of transistors of the first pixel other than the seventh transistor and the arrangement of transistors of the second pixel other than the seventh transistor may be symmetrical about the boundary between the first pixel and the second pixel.

[0021] According to one or more embodiments, the first pixel and the second pixel may share a contact area where the fifth transistor of the first pixel and the fifth transistor of the second pixel are connected to a reference voltage line.

[0022] According to one or more embodiments, the fifth transistor included in the first pixel and the fifth transistor included in the second pixel may each include a first sub-transistor, and the fifth transistor included in the first pixel and the fifth transistor included in the second pixel may further include a second sub-transistor shared by the first pixel and the second pixel. The second sub-transistor shared by the first pixel and the second pixel may be connected in series with the first sub-transistor of the fifth transistor of the first pixel, and is closer to the reference voltage line than the first sub-transistor of the fifth transistor of the first pixel.

[0023] According to one or more embodiments, the first pixel and the second pixel may share a contact area where the second sub-transistor is connected to the reference voltage line.

[0024] According to one or more embodiments, the second sub-transistor may be arranged at the boundary between the first pixel and the second pixel, wherein the arrangement of transistors of the first pixel other than the second sub-transistor and the arrangement of transistors of the second pixel other than the second sub-transistor may be symmetrical about the boundary between the first pixel and the second pixel.

[0025] According to one or more embodiments, the fourth transistor may include a first sub-transistor, wherein the plurality of pixels may further include a third pixel adjacent to the second pixel, wherein the fourth transistor included in the second pixel and the fourth transistor included in the third pixel may further include a second sub-transistor shared by the second pixel and the third pixel. The second sub-transistor shared by the second pixel and the third pixel may be connected in series with the first sub-transistor of the fourth transistor of the second pixel, and is closer to the first initialization voltage line than the first sub-transistor of the fourth transistor of the second pixel. The second sub-transistor shared by the second pixel and the third pixel may be connected in series with the first sub-transistor of the fourth transistor of the third pixel, and is closer to the first initialization voltage line than the first sub-transistor of the fourth transistor of the third pixel.

[0026] According to one or more embodiments, the second sub-transistor of the fourth transistor may be arranged at the boundary between the second pixel and the third pixel, wherein the arrangement of transistors of the second pixel other than the second sub-transistor of the fourth transistor and the arrangement of transistors of the third pixel other than the second sub-transistor of the fourth transistor may be symmetrical about the boundary between the second pixel and the third pixel.

[0027] According to one or more embodiments, each of the plurality of pixels may further include: a seventh transistor connected to a driving voltage line; an eighth transistor connected to a second terminal of the first transistor and a light-emitting element; and a ninth transistor connected to the light-emitting element and a second initialization voltage line, wherein the plurality of pixels may further include a third pixel adjacent to the second pixel, and wherein the second pixel and the third pixel may share a contact area where the ninth transistor of the second pixel and the ninth transistor of the third pixel are connected to the second initialization voltage line. Attached Figure Description

[0028] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1A and Figure 1B This is a schematic diagram of a display device according to an embodiment;

[0030] Figure 2 This is a schematic diagram of a display device according to an embodiment;

[0031] Figures 3 to 5 This is a schematic diagram of pixels according to an embodiment;

[0032] Figure 6A and Figure 6B This is a schematic diagram illustrating the sharing of transistors between adjacent pixels according to an embodiment;

[0033] Figure 7A and Figure 7B This is a schematic diagram illustrating the sharing of transistors between adjacent pixels according to an embodiment;

[0034] Figure 8 This is a schematic diagram illustrating the sharing of transistors between adjacent pixels according to an embodiment;

[0035] Figures 9 to 11 This is a schematic diagram illustrating the sharing of transistors between adjacent pixels according to an embodiment;

[0036] Figure 12 This is a schematic diagram illustrating the positions of the transistors and capacitors of a pixel according to an embodiment;

[0037] Figures 13 to 19 It is a schematic diagram layer by layer. Figure 12 A diagram of the pixel elements;

[0038] Figure 20 It is along Figure 12 The line I-I' intercepted Figure 12 A cross-sectional view of the area;

[0039] Figures 21 to 23 This is a schematic diagram of pixels according to an embodiment; and

[0040] Figure 24 This is a schematic diagram illustrating the sharing of transistors between adjacent pixels according to an embodiment. Detailed Implementation

[0041] Reference will now be made in detail to embodiments illustrated in the accompanying drawings, wherein the same reference numerals denote the same elements throughout. In this respect, the present embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, embodiments are described herein solely by reference to the accompanying drawings to illustrate aspects of the present description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0042] Because this description allows for various modifications and numerous embodiments, specific embodiments will be illustrated in the accompanying drawings and described in the written description. The effects and features of one or more embodiments, and their implementation methods, will become apparent from the following detailed description of one or more embodiments taken in conjunction with the accompanying drawings. However, these embodiments may take different forms and should not be construed as limited to the description set forth herein.

[0043] Although terms such as "first" and "second" can be used to describe various elements, these elements are not necessarily limited to these terms. The terms above are used to distinguish one element from another.

[0044] As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the / that” are intended to include the plural forms as well.

[0045] It will be understood that, as used herein, the terms “comprising,” “including,” and “having” specify the presence of a feature or element of a statement, but do not preclude the addition of one or more other features or elements.

[0046] It will be further understood that when a layer, area, or element is referred to as being on another layer, area, or element, that layer, area, or element may be directly or indirectly on that other layer, area, or element. That is, for example, there may be an intermediate layer, area, or element.

[0047] For ease of illustration, the dimensions of elements in the accompanying drawings may be exaggerated or reduced. For example, since the dimensions and thicknesses of elements in the accompanying drawings are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0048] As used herein, the expression "A and / or B" means A, B, or A and B. In some respects, the expression "at least one of A and B" means A, B, or A and B.

[0049] As used herein, the description of X and Y connections can include cases where X and Y are physically connected, cases where X and Y are functionally connected, and cases where X and Y are electrically connected. In some aspects, the description of X and Y connections can include cases where X and Y are directly connected or cases where X and Y are indirectly connected with another element disposed between them. In this respect, X and Y can include elements (e.g., devices, apparatuses, circuits, wiring, electrodes, terminals, films, layers, or regions, etc.).

[0050] For example, an electrical connection between X and Y can include a direct electrical connection between X and Y and / or an indirect electrical connection between X and Y with another component positioned between them. An indirect electrical connection between X and Y can include at least one device (e.g., a switch, transistor, capacitor, inductor, resistor, or diode, etc.) connected between X and Y to achieve the electrical connection between X and Y. Therefore, the connection is not limited to a predetermined connection relationship, for example, not limited to the connection relationships illustrated in the accompanying drawings or described in the detailed description, and may include other connection relationships not illustrated in the accompanying drawings or described in the detailed description.

[0051] As used herein, the term "on" in association with the state of a device can indicate an active state of the device, and the term "off" can indicate a deactivated state of the device. The term "on" in association with a signal received by the device can indicate a signal that activates the device, and the term "off" can indicate a signal that deactivates the device. A device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the "on" voltages of P-type and N-type transistors are opposite (low to high) voltage levels.

[0052] The x, y, and z directions are not limited to directions along the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0053] Figure 1A and Figure 1B This is a schematic diagram of the display device 10 according to an embodiment. Figure 2 This is a schematic diagram of the display device 10 according to an embodiment.

[0054] refer to Figure 1A and Figure 1B The display device 10 may include a display area DA for displaying an image and a peripheral area PA outside the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0055] In the plan view of the display area DA, the display area DA can have a rectangular shape. In another embodiment, the display area DA can have other polygonal shapes, such as triangles, pentagons, or hexagons, circular shapes, elliptical shapes, or atypical shapes. The corners of the edges of the display area DA can be rounded. In embodiments, such as Figure 1A As shown, the display area DA in the display device 10 can have a length in the x direction greater than the length in the y direction. In another embodiment, as... Figure 1B As shown, the display area DA in the display device 10 can have a length in the y direction that is greater than the length in the x direction. The z direction can be perpendicular to both the x and y directions.

[0056] refer to Figure 2 The display device 10 according to the embodiment may include a pixel region 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19.

[0057] Pixel region 11 can correspond to display region DA. For example... Figure 2As shown, multiple gate lines GL, multiple data lines DL, and multiple pixels PX connected to these lines can be arranged in pixel region 11. The multiple pixels PX can be arranged, for example, in stripes, Various arrangements, such as rhomboid, mosaic, and pixel arrangements, are used to display images. Each pixel PX may include an organic light-emitting diode (OLED) as a display element (light-emitting element), and the OLED may be connected to the pixel circuitry. Pixel PX may emit light, such as red, green, blue, or white light, through the OLED. Each pixel PX may be connected to at least one corresponding gate line GL and at least one corresponding data line DL among multiple gate lines GL and multiple data lines DL.

[0058] A pixel circuit may include a plurality of transistors and at least one capacitor. In one embodiment, the plurality of transistors included in the pixel circuit may be P-type silicon thin-film transistors. In another embodiment, the plurality of transistors included in the pixel circuit may be N-type oxide thin-film transistors. In yet another embodiment, some of the transistors included in the pixel circuit may be N-type oxide thin-film transistors, and some of the transistors included in the pixel circuit may be P-type silicon thin-film transistors.

[0059] A silicon thin-film transistor can be a thin-film transistor in which the semiconductor layer includes amorphous silicon or polycrystalline silicon (e.g., low-temperature polycrystalline silicon (LTPS)). An oxide thin-film transistor can be a low-temperature polycrystalline oxide (LTPO) thin-film transistor in which the semiconductor layer includes oxide. However, this is just an example, and N-type transistors are not limited thereto. For example, the semiconductor layer included in an N-type transistor can include inorganic semiconductors (e.g., amorphous silicon, polycrystalline silicon) or organic semiconductors.

[0060] Each of the gate lines GL can extend in the x-direction (row direction) and can connect to a pixel PX located in the same row. The gate line GL can be configured to transmit a gate signal to the pixel PX in the same row. Each of the data lines DL can extend in the y-direction (column direction) and can connect to a pixel PX located in the same column. Each data line DL can be configured to transmit a data signal synchronously with the gate signal to each of the pixels PX in the same column.

[0061] In an embodiment, the peripheral region PA may be a non-display area in which no pixels PX are disposed. Various conductive lines may be present in the peripheral region PA and may be configured to transmit electrical signals to be applied to the pixel region 11, external circuitry electrically connected to the pixel circuitry, and pads on which a printed circuit board or driver integrated circuit (IC) chip is attached. For example, gate drive circuitry 13, data drive circuitry 15, power supply circuitry 17, and controller 19 may be provided in the peripheral region PA.

[0062] The gate drive circuit 13 can be connected to multiple gate lines GL and can be configured to generate a gate signal GS in response to a drive control signal GCS from the controller 19 and sequentially supply the gate signal GS to the gate lines GL. The gate lines GL can be connected to the gates of transistors included in the pixel PX. The gate signal GS can be a gate control signal used to control the on and off states of transistors whose gates are connected to the gate lines GL. The gate signal GS can be a square wave signal including a gate on voltage that can turn on the transistors and a gate off voltage that can turn off the transistors. In an embodiment, the gate on voltage can be a high-level voltage or a low-level voltage.

[0063] although Figure 2 The figure shows a pixel PX connected to a gate line GL, but this is an example, and the pixel PX can be connected to two or more gate lines, and the gate drive circuit 13 can be configured to supply two or more gate signals to the corresponding gate lines, and the timing of the application of the gate turn-on voltage of the two or more gate signals can be different from each other.

[0064] The data driving circuit 15 can be connected to multiple data lines DL and can be configured to supply data signals DATA to the data lines DL in response to a drive control signal DCS from the controller 19. The data signals DATA supplied to the data lines DL can be supplied to pixels PX that are supplied with gate signals GS. The data driving circuit 15 can be configured to convert grayscale input image data from the controller 19 into data signals DATA in the form of voltage or current.

[0065] The power supply circuit 17 can be configured to generate a voltage associated with the driving pixel PX in response to a drive control signal PCS from the controller 19. The power supply circuit 17 can be configured to generate a drive voltage ELVDD and a common voltage ELVSS, and supply them to the pixel PX. The drive voltage ELVDD can be a high-level voltage supplied to a terminal of a driving transistor connected to a first electrode (pixel electrode or anode) of the display element included in the pixel PX. The common voltage ELVSS can be a low-level voltage supplied to a second electrode (counter electrode or cathode) of the display element included in the pixel PX.

[0066] The controller 19 can generate drive control signals GCS, DCS, and PCS based on signals input from an external source, and can supply them to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17, respectively. The drive control signal GCS output to the gate drive circuit 13 may include multiple clock signals and a gate start signal. The drive control signal DCS output to the data drive circuit 15 may include multiple clock signals and a data start signal.

[0067] The display device 10 may include a display panel, and the display panel may include a substrate. Pixels PX may be arranged in the display area DA (pixel area 11) of the substrate. During the process of forming transistors constituting pixel circuits in the display area DA of the substrate, a portion or the entire gate driving circuit 13 may be directly formed in the peripheral area PA of the substrate. The data driving circuit 15, the power supply circuit 17, and the controller 19 may each be formed as separate IC chips or may be formed together as a single IC chip, and may be disposed on a flexible printed circuit board (FPCB) electrically connected to pads disposed on one side of the substrate. In another embodiment, the data driving circuit 15, the power supply circuit 17, and the controller 19 may be directly disposed on the substrate in a chip-on-glass (COG) or chip-on-plastic (COP) manner.

[0068] Figures 3 to 5 This is a schematic diagram of pixel PXa according to an embodiment.

[0069] refer to Figure 3 Pixel PXa may include pixel circuit PC and organic light-emitting diode (OLED) connected to pixel circuit PC as a display element.

[0070] The pixel circuit PC of pixel PXa may include first transistors T1 to ninth transistors T9, first capacitor C1 and second capacitor C2, and the pixel circuit PC may be connected to multiple signal lines. The signal lines may include data line DL, first gate line GWL, second gate line GIL, third gate line GCL, fourth gate line EML1, fifth gate line EML2, sixth gate line EBL, drive voltage line PL, reference voltage line VRL, first initialization voltage line VIL1, second initialization voltage line VIL2 and bias voltage line VBL.

[0071] The first transistor T1 can be a driving transistor in which the magnitude of the source-drain current is determined by the gate-source voltage (Vgs), and the second transistor T2 through the ninth transistor T9 can be switching transistors that transmit signals by being turned on / off according to the gate voltage. The first transistor T1 through the ninth transistor T9 can be implemented using thin-film transistors. Depending on the transistor type (P-type or N-type) and / or operating conditions of each of the first transistors T1 through the ninth transistor T9, the first terminal can be either the source or the drain, and the second terminal can be a terminal different from the first terminal. In an example where the first terminal is the source, the second terminal can be the drain.

[0072] In the example, the first transistor T1 to the ninth transistor T9 can be P-type silicon thin film transistors. The gate turn-on voltage for turning on the gate signals of the first transistor T1 to the ninth transistor T9 can be a low-level voltage, and the gate turn-off voltage for turning off the gate signals of the first transistor T1 to the ninth transistor T9 can be a high-level voltage.

[0073] A first transistor T1 can be connected between the driving voltage line PL and the organic light-emitting diode (OLED). The first transistor T1 can be connected to the driving voltage line PL via a ninth transistor T9, and can be connected to the OLED via a sixth transistor T6. The first transistor T1 may include a gate connected to a first node N1, a first terminal connected to a second node N2, and a second terminal connected to a third node N3. The first transistor T1 can be configured to receive a data signal DATA according to the switching operation of the second transistor T2 and to supply driving current to the OLED.

[0074] A second transistor T2 can be connected between data line DL and the first node N1. A second transistor T2 can also be connected between data line DL and the fourth node N4. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the fourth node N4. The second transistor T2 can be turned on according to a first gate signal GW received through the first gate line GWL to perform a switching operation for transmitting the data signal DATA transmitted to the data line DL to the fourth node N4.

[0075] A third transistor T3 can be connected between a third node N3 and a first node N1. The third transistor T3 can be connected to an organic light-emitting diode (OLED) via a sixth transistor T6. The third transistor T3 may include a gate connected to a third gate line GCL, a first terminal connected to the third node N3, and a second terminal connected to the first node N1. The third transistor T3 can be turned on according to a third gate signal GC received through the third gate line GCL to diode-connect the first transistor T1 and compensate for the threshold voltage of the first transistor T1. In an embodiment, as... Figure 4 and Figure 5 As shown, the third transistor T3 can be a dual-gate transistor in which a pair of sub-transistors (e.g., the first sub-transistor T3-1 and the second sub-transistor T3-2) are connected in series. The gates of the first sub-transistor T3-1 and the second sub-transistor T3-2 can be connected to the third gate line GCL.

[0076] A fourth transistor T4 can be connected between the first node N1 and the first initialization voltage line VIL1. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the first node N1, and a second terminal connected to the first initialization voltage line VIL1. The fourth transistor T4 can be turned on according to the second gate signal GI received through the second gate line GIL to initialize the gate of the first transistor T1 with the first initialization voltage VINT. In an embodiment, as... Figure 4 and Figure 5 As shown, the fourth transistor T4 can be a dual-gate transistor in which a pair of sub-transistors (e.g., the first sub-transistor T4-1 and the second sub-transistor T4-2) are connected in series. The gates of the first sub-transistor T4-1 and the second sub-transistor T4-2 can be connected to the second gate line GIL.

[0077] A fifth transistor T5 can be connected between the fourth node N4 and the reference voltage line VRL. The fifth transistor T5 may include a gate connected to the third gate line GCL, a first terminal connected to the reference voltage line VRL, and a second terminal connected to the fourth node N4. The fifth transistor T5 can be turned on according to the third gate signal GC received through the third gate line GCL to transmit the reference voltage VREF to the fourth node N4. In an embodiment, as... Figure 5 As shown, the fifth transistor T5 can be a dual-gate transistor in which a pair of sub-transistors (e.g., the first sub-transistor T5-1 and the second sub-transistor T5-2) are connected in series. The gates of the first sub-transistor T5-1 and the second sub-transistor T5-2 can be connected to a third gate line GCL.

[0078] The sixth transistor T6 can be connected between the third node N3 and the organic light-emitting diode (OLED). The sixth transistor T6 may include a gate connected to the fifth gate line EML2, a first terminal connected to the third node N3, and a second terminal connected to the pixel electrode of the OLED. The sixth transistor T6 can be turned on according to the fifth gate signal EM2 received through the fifth gate line EML2.

[0079] A seventh transistor T7 can be connected between the organic light-emitting diode (OLED) and the second initialization voltage line VIL2. The seventh transistor T7 may include a gate connected to the sixth gate line EBL, a first terminal connected to the second terminal of the sixth transistor T6 and the pixel electrode of the OLED, and a second terminal connected to the second initialization voltage line VIL2. The seventh transistor T7 can be turned on according to the sixth gate signal EB received through the sixth gate line EBL to transmit the second initialization voltage VAINT to the pixel electrode of the OLED and initialize the pixel electrode of the OLED.

[0080] An eighth transistor T8 can be connected between the second node N2 and the bias voltage line VBL. The eighth transistor T8 may include a gate connected to the sixth gate line EBL, a first terminal connected to the bias voltage line VBL, and a second terminal connected to the second node N2. The eighth transistor T8 can be turned on according to the sixth gate signal EB received through the sixth gate line EBL to transmit the bias voltage VBIAS to the first terminal of the first transistor T1 and control the gate-source voltage (Vgs) of the first transistor T1. By controlling the gate-source voltage (Vgs) of the first transistor T1, the threshold voltage of the first transistor T1 can be changed. Accordingly, the change in voltage-current characteristics due to the hysteresis characteristics of the first transistor T1 can be compensated.

[0081] A ninth transistor T9 can be connected between the drive voltage line PL and the second node N2. The ninth transistor T9 may include a gate connected to the fourth gate line EML1, a first terminal connected to the drive voltage line PL, and a second terminal connected to the second node N2. The ninth transistor T9 can be turned on according to a fourth gate signal EM1 received through the fourth gate line EML1. In an example where both the sixth transistor T6 and the ninth transistor T9 are active (e.g., simultaneously turned on), a current path can be formed from the drive voltage line PL to the organic light-emitting diode (OLED). The first transistor T1 can be configured to output a drive current corresponding to the data signal DATA stored in the first capacitor C1.

[0082] The first capacitor C1 can be connected between the first node N1 and the fourth node N4. The first capacitor C1 can be charged with a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal DATA. The second capacitor C2 can be connected between the drive voltage line PL and the fourth node N4.

[0083] An organic light-emitting diode (OLED) may include a pixel electrode (e.g., an anode) and a counter electrode (e.g., a cathode) facing the pixel electrode, and the counter electrode may receive a common voltage ELVSS. The OLED may receive a drive current corresponding to a data signal DATA from a first transistor T1 and emit light of a specific color to display an image.

[0084] According to the embodiment, at least one of the third transistor T3, the fourth transistor T4 and the fifth transistor T5 can be a dual-gate transistor, and therefore leakage current can be prevented by reducing the cutoff current during the cutoff period, which can support the stable holding of the data signal in the first capacitor C1.

[0085] According to an embodiment, neighboring pixels may share one of the sub-transistors of at least one of the fourth transistor T4 and the fifth transistor T5, which can support efficient use of the space for arranging pixel circuitry and thus achieve a high-resolution display device. For example, neighboring pixels may share a sub-transistor of at least one of the fourth transistor T4 and the fifth transistor T5 that is relatively close to the power supply.

[0086] In one embodiment, two adjacent pixels may share the second sub-transistor T4-2 of the fourth transistor T4, and therefore may share the contact area that connects the second sub-transistor T4-2 to the first initialization voltage line VIL1, which will be referred to at least later. Figure 6A Describe an example. In other words, the respective fourth transistor T4 of neighboring pixels can share the second sub-transistor T4-2.

[0087] In one embodiment, two adjacent pixels may share the second sub-transistor T5-2 of the fifth transistor T5, and therefore may share the contact area that connects the second sub-transistor T5-2 to the reference voltage line VRL, which will be discussed later at least. Figure 8 Describe an example. In other words, the respective fifth transistor T5 of neighboring pixels can share the second sub-transistor T5-2.

[0088] According to an embodiment, neighboring pixels can share at least one transistor constituting the pixel circuit (e.g., at least one of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9), thereby effectively utilizing the space for arranging the pixel circuit and thus realizing a high-resolution display device, as at least referred to herein. Figure 7A and Figure 8 Describe its examples.

[0089] In one embodiment, two adjacent pixels may share a seventh transistor T7, and therefore may share the contact area connecting the seventh transistor T7 to the second initialization voltage line VIL2. In another embodiment, two adjacent pixels may share an eighth transistor T8, and therefore may share the contact area connecting the eighth transistor T8 to the bias voltage line VBL. In yet another embodiment, two adjacent pixels may share a ninth transistor T9, and therefore may share the contact area connecting the ninth transistor T9 to the drive voltage line PL.

[0090] According to an embodiment, neighboring pixels can share a contact area that connects at least one transistor constituting a pixel circuit to a voltage line, thereby making efficient use of the space where the pixel circuit is arranged and thus realizing a high-resolution display device.

[0091] In one embodiment, two adjacent pixels may each include a seventh transistor T7 and may share a contact area connecting the seventh transistor T7 to the second initialization voltage line VIL2. In another embodiment, two adjacent pixels may each include an eighth transistor T8 and may share a contact area connecting the eighth transistor T8 to the bias voltage line VBL. In yet another embodiment, two adjacent pixels may each include a ninth transistor T9 and may share a contact area connecting the ninth transistor T9 to the drive voltage line PL.

[0092] Figure 6A and Figure 6B This is a schematic diagram illustrating the sharing of transistors between adjacent pixels according to an embodiment. Figure 6A and Figure 6B This is a schematic diagram illustrating the sharing of a fourth transistor between adjacent pixels. Figure 6A It is a diagram. Figure 4 The image shown in the middle is a graph of pixels. Figure 6B It is a schematic diagram. Figure 4 The diagram shows the transistors in the pixels.

[0093] refer to Figure 6A Left pixel PXL and right pixel PXR, which are adjacent to each other in the x-direction (row direction), can share the second sub-transistor T4-2 of the fourth transistor T4. In other words, the respective fourth transistor T4 of the left pixel PXL and right pixel PXR can share the second sub-transistor T4-2.

[0094] The second sub-transistor T4-2 of the fourth transistor T4 can be arranged between the left pixel PXL and the right pixel PXR, for example, in the boundary region between the left pixel PXL and the right pixel PXR. The second sub-transistor T4-2 can be connected between the first sub-transistor T4-1 of the left pixel PXL and the first initialization voltage line VIL1, and can also be connected between the first sub-transistor T4-1 of the right pixel PXR and the first initialization voltage line VIL1. The second sub-transistor T4-2 can be closer to the first initialization voltage line VIL1 than the first sub-transistor T4-1 of the left pixel PXL.

[0095] Regarding the boundary between the left pixel PXL and the right pixel PXR, the first transistor T1 to the ninth transistor T9 of the left pixel PXL, as well as the first capacitor C1 and the second capacitor C2, can be arranged symmetrically with the first transistor T1 to the ninth transistor T9 of the right pixel PXR, as well as the first capacitor C1 and the second capacitor C2.

[0096] The first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EML1, the fifth gate line EML2, the sixth gate line EBL, the reference voltage line VRL, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and the bias voltage line VBL can each extend in the x-direction, and the data line DL can extend in the y-direction. The drive voltage line PL can include a first drive voltage line PLh extending in the x-direction and / or a second drive voltage line PLv extending in the y-direction. In an embodiment, the first drive voltage line PLh and the second drive voltage line PLv can be connected to each other, and therefore, the drive voltage line PL can have a mesh structure.

[0097] The second sub-transistor T4-2 of the fourth transistor T4 can be connected to the first initialization voltage line VIL1 in the contact area CNT_VIL1. The left pixel PXL and the right pixel PXR can share the second sub-transistor T4-2 and can share the contact area CNT_VIL1 that connects the second sub-transistor T4-2 to the first initialization voltage line VIL1.

[0098] Left pixel PXL and right pixel PXR may each include a seventh transistor T7, and the seventh transistor T7 of left pixel PXL and right pixel PXR may be connected to the second initialization voltage line VIL2 in the contact area CNT_VIL2. Left pixel PXL and right pixel PXR may share the contact area CNT_VIL2 where the seventh transistor T7 of left pixel PXL and right pixel PXR are connected to the second initialization voltage line VIL2.

[0099] refer to Figure 6B Each of the first transistor T1 to the ninth transistor T9 may include a semiconductor layer and a gate electrode (gate) overlapping the semiconductor layer. The semiconductor layer may include a source region, a drain region, and a channel region between the source and drain regions, and the gate electrode may overlap the channel region. In some cases, the source region or drain region may be interpreted as the source electrode (source) or drain electrode (drain) of the transistor.

[0100] Each of the left pixel PXL and the right pixel PXR may include a first semiconductor layer ACT1, a second semiconductor layer ACT2, and a third semiconductor layer ACT3.

[0101] The first semiconductor layer ACT1 may include semiconductor layers of a first transistor T1, a third transistor T3, a fourth transistor T4, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. In each of the left pixel PXL and the right pixel PXR, the first semiconductor layer ACT1 of the left pixel PXL and the first semiconductor layer ACT1 of the right pixel PXR may be integrally formed and connected to each other.

[0102] The second gate line GIL, the third gate line GCL, the fourth gate line EML1, the fifth gate line EML2, and the sixth gate line EBL can each extend in the x-direction and be disposed above the first semiconductor layer ACT1, the second semiconductor layer ACT2, and the third semiconductor layer ACT3.

[0103] The first semiconductor layer ACT1 may include the source region S1 and drain region D1 of the first transistor T1, the source regions S31 and S32 and drain regions D31 and D32 of the third transistor T3, the source regions S41 and S42 and drain regions D41 and D42 of the fourth transistor T4, the source region S6 and drain region D6 of the sixth transistor T6, the source region S7 and drain region D7 of the seventh transistor T7, the source region S8 and drain region D8 of the eighth transistor T8, and the source region S9 and drain region D9 of the ninth transistor T9. The second semiconductor layer ACT2 may include the source region S2 and drain region D2 of the second transistor T2. The third semiconductor layer ACT3 may include the source region S5 and drain region D5 of the fifth transistor T5.

[0104] The gate electrodes G1 to G9 of the first transistor T1 to the ninth transistor T9 can be disposed above the first semiconductor layer ACT1, the second semiconductor layer ACT2 and the third semiconductor layer ACT3.

[0105] The gate electrode G1 of the first transistor T1 can be island-shaped. The gate electrode G2 of the second transistor T2 can be island-shaped. The gate electrodes G31 and G32 of the third transistor T3 can be part of the third gate line GCL and can be disposed on the same layer. The gate electrodes G41 and G42 of the fourth transistor T4 can be part of the second gate line GIL and can be disposed on the same layer. The gate electrode G5 of the fifth transistor T5 can be part of the third gate line GCL. The gate electrode G6 of the sixth transistor T6 can be part of the fifth gate line EML2. The gate electrode G7 of the seventh transistor T7 can be part of the sixth gate line EBL. The gate electrode G8 of the eighth transistor T8 can be part of the sixth gate line EBL. The gate electrode G9 of the ninth transistor T9 can be part of the fourth gate line EML1.

[0106] The drain region D42 of the second sub-transistor T4-2 of the fourth transistor T4 can be connected to the first initialization voltage line VIL1, which will later be positioned above the drain region D42, through a contact hole in the contact area CNT_VIL1. The left pixel PXL and the right pixel PXR can share the second sub-transistor T4-2 and can share the contact area CNT_VIL1 that connects the second sub-transistor T4-2 to the first initialization voltage line VIL1.

[0107] The left pixel PXL and the right pixel PXR may each include a seventh transistor T7, and the drain region D7 of the seventh transistor T7 of the left pixel PXL and the drain region D7 of the seventh transistor T7 of the right pixel PXR may be integrally formed and connected to each other. The left pixel PXL and the right pixel PXR may share the contact area CNT_VIL2 that connects the seventh transistor T7 to the second initialization voltage line VIL2. The drain region D7 of the seventh transistor T7 of the left pixel PXL and the drain region D7 of the seventh transistor T7 of the right pixel PXR may be connected to the second initialization voltage line VIL2, which will be later disposed above the drain region D7, through contact holes in the contact area CNT_VIL2.

[0108] In an embodiment, a shielding layer SHL may be provided covering the semiconductor region (e.g., the semiconductor region between two channel regions) between the gate electrodes G31 and G32 of the third transistor T3 and the semiconductor region (e.g., the semiconductor region between two channel regions) between the gate electrodes G41 and G42 of the fourth transistor T4.

[0109] Figure 7A and Figure 7B This is a schematic diagram illustrating the sharing of transistors between adjacent pixels according to an embodiment.

[0110] Figure 7A and Figure 7B This is a schematic diagram illustrating the sharing of the eighth and ninth transistors between adjacent pixels.

[0111] Figure 7A It is a diagram. Figure 4 The image shown in the middle is a graph of pixels. Figure 7B It is a schematic diagram. Figure 4 The diagram shows the transistors in the pixels.

[0112] refer to Figure 7A Left pixel PXL and right pixel PXR that are adjacent to each other in the x-direction (row direction) can share the eighth transistor T8 and the ninth transistor T9.

[0113] The eighth transistor T8 and the ninth transistor T9 can be arranged between the left pixel PXL and the right pixel PXR, for example, in the boundary region between the left pixel PXL and the right pixel PXR. The left pixel PXL and the right pixel PXR can share the contact area CNT_VBL where the eighth transistor T8 is connected to the bias voltage line VBL. The left pixel PXL and the right pixel PXR can share the contact area CNT_PL where the ninth transistor T9 is connected to the drive voltage line PL.

[0114] Regarding the boundary between the left pixel PXL and the right pixel PXR, the first transistors T1 to T7 and the first capacitor C1 and the second capacitor C2 of the left pixel PXL can be arranged symmetrically with those of the right pixel PXR. The left pixel PXL and the right pixel PXR can each include a fourth transistor T4, and the fourth transistor T4 can include a first sub-transistor T4-1 and a second sub-transistor T4-2.

[0115] The first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EML1, the fifth gate line EML2, the sixth gate line EBL, the drive voltage line PL, the reference voltage line VRL, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and the bias voltage line VBL can each extend in the x-direction, and the data line DL can extend in the y-direction. Figure 7A In one embodiment, the driving voltage line PL extends in the x-direction, but in another embodiment, such as... Figure 6A As shown, the driving voltage line PL may further include a second driving voltage line PLv that extends in the y direction and is connected to the driving voltage line PL.

[0116] The left pixel PXL and the right pixel PXR can share the fifth transistor T5 of the left pixel PXL and the fifth transistor T5 of the right pixel PXR, which are connected to the contact area CNT_VRL of the reference voltage line VRL.

[0117] refer to Figure 7B Each of the first transistor T1 to the ninth transistor T9 may include a semiconductor layer and a gate electrode (gate) overlapping the semiconductor layer. This section primarily describes... Figure 6B The differences.

[0118] The source region S8 of the eighth transistor T8 can be connected to the bias voltage line VBL, which will be set above the source region S8 later, through a contact hole in the contact area CNT_VBL. The source region S9 of the ninth transistor T9 can be connected to the drive voltage line PL, which will be set above the source region S9 later, through a contact hole in the contact area CNT_PL.

[0119] Left pixel PXL and right pixel PXR can share the semiconductor layer of the eighth transistor T8 and the semiconductor layer of the ninth transistor T9. Left pixel PXL and right pixel PXR can share the contact area CNT_VBL that connects the eighth transistor T8 to the bias voltage line VBL. Left pixel PXL and right pixel PXR can share the contact area CNT_PL that connects the ninth transistor T9 to the drive voltage line PL.

[0120] Left pixel PXL and right pixel PXR may each include a fifth transistor T5, and the source region S5 of the fifth transistor T5 of the left pixel PXL and the source region S5 of the fifth transistor T5 of the right pixel PXR may be integrally formed and connected to each other. Left pixel PXL and right pixel PXR may share a contact area CNT_VRL that connects the fifth transistor T5 to the reference voltage line VRL. The source region S5 of the fifth transistor T5 of the left pixel PXL and the source region S5 of the fifth transistor T5 of the right pixel PXR may be connected to the reference voltage line VRL, which will later be positioned above the source region S5, through contact holes in the contact area CNT_VRL.

[0121] In an embodiment, a shielding layer SHL may be provided covering the semiconductor region (e.g., the semiconductor region between two channel regions) between the gate electrodes G31 and G32 of the third transistor T3 and the semiconductor region (e.g., the semiconductor region between two channel regions) between the gate electrodes G41 and G42 of the fourth transistor T4.

[0122] Figure 8 This is a schematic diagram illustrating the sharing of transistors between adjacent pixels according to an embodiment. Figure 8 It is a schematic diagram illustrating the sharing of the sub-transistors of the fifth transistor, the sharing of the eighth transistor, and the sharing of the ninth transistor between adjacent pixels.

[0123] refer to Figure 8 In the x-direction (row direction), adjacent left pixels PXL and right pixels PXR can share the eighth transistor T8 and the ninth transistor T9. In some aspects, left pixels PXL and right pixels PXR can share the second sub-transistor T5-2 of the fifth transistor T5. In other words, the respective fifth transistor T5 of left pixels PXL and right pixels PXR can share the second sub-transistor T5-2. The sharing of the eighth transistor T8 and the ninth transistor T9 is referenced. Figure 7A The descriptions are identical, and therefore their detailed descriptions are omitted.

[0124] Regarding the boundary between the left pixel PXL and the right pixel PXR, the first transistor T1 to the seventh transistor T7 (e.g., excluding the second sub-transistor T5-2) and the first capacitor C1 and the second capacitor C2 of the left pixel PXL can be arranged symmetrically with each other as well as the first transistor T1 to the seventh transistor T7 (e.g., excluding the second sub-transistor T5-2) and the first capacitor C1 and the second capacitor C2 of the right pixel PXR.

[0125] The fifth transistor T5 may include a first sub-transistor T5-1 and a second sub-transistor T5-2, and the left pixel PXL and the right pixel PXR may share the second sub-transistor T5-2 of the fifth transistor T5. In other words, the fifth transistor T5 of the left pixel PXL and the fifth transistor T5 of the right pixel PXR may share the second sub-transistor T5-2.

[0126] The second sub-transistor T5-2 of the fifth transistor T5 can be arranged between the left pixel PXL and the right pixel PXR, for example, in the boundary region between the left pixel PXL and the right pixel PXR. The second sub-transistor T5-2 can be connected between the first sub-transistor T5-1 of the left pixel PXL and the reference voltage line VRL, and can also be connected between the first sub-transistor T5-1 of the right pixel PXR and the reference voltage line VRL. The second sub-transistor T5-2 of the fifth transistor T5 can be connected to the reference voltage line VRL in the contact region CNT_VRL. The left pixel PXL and the right pixel PXR can share the second sub-transistor T5-2 and can share the contact region CNT_VRL that connects the second sub-transistor T5-2 to the reference voltage line VRL. The second sub-transistor T5-2 can be closer to the reference voltage line VRL than the first sub-transistor T5-1 of the left pixel PXL. The second sub-transistor T5-2 can be closer to the reference voltage line VRL than the first sub-transistor T5-1 of the right pixel PXR.

[0127] Figures 9 to 11 This is a schematic diagram illustrating the sharing of transistors between adjacent pixels according to an embodiment. Focusing on... Figure 9 Description of differences Figure 10 and Figure 11 .

[0128] refer to Figure 9 In this unit pixel arrangement, first pixels PX1, second pixels PX2, and third pixels PX3 that are adjacent to each other in the x-direction can constitute a single unit pixel, and these unit pixels can be repeatedly arranged in the x-direction within the display area. Each of the three unit pixels, PX1, PX2, and PX3, can be a sub-pixel that emits a different color of light. In this embodiment, first pixel PX1 can be a red pixel, second pixel PX2 can be a green pixel, and third pixel PX3 can be a blue pixel.

[0129] In an embodiment, such as Figure 9 As shown, a pair of adjacent pixels in the x-direction (e.g., first pixel PX1 and second pixel PX2, second pixel PX2 and third pixel PX3, and third pixel PX3 and first pixel PX1 (first pixel PX1 is arranged to the right of third pixel PX3)) can share at least one transistor and at least one contact area.

[0130] Regarding the boundary between the first pixel PX1 and the second pixel PX2, the first transistors T1 to T9, the first capacitor C1, and the second capacitor C2 of the first pixel PX1 can be arranged symmetrically with each other as well as the first transistors T1 to T9, the first capacitor C1, and the second capacitor C2 of the second pixel PX2. Similarly, regarding the boundary between the second pixel PX2 and the third pixel PX3, the first transistors T1 to T9, the first capacitor C1, and the second capacitor C2 of the second pixel PX2 can be arranged symmetrically with each other as well as the first transistors T1 to T9, the first capacitor C1, and the second capacitor C2 of the third pixel PX3. Likewise, regarding the boundary between the third pixel PX3 and the first pixel PX1, the first transistors T1 to T9, the first capacitor C1, and the second capacitor C2 of the third pixel PX3 can be arranged symmetrically with each other as well as the first transistors T1 to T9, the first capacitor C1, and the second capacitor C2 of the first pixel PX1.

[0131] In an embodiment, such as Figures 9 to 11 As shown, the first pixel PX1 and the second pixel PX2 can share the eighth transistor T8, and can also share the contact area CNT_VBL that connects the eighth transistor T8 to the bias voltage line VBL.

[0132] In an embodiment, such as Figure 9 As shown, the first pixel PX1 and the second pixel PX2 can share the contact area CNT_VRL that connects the fifth transistor T5 to the reference voltage line VRL.

[0133] In an embodiment, such as Figure 10 and Figure 11 As shown, the fifth transistor T5 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first sub-transistor T5-1 and a second sub-transistor T5-2. The first pixel PX1 and the second pixel PX2 may share the second sub-transistor T5-2 of the fifth transistor T5. For example, the fifth transistor T5 of the first pixel PX1 and the fifth transistor T5 of the second pixel PX2 may share the second sub-transistor T5-2. The first pixel PX1 and the second pixel PX2 may share the contact area CNT_VRL where the second sub-transistor T5-2, shared by the fifth transistor T5 of the first pixel PX1 and the fifth transistor T5 of the second pixel PX2, is connected to the reference voltage line VRL.

[0134] Similarly, for example, the fifth transistor T5 of the third pixel PX3 and the fifth transistor T5 of another first pixel PX1 (not shown) adjacent to the third pixel PX3 can share a second sub-transistor T5-2. The third pixel PX3 and the other first pixel PX1 can share the contact area CNT_VRL (not shown) where the second sub-transistor T5-2, shared by the fifth transistor T5 of the third pixel PX3 and the fifth transistor T5 of the other first pixel PX1, is connected to the reference voltage line VRL.

[0135] In an embodiment, such as Figure 11 As shown, the first pixel PX1 and the second pixel PX2 can further share the ninth transistor T9. The first pixel PX1 and the second pixel PX2 can further share the contact area CNT_PL that connects the ninth transistor T9 to the drive voltage line PL.

[0136] In an embodiment, such as Figures 9 to 11 As shown, the fourth transistor T4 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first sub-transistor T4-1 and a second sub-transistor T4-2. For example, the fourth transistor T4 of the first pixel PX1 and the fourth transistor T4 of the second pixel PX2 may share the second sub-transistor T4-2 and may share the contact area CNT_VIL1 that connects the second sub-transistor T4-2 to the first initialization voltage line VIL1. The second pixel PX2 and the third pixel PX3 may share the second sub-transistor T4-2 of the fourth transistor T4 and may share the contact area CNT_VIL1 that connects the second sub-transistor T4-2 to the first initialization voltage line VIL1. In other words, the fourth transistor T4 of the second pixel PX2 and the fourth transistor T4 of the third pixel PX3 may share the second sub-transistor T4-2 and may share the contact area CNT_VIL1 that connects the second sub-transistor T4-2 to the first initialization voltage line VIL1.

[0137] In an embodiment, such as Figures 9 to 11 As shown, the second pixel PX2 and the third pixel PX3 can share the contact area CNT_VIL2 that connects the seventh transistor T7 to the second initialization voltage line VIL2.

[0138] In an embodiment, the arrangement of the devices in the third pixel PX3 and the first pixel PX1 (the first pixel PX1 arranged to the right of the third pixel PX3) can be the same as... Figures 9 to 11 The devices in the first pixel PX1 and the second pixel PX2 in the diagram are arranged in the same way.

[0139] In an embodiment, the arrangement of the devices in the first pixel PX1 and the third pixel PX3 (the third pixel PX3 arranged to the left of the first pixel PX1) can be consistent with... Figures 9 to 11 The devices in the second pixel PX2 and the third pixel PX3 in the diagram are arranged in the same way.

[0140] Figure 12 This is a schematic diagram illustrating the positions of the transistors and capacitors of a pixel according to an embodiment. Figures 13 to 19 It is a schematic diagram layer by layer. Figure 12 A diagram of pixel-based elements. Figure 20 It is along Figure 12 The line I-I' intercepted Figure 12 A cross-sectional view of the region.

[0141] The display area DA defined on the substrate 100 may include multiple circuit areas. A circuit area may be a region where rows (pixel rows) and columns (pixel columns) intersect each other, and may be a region where pixel circuits are arranged. In embodiments, a unit circuit area may be defined, comprising two or more circuit areas adjacent to each other in the x-direction, and a unit pixel may be defined by pixels arranged in the circuit area constituting the unit circuit area. For example, a unit circuit area PCAu may include a first circuit area PCA1, a second circuit area PCA2, and a third circuit area PCA3 as three circuit areas adjacent to each other in the x-direction, and a unit pixel may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first circuit area PCA1 may be the region where the pixel circuit of the first pixel PX1 is arranged. The second circuit area PCA2 may be the region where the pixel circuit of the second pixel PX2 is arranged. The third circuit area PCA3 may be the region where the pixel circuit of the third pixel PX3 is arranged.

[0142] Figure 12 The first pixel PX1, the second pixel PX2, and the third pixel PX3 in the diagram can be compared with... Figure 10 The first pixel PX1, the second pixel PX2, and the third pixel PX3 in the diagram correspond to each other.

[0143] First pixel PX1 and second pixel PX2 can share an eighth transistor T8 and a contact area CNT_VBL that connects the eighth transistor T8 to the bias voltage line VBL. In some aspects, first pixel PX1 and second pixel PX2 can share a second sub-transistor T5-2 of fifth transistor T5 and a contact area CNT_VRL that connects the second sub-transistor T5-2 to the reference voltage line VRL. In other words, the fifth transistor T5 of first pixel PX1 and the fifth transistor T5 of second pixel PX2 can share a second sub-transistor T5-2 and a contact area CNT_VRL that connects the second sub-transistor T5-2 to the reference voltage line VRL.

[0144] The second pixel PX2 and the third pixel PX3 can share the second sub-transistor T4-2 of the fourth transistor T4, and can also share the contact area CNT_VIL1 that connects the second sub-transistor T4-2 to the first initialization voltage line VIL1. In other words, the fourth transistor T4 of the second pixel PX2 and the fourth transistor T4 of the third pixel PX3 can share the second sub-transistor T4-2, and can also share the contact area CNT_VIL1 that connects the second sub-transistor T4-2 to the first initialization voltage line VIL1.

[0145] The same devices can be disposed on each layer of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. In the following description, for ease of illustration and description, the devices of the pixel circuit PC arranged in the first circuit region PCA1 are given reference numerals, primarily describing the first circuit region PCA1, and the same description can be applied to the same elements in the second circuit region PCA2 and the third circuit region PCA3. See below for further reference. Figures 13 to 20 A description is provided. In the following text, a connecting electrode can be an electrode that transmits signals by electrically connecting a conductive wire to an electrode (conductive pattern) disposed on different layers.

[0146] like Figure 13 and Figure 20 As shown, the first insulating layer 101 may be disposed on the substrate 100, and the semiconductor layer ACT may be disposed on the first insulating layer 101.

[0147] The semiconductor layer ACT may include silicon semiconductor. The semiconductor layers ACT of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3 may be integrally formed and interconnected. The semiconductor layer ACT may include the source region, the drain region, and the channel region between the source and drain regions of each of the first transistor T1 to the ninth transistor T9.

[0148] Figure 15 This is a diagram illustrating the transistors in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. (Reference) Figure 15 The semiconductor layer ACT may include the source region S1 and drain region D1 of the first transistor T1, the source region S2 and drain region D2 of the second transistor T2, the source regions S31 and S32 and drain regions D31 and D32 of the third transistor T3, the source regions S41 and S42 and drain regions D41 and D42 of the fourth transistor T4, the source regions S51 and S52 and drain regions D51 and D52 of the fifth transistor T5, the source region S6 and drain region D6 of the sixth transistor T6, the source region S7 and drain region D7 of the seventh transistor T7, the source region S8 and drain region D8 of the eighth transistor T8, and the source region S9 and drain region D9 of the ninth transistor T9.

[0149] The first pixel PX1 and the second pixel PX2 can share the second sub-transistor T5-2 of the fifth transistor T5 (in other words, the fifth transistor T5 of the first pixel PX1 and the fifth transistor T5 of the second pixel PX2 can share the second sub-transistor T5-2), and the semiconductor layer of the second sub-transistor T5-2 can be located at the boundary between the first circuit region PCA1 and the second circuit region PCA2.

[0150] The first pixel PX1 and the second pixel PX2 can share the eighth transistor T8, and the semiconductor layer of the eighth transistor T8 can be located at the boundary between the first circuit region PCA1 and the second circuit region PCA2.

[0151] The second pixel PX2 and the third pixel PX3 can share the second sub-transistor T4-2 of the fourth transistor T4 (in other words, the fourth transistor T4 of the second pixel PX2 and the fourth transistor T4 of the third pixel PX3 can share the second sub-transistor T4-2), and the semiconductor layer of the second sub-transistor T4-2 can be located at the boundary between the second circuit region PCA2 and the third circuit region PCA3.

[0152] like Figure 14 and Figure 20 As shown, the second insulating layer 102 may be disposed above the first insulating layer 101 and cover the semiconductor layer ACT, and the first conductive layer ML1 may be disposed on the second insulating layer 102. The first conductive layer ML1 may include a second gate line GIL, a third gate line GCL, a fifth gate line EML2, a sixth gate line EBL, a first electrode 211, a second electrode 212, and a third electrode 213.

[0153] The first electrode 211, the second electrode 212, and the third electrode 213 may each be island-shaped. The first electrode 211, the second electrode 212, and the third electrode 213 may be arranged in each of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3.

[0154] The second gate line GIL can extend in the x direction and can be separated at the boundary between the circuit regions of the pixels sharing the fifth transistor T5-2 (e.g., the boundary between the first circuit region PCA1 and the second circuit region PCA2).

[0155] The fifth gate line EML2 can extend in the x direction and can be separated at the boundary between the circuit regions of the pixels sharing the eighth transistor T8 (e.g., the boundary between the first circuit region PCA1 and the second circuit region PCA2).

[0156] The third gate line GCL and the sixth gate line EBL can extend in the x direction and can be arranged across the first circuit region PCA1, the second circuit region PCA2 and the third circuit region PCA3.

[0157] like Figure 15 As shown, the first conductive layer ML1 may include the gate electrodes G1 to G9 of the first transistor T1 to the ninth transistor T9. The gate electrodes G1 to G9 may overlap with the channel region of the semiconductor layer ACT.

[0158] The first electrode 211 may include the gate electrode G1 of the first transistor T1. The first electrode 211 may also include the first electrode C11 of the first capacitor C1 (see reference). Figure 20 The second electrode 212 may include the gate electrode G2 of the second transistor T2. The third electrode 213 may include the gate electrode G9 of the ninth transistor T9. The gate electrodes G41 and G42 of the fourth transistor T4 may be part of the second gate line GIL. The gate electrodes G51 and G52 of the fifth transistor T5 may be part of the third gate line GCL. The gate electrode G6 of the sixth transistor T6 may be part of the fifth gate line EML2. The gate electrode G7 of the seventh transistor T7 may be part of the sixth gate line EBL. The gate electrode G8 of the eighth transistor T8 may be part of the sixth gate line EBL.

[0159] The gate electrode G52 of the second sub-transistor T5-2 of the fifth transistor T5, which is shared by the first pixel PX1 and the second pixel PX2, can be located at the boundary between the first circuit region PCA1 and the second circuit region PCA2.

[0160] The gate electrode G8 of the eighth transistor T8, which is shared by the first pixel PX1 and the second pixel PX2, can be located at the boundary between the first circuit region PCA1 and the second circuit region PCA2.

[0161] The gate electrode G42 of the second sub-transistor T4-2 of the fourth transistor T4, which is shared by the second pixel PX2 and the third pixel PX3, can be located at the boundary between the second circuit region PCA2 and the third circuit region PCA3.

[0162] like Figure 16 and Figure 20 As shown, the third insulating layer 103 may be disposed on the second insulating layer 102 and cover the first conductive layer ML1, and the second conductive layer ML2 may be disposed on the third insulating layer 103. The second conductive layer ML2 may include a fourth electrode 221 and a fifth electrode 222.

[0163] The fourth electrode 221 and the fifth electrode 222 may each be island-shaped. The fourth electrode 221 and the fifth electrode 222 may be arranged in each of the first circuit region PCA1, the second circuit region PCA2 and the third circuit region PCA3.

[0164] The fourth electrode 221 may overlap with the first electrode 211, and an opening GOP may be defined in the fourth electrode 221. The fourth electrode 221 may include the second electrode C12 of the first capacitor C1 (see reference). Figure 20 The fourth electrode 221 may include the first electrode C21 of the second capacitor C2 (see reference). Figure 20 ).

[0165] The fifth electrode 222 may overlap with the semiconductor region between the gate electrodes G31 and G32 of the third transistor T3 (e.g., the semiconductor region between two channel regions) and the semiconductor region between the gate electrodes G41 and G42 of the fourth transistor T4 (e.g., the semiconductor region between two channel regions). The fifth electrode 222 may be a shielding layer of the semiconductor layer.

[0166] like Figure 17 and Figure 20 As shown, the fourth insulating layer 104 may be disposed on the third insulating layer 103 and cover the second conductive layer ML2, and the third conductive layer ML3 may be disposed on the fourth insulating layer 104. The third conductive layer ML3 may include a reference voltage line VRL, a horizontal voltage line HL, and a second initialization voltage line VIL2.

[0167] The reference voltage line VRL, the horizontal voltage line HL, and the second initialization voltage line VIL2 can extend in the x direction and can be arranged across the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3.

[0168] The horizontal voltage line HL may overlap with the first electrode 211 and the fourth electrode 221. An opening SOP may be defined in the horizontal voltage line HL. The opening SOP may overlap with the opening GOP of the fourth electrode 221. The size of the opening SOP may be larger than the size of the opening GOP. The horizontal voltage line HL may include the second electrode C22 of the second capacitor C2 (see reference). Figure 20 ).

[0169] like Figure 18 and Figure 20As shown, the fifth insulating layer 105 may be disposed on the fourth insulating layer 104 and cover the third conductive layer ML3, and the fourth conductive layer ML4 may be disposed on the fifth insulating layer 105. The fourth conductive layer ML4 may include a first initialization voltage line VIL1, a first gate line GWL, a fourth gate line EML1, a bias voltage line VBL, and connecting electrodes 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, and 241.

[0170] The first initialization voltage line VIL1, the first gate line GWL, the fourth gate line EML1, and the bias voltage line VBL can extend in the x direction and can be arranged across the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3.

[0171] The first initialization voltage line VIL1 can be connected to the drain region D42 of the second sub-transistor T4-2 of the fourth transistor T4 through a contact hole CH1 that penetrates the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105. The contact hole CH1 can be located in the contact area CNT_VIL1 where the drain region D42 of the second sub-transistor T4-2 of the fourth transistor T4 is connected to the first initialization voltage line VIL1.

[0172] The first gate line GWL can be connected to the second electrode 212 of the gate electrode G2 of the second transistor T2 through the contact hole CH2 that penetrates the third insulating layer 103, the fourth insulating layer 104 and the fifth insulating layer 105.

[0173] The fourth gate line EML1 can be connected to the gate electrode G9 of the ninth transistor T9 through the contact hole CH3 that penetrates the third insulating layer 103, the fourth insulating layer 104 and the fifth insulating layer 105.

[0174] The bias voltage line VBL can be connected to the source region S8 of the eighth transistor T8 through a contact hole CH4 that penetrates the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105. The contact hole CH4 can be located in the contact area CNT_VBL where the source region S8 of the eighth transistor T8 is connected to the bias voltage line VBL.

[0175] The connecting electrode 231 can be connected to the source region S2 of the second transistor T2 through the contact hole CH5 that penetrates the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104 and the fifth insulating layer 105.

[0176] The connecting electrode 232 can be arranged between two adjacent circuit regions and can be connected to the second gate line GIL. For example, the connecting electrode 232 can be located at the boundary between the first circuit region PCA1 and the second circuit region PCA2, and can be connected to the second gate line GIL through contact holes CH6a and CH6b penetrating the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105. Accordingly, the second gate line GIL separated at the boundary between the first circuit region PCA1 and the second circuit region PCA2 can be connected.

[0177] The connecting electrode 233 can be connected to the source region S5 of the second sub-transistor T5-2 of the fifth transistor T5 through the contact hole CH7 penetrating the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105. The connecting electrode 233 can be connected to the reference voltage line VRL through the contact hole CH8 penetrating the fifth insulating layer 105. The region including the contact holes CH7 and CH8 can be the contact region CNT_VRL where the source region S5 of the second sub-transistor T5-2 is connected to the reference voltage line VRL.

[0178] Connection electrode 234 can be connected to the reference voltage line VRL through contact hole CH9 penetrating the fifth insulating layer 105. Connection electrode 234 can be connected to the fifth electrode 222 through contact hole CH10 penetrating the fourth insulating layer 104 and the fifth insulating layer 105. Accordingly, the fifth electrode 222 can receive the reference voltage VREF.

[0179] The connecting electrode 235 can be connected to the horizontal voltage line HL through the contact hole CH11 that penetrates the fifth insulating layer 105.

[0180] The connecting electrode 236 can be connected to the drain region D6 of the sixth transistor T6 and the source region S7 of the seventh transistor T7 through the contact hole CH12 that penetrates the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104 and the fifth insulating layer 105.

[0181] The connecting electrode 237 can be connected to the drain region D31 of the first sub-transistor T3-1 of the third transistor T3 and the source region S41 of the first sub-transistor T4-1 of the fourth transistor T4 through a contact hole CH13 penetrating the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105. The connecting electrode 237 can also be connected to the first electrode 211 of the gate electrode G1 of the first transistor T1 through a contact hole CH14 penetrating the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105. The contact hole CH14 can be located in the opening GOP of the fourth electrode 221 and the opening SOP of the horizontal voltage line HL.

[0182] The connecting electrode 238 can be connected to the drain region D2 of the second transistor T2 and the drain region D51 of the first sub-transistor T5-1 of the fifth transistor T5 through a contact hole CH15 penetrating the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105. The connecting electrode 238 can be connected to the fourth electrode 221 through a contact hole CH16 penetrating the fourth insulating layer 104 and the fifth insulating layer 105. The contact hole CH16 can be located within the opening SOP of the horizontal voltage line HL.

[0183] The connecting electrode 239 can be connected to the horizontal voltage line HL through the contact hole CH17 penetrating the fifth insulating layer 105. The connecting electrode 239 can be connected to the source region S9 of the ninth transistor T9 through the contact hole CH18 penetrating the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104 and the fifth insulating layer 105.

[0184] The connecting electrode 240 can be arranged between two adjacent circuit regions and can be connected to the fifth gate line EML2. For example, the connecting electrode 240 can be located at the boundary between the first circuit region PCA1 and the second circuit region PCA2, and can be connected to the fifth gate line EML2 through contact holes CH19a and CH19b penetrating the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105. Accordingly, the fifth gate line EML2, which is separated at the boundary between the first circuit region PCA1 and the second circuit region PCA2, can be connected.

[0185] The connection electrode 241 can be arranged between two adjacent circuit regions. The connection electrode 241 can be connected to the drain region D7 of the seventh transistor T7 through a contact hole CH20 penetrating the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105. The connection electrode 241 can be connected to the second initialization voltage line VIL2 through a contact hole CH21 penetrating the fifth insulating layer 105. The contact hole CH20 can be located in the contact region CNT_VIL2 where the drain region D7 of the seventh transistor T7 is connected to the second initialization voltage line VIL2.

[0186] like Figure 19 and Figure 20 As shown, the sixth insulating layer 106 may be disposed on the fifth insulating layer 105 and cover the fourth conductive layer ML4, and the fifth conductive layer ML5 may be disposed on the sixth insulating layer 106. The fifth conductive layer ML5 may include a data line DL, a drive voltage line PL, a vertical reference voltage line VRLv, and a connection electrode 251.

[0187] The data line DL can be arranged in each circuit region while extending along the y-direction. The data line DL can be connected to the connection electrode 231 through the contact hole CH31 penetrating the sixth insulating layer 106. Because the connection electrode 231 is connected to the source region S2 of the second transistor T2, the data line DL can be connected to the source region S2 of the second transistor T2.

[0188] The driving voltage line PL can be connected to the connecting electrode 235 through the contact hole CH32 penetrating the sixth insulating layer 106. Because the connecting electrode 235 is connected to the horizontal voltage line HL, the horizontal voltage line HL can receive the driving voltage ELVDD. In this embodiment, the horizontal voltage line HL can be referred to as the first driving voltage line in the x-direction, and the driving voltage line PL can be referred to as the second driving voltage line in the y-direction. Due to the horizontal voltage line HL and the driving voltage line PL, the conductive line configured to supply the driving voltage ELVDD can be understood as having a grid structure. Figure 9 The driving voltage line PL shown in the diagram can be connected to... Figure 17 The horizontal voltage line HL in the diagram corresponds to this.

[0189] The vertical reference voltage line VRLv can be connected to the connecting electrode 234 through the contact hole CH33 penetrating the sixth insulating layer 106, and the connecting electrode 234 is connected to the reference voltage line VRL. The reference voltage line VRL can be referred to as the horizontal reference voltage line, and due to the reference voltage line VRL and the vertical reference voltage line VRLv, the conductive line configured to supply the reference voltage VREF can be understood as having a grid structure.

[0190] The connecting electrode 251 can be connected to the connecting electrode 236 through the contact hole CH34 that penetrates the sixth insulating layer 106.

[0191] like Figure 20 As shown, the seventh insulating layer 107 can be disposed on the sixth insulating layer 106 and cover the fifth conductive layer ML5, and the organic light-emitting diode (OLED) can be disposed on the seventh insulating layer 107.

[0192] An organic light-emitting diode (OLED) may include a pixel electrode 311, a counter electrode 315, and an intermediate layer 313 between the pixel electrode 311 and the counter electrode 315. An eighth insulating layer 108 may be disposed on the seventh insulating layer 107. The eighth insulating layer 108 may cover a portion of the pixel electrode 311.

[0193] Pixel electrode 311 can pass through contact hole CH41 of seventh insulating layer 107 (reference). Figure 19The pixel electrode 311 is connected to the connection electrode 251, which in turn is connected to the connection electrode 236. Because the connection electrode 236 is connected to the drain region D6 of the sixth transistor T6, the pixel electrode 311 can be connected to the drain region D6 of the sixth transistor T6.

[0194] Figures 21 to 23 This is a schematic diagram of pixels according to an embodiment. (Reference) Figures 21 to 23 The described pixels PXb, PXc, and PXd may include references Figures 3 to 5 This describes aspects of pixel PXa. The main focus here is on... Figures 3 to 5 The differences in pixel PXa shown in the diagram.

[0195] Figure 21 The pixel PXb in the diagram is... Figure 3 The difference in the pixel PXa shown in the diagram is that the eighth transistor T8 and the ninth transistor T9 are omitted, and the fifth transistor T5 is connected to the drive voltage line PL.

[0196] A fifth transistor T5 can be connected between the fourth node N4 and the drive voltage line PL. The fifth transistor T5 may include a gate connected to the third gate line GCL, a first terminal connected to the drive voltage line PL, and a second terminal connected to the fourth node N4. The fifth transistor T5 can be turned on according to the third gate signal GC received through the third gate line GCL to transmit the drive voltage ELVDD to the fourth node N4.

[0197] In an embodiment, such as Figure 21 As shown, the fifth transistor T5 of pixel PXb can be a dual-gate transistor in which a pair of sub-transistors (e.g., the first sub-transistor T5-1 and the second sub-transistor T5-2) are connected in series.

[0198] In an embodiment, such as Figure 21 As shown, the third transistor T3 of pixel PXb can be a dual-gate transistor in which a pair of sub-transistors (e.g., the first sub-transistor T3-1 and the second sub-transistor T3-2) are connected in series.

[0199] like Figure 21 As shown, the fourth transistor T4 of pixel PXb can be a dual-gate transistor in which a pair of sub-transistors (e.g., the first sub-transistor T4-1 and the second sub-transistor T4-2) are connected in series.

[0200] Figure 22 The pixel PXc in the diagram is... Figure 3 The difference in pixel PXa shown in the diagram is that the second capacitor C2, the fifth transistor T5, and the eighth transistor T8 are omitted, and the connection relationships between some of the other transistors and the first capacitor C1 are also omitted. Figure 22The pixel PXc shown in the diagram is different Figure 3 The pixel PXa shown in the diagram.

[0201] A second transistor T2 can be connected between the data line DL and the second node N2. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the second node N2. The second transistor T2 can be turned on according to a first gate signal GW received through the first gate line GWL to perform a switching operation for transmitting the data signal DATA transmitted to the data line DL to the second node N2.

[0202] The first capacitor C1 can be connected between the driving voltage line PL and the first node N1.

[0203] In an embodiment, pixel PXc may further include a boost capacitor Cb, and the boost capacitor Cb may be connected between the gate of the second transistor T2 and the first node N1.

[0204] The gates of the ninth transistor T9 and the sixth transistor T6 can be connected to a gate line EML configured to receive a gate signal EM. In an embodiment, the gate line EML can be configured to receive a fourth gate signal EM1. Figures 3 to 5 The fourth gate line EML1 () Figures 3 to 5 In an embodiment, the gate line EML may be configured to receive the fifth gate signal EM2. Figures 3 to 5 The fifth gate line EML2 () Figures 3 to 5 ).exist Figure 22 In pixel PXc shown in the diagram, the gates of the ninth transistor T9 and the sixth transistor T6 can be connected to the same gate line to receive the same gate signal, thus enabling them to... Figure 3 The pixel PXa shown in the diagram has a reduced number of grid lines and grid signals compared to the previous version.

[0205] In an embodiment, such as Figure 22 As shown, the third transistor T3 of pixel PXc can be a dual-gate transistor in which a pair of sub-transistors (e.g., the first sub-transistor T3-1 and the second sub-transistor T3-2) are connected in series.

[0206] In an embodiment, such as Figure 22 As shown, the fourth transistor T4 of pixel PXc can be a dual-gate transistor in which a pair of sub-transistors (e.g., the first sub-transistor T4-1 and the second sub-transistor T4-2) are connected in series.

[0207] Figure 23 The pixel PXd in the diagram is... Figure 3The difference in pixel PXa shown in the diagram is that the fifth transistor T5 is omitted, and the connection relationships between some of the other transistors and the first capacitor C1 and the second capacitor C2 are also different. Figure 23 The pixel PXd shown in the diagram is different Figure 3 The pixel PXa shown in the diagram.

[0208] A second transistor T2 can be connected between the data line DL and the second node N2. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the second node N2. The second transistor T2 can be turned on according to a first gate signal GW received through the first gate line GWL to transmit the data signal DATA transmitted to the data line DL to the second node N2.

[0209] The first capacitor C1 can be connected between the driving voltage line PL and the first node N1.

[0210] The second capacitor C2 can be connected between the drive voltage line PL and the second node N2.

[0211] The gates of the ninth transistor T9 and the sixth transistor T6 can be connected to a gate line EML configured to receive a gate signal EM. In an embodiment, the gate line EML can be configured to receive a fourth gate signal EM1. Figures 3 to 5 The fourth gate line EML1 () Figures 3 to 5 In an embodiment, the gate line EML may be configured to receive the fifth gate signal EM2. Figures 3 to 5 The fifth gate line EML2 () Figures 3 to 5 ).

[0212] In an embodiment, such as Figure 4 and Figure 5 As shown, Figure 23 The third transistor T3 of pixel PXd can be a dual-gate transistor in which a pair of sub-transistors (e.g., the first sub-transistor T3-1 and the second sub-transistor T3-2) are connected in series.

[0213] In an embodiment, such as Figure 4 and Figure 5 As shown, Figure 23 The fourth transistor T4 of pixel PXd can be a dual-gate transistor in which a pair of sub-transistors (e.g., the first sub-transistor T4-1 and the second sub-transistor T4-2) are connected in series.

[0214] exist Figures 21 to 23 In the diagram, pixels PXb, PXc, and PXd, as shown... Figures 6A to 11As shown, neighboring pixels can share one of the sub-transistors of at least one of the fourth transistor T4 and the fifth transistor T5. For example, two neighboring pixels can share the second sub-transistor T4-2 of the fourth transistor T4 and can share the contact area connecting the second sub-transistor T4-2 to the first initialization voltage line VIL1. Two neighboring pixels can share the second sub-transistor T5-2 of the fifth transistor T5 and can share the contact area connecting the second sub-transistor T5-2 to the drive voltage line PL. In other words, the respective fifth transistor T5 of neighboring pixels can share the second sub-transistor T5-2 and can share the contact area connecting the second sub-transistor T5-2 to the drive voltage line PL.

[0215] exist Figures 21 to 23 In the diagram, pixels PXb, PXc, and PXd, as shown... Figures 6A to 11 As shown, neighboring pixels can share at least one transistor constituting the pixel circuit (e.g., at least one of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9). For example, two neighboring pixels can share the seventh transistor T7 and can share the contact area connecting the seventh transistor T7 to the second initialization voltage line VIL2. Two neighboring pixels can share the eighth transistor T8 and can share the contact area connecting the eighth transistor T8 to the bias voltage line VBL. Two neighboring pixels can share the ninth transistor T9 and can share the contact area connecting the ninth transistor T9 to the drive voltage line PL.

[0216] exist Figures 21 to 23 In the diagram, pixels PXb, PXc, and PXd, as shown... Figures 6A to 11 As shown, neighboring pixels can share a contact area that connects at least one transistor constituting the pixel circuit to a voltage line. For example, two neighboring pixels can each include a seventh transistor T7 and can share a contact area that connects the seventh transistor T7 to the second initialization voltage line VIL2. Two neighboring pixels can each include an eighth transistor T8 and can share a contact area that connects the eighth transistor T8 to the bias voltage line VBL. Two neighboring pixels can each include a ninth transistor T9 and can share a contact area that connects the ninth transistor T9 to the drive voltage line PL.

[0217] Figure 24 This is a schematic diagram illustrating the sharing of transistors between adjacent pixels according to an embodiment. Figure 24 This is a schematic diagram illustrating the sharing of a fourth transistor between adjacent pixels. Figure 24 It is a diagram. Figure 21 The image shown in the middle is a graph of pixels.

[0218] refer to Figure 24Left pixel PXL and right pixel PXR, which are adjacent to each other in the x-direction (row direction), can share the second sub-transistor T4-2 of the fourth transistor T4. In other words, the respective fourth transistor T4 of the left pixel PXL and right pixel PXR can share the second sub-transistor T4-2.

[0219] The second sub-transistor T4-2 of the fourth transistor T4 can be arranged in the boundary region between the left pixel PXL and the right pixel PXR. Regarding the boundary between the left pixel PXL and the right pixel PXR, the first transistors T1 to T7 of the left pixel PXL, as well as the first capacitor C1 and the second capacitor C2, can be arranged symmetrically with the first transistors T1 to T7 of the right pixel PXR, as well as the first capacitor C1 and the second capacitor C2.

[0220] The second sub-transistor T4-2 of the fourth transistor T4 can be connected to the first initialization voltage line VIL1 in the contact area CNT_VIL1. The left pixel PXL and the right pixel PXR can share the second sub-transistor T4-2 and can share the contact area CNT_VIL1 that connects the second sub-transistor T4-2 to the first initialization voltage line VIL1.

[0221] Left pixel PXL and right pixel PXR may each include a seventh transistor T7, and the seventh transistor T7 of left pixel PXL and right pixel PXR may be connected to the second initialization voltage line VIL2 in the contact area CNT_VIL2. Left pixel PXL and right pixel PXR may share the contact area CNT_VIL2 where the seventh transistor T7 of left pixel PXL and right pixel PXR are connected to the second initialization voltage line VIL2.

[0222] According to one or more of the above embodiments, the pixel circuits can be arranged symmetrically about the boundaries between adjacent pixels, and pixels having symmetrical pixel circuits can share at least one transistor and at least one contact area. Accordingly, embodiments of this disclosure support achieving high-resolution display devices by improving the integration efficiency of pixel circuits and increasing pixel density.

[0223] According to one or more of the above embodiments, a high-resolution display device can be provided. However, one or more embodiments are not limited by such effects.

[0224] It should be understood that the embodiments described herein are to be considered in a descriptive sense and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: Multiple pixels, Each of the plurality of pixels includes: First transistor; The second transistor is connected to the data line; The third transistor is connected to the gate of the first transistor and the second terminal of the first transistor; A fourth transistor is connected to the gate of the first transistor and the first initialization voltage line; A fifth transistor, connected to the second transistor and the reference voltage line, wherein the fifth transistor includes a first sub-transistor; and A capacitor is connected to the gate of the first transistor and the second transistor. The plurality of pixels includes a first pixel and a second pixel adjacent to the first pixel. The fifth transistor included in the first pixel and the fifth transistor included in the second pixel further include a second sub-transistor shared by the first pixel and the second pixel, and The second sub-transistor is shared by the first pixel and the second pixel: It is connected in series with the first sub-transistor of the fifth transistor of the first pixel, and is closer to the reference voltage line than the first sub-transistor of the fifth transistor of the first pixel; and It is connected in series with the first sub-transistor of the fifth transistor of the second pixel, and is closer to the reference voltage line than the first sub-transistor of the fifth transistor of the second pixel.

2. The display device according to claim 1, wherein, The first pixel and the second pixel share the contact area where the second sub-transistor is connected to the reference voltage line.

3. The display device according to claim 1, wherein, The second sub-transistor is arranged at the boundary between the first pixel and the second pixel, and The arrangement of transistors in the first pixel, excluding the second sub-transistor, and the arrangement of transistors in the second pixel, excluding the second sub-transistor, are symmetrical about the boundary between the first pixel and the second pixel.

4. The display device according to claim 1, wherein, The first pixel and the second pixel share a sixth transistor connected to the driving voltage line, and The sixth transistor, shared by the first pixel and the second pixel, is connected to the first terminal of the first transistor of the first pixel and the first terminal of the first transistor of the second pixel.

5. The display device according to claim 4, wherein, The sixth transistor, shared by the first pixel and the second pixel, is arranged at the boundary between the first pixel and the second pixel, and The arrangement of transistors in the first pixel (excluding the sixth transistor) and the arrangement of transistors in the second pixel (excluding the sixth transistor) are symmetrical about the boundary between the first pixel and the second pixel.

6. The display device according to claim 1, wherein, The first pixel and the second pixel share a seventh transistor connected to the bias voltage line, and The seventh transistor, shared by the first pixel and the second pixel, is connected to the first terminal of the first transistor of the first pixel and the first terminal of the first transistor of the second pixel.

7. The display device according to claim 6, wherein, The seventh transistor, shared by the first pixel and the second pixel, is arranged at the boundary between the first pixel and the second pixel, and The arrangement of transistors in the first pixel (excluding the seventh transistor) and the arrangement of transistors in the second pixel (excluding the seventh transistor) are symmetrical about the boundary between the first pixel and the second pixel.

8. The display device according to claim 1, wherein, The fourth transistor includes a first sub-transistor. The plurality of pixels further includes a third pixel adjacent to the second pixel. Wherein, the fourth transistor included in the second pixel and the fourth transistor included in the third pixel further include a second sub-transistor shared by the second pixel and the third pixel, and The second sub-transistor is shared by the second pixel and the third pixel: It is connected in series with the first sub-transistor of the fourth transistor of the second pixel, and is closer to the first initialization voltage line than the first sub-transistor of the fourth transistor of the second pixel; and It is connected in series with the first sub-transistor of the fourth transistor of the third pixel, and is closer to the first initialization voltage line than the first sub-transistor of the fourth transistor of the third pixel.

9. The display device according to claim 8, wherein, The second sub-transistor of the fourth transistor is arranged at the boundary between the second pixel and the third pixel, and The arrangement of transistors in the second pixel, excluding the second sub-transistor of the fourth transistor, and the arrangement of transistors in the third pixel, excluding the second sub-transistor of the fourth transistor, are symmetrical about the boundary between the second pixel and the third pixel.

10. The display device according to claim 1, wherein, Each of the plurality of pixels further includes: The eighth transistor is connected to the second terminal of the first transistor and the light-emitting element; and The ninth transistor is connected to the light-emitting element and the second initialization voltage line. The plurality of pixels further includes a third pixel adjacent to the second pixel, and Wherein, the second pixel and the third pixel share the contact area where the ninth transistor of the second pixel and the ninth transistor of the third pixel are connected to the second initialization voltage line.

11. A display device, comprising: Multiple pixels, Each of the plurality of pixels includes: First transistor; The second transistor is connected to the data line; The third transistor is connected to the gate of the first transistor and the second terminal of the first transistor; A fourth transistor is connected to the gate of the first transistor and the first initialization voltage line; The fifth transistor is connected to the second transistor and the reference voltage line; and A capacitor is connected to the gate of the first transistor and the second transistor. The plurality of pixels includes a first pixel and a second pixel adjacent to the first pixel. The first pixel and the second pixel share a sixth transistor connected to the bias voltage line, and The sixth transistor, shared by the first pixel and the second pixel, is connected to the first terminal of the first transistor of the first pixel and the first terminal of the first transistor of the second pixel.

12. The display device according to claim 11, wherein, The sixth transistor, shared by the first pixel and the second pixel, is arranged at the boundary between the first pixel and the second pixel, and The arrangement of transistors in the first pixel (excluding the sixth transistor) and the arrangement of transistors in the second pixel (excluding the sixth transistor) are symmetrical about the boundary between the first pixel and the second pixel.

13. The display device according to claim 11, wherein, The first pixel and the second pixel share a seventh transistor connected to the driving voltage line, and The seventh transistor, shared by the first pixel and the second pixel, is connected to the first terminal of the first transistor of the first pixel and the first terminal of the first transistor of the second pixel.

14. The display device according to claim 13, wherein, The seventh transistor, shared by the first pixel and the second pixel, is arranged at the boundary between the first pixel and the second pixel, and The arrangement of transistors in the first pixel (excluding the seventh transistor) and the arrangement of transistors in the second pixel (excluding the seventh transistor) are symmetrical about the boundary between the first pixel and the second pixel.

15. The display device according to claim 11, wherein, The first pixel and the second pixel share a contact area where the fifth transistor of the first pixel and the fifth transistor of the second pixel are connected to the reference voltage line.

16. The display device according to claim 11, wherein: The fifth transistor included in the first pixel and the fifth transistor included in the second pixel each include a first sub-transistor, and The fifth transistor included in the first pixel and the fifth transistor included in the second pixel further include a second sub-transistor shared by the first pixel and the second pixel. The second sub-transistor is shared by the first pixel and the second pixel: It is connected in series with the first sub-transistor of the fifth transistor of the first pixel, and is closer to the reference voltage line than the first sub-transistor of the fifth transistor of the first pixel; and The first sub-transistor of the fifth transistor of the second pixel is connected in series with the first sub-transistor of the fifth transistor of the second pixel and is closer to the reference voltage line than the first sub-transistor of the fifth transistor of the second pixel, wherein the first pixel and the second pixel share the contact area where the second sub-transistor is connected to the reference voltage line.

17. The display device according to claim 16, wherein, The second sub-transistor is arranged at the boundary between the first pixel and the second pixel, and The arrangement of transistors in the first pixel, excluding the second sub-transistor, and the arrangement of transistors in the second pixel, excluding the second sub-transistor, are symmetrical about the boundary between the first pixel and the second pixel.

18. The display device according to claim 11, wherein, The fourth transistor includes a first sub-transistor. The plurality of pixels further includes a third pixel adjacent to the second pixel. Wherein, the fourth transistor included in the second pixel and the fourth transistor included in the third pixel further include a second sub-transistor shared by the second pixel and the third pixel, and The second sub-transistor is shared by the second pixel and the third pixel: It is connected in series with the first sub-transistor of the fourth transistor of the second pixel, and is closer to the first initialization voltage line than the first sub-transistor of the fourth transistor of the second pixel; and It is connected in series with the first sub-transistor of the fourth transistor of the third pixel, and is closer to the first initialization voltage line than the first sub-transistor of the fourth transistor of the third pixel.

19. The display device according to claim 18, wherein, The second sub-transistor of the fourth transistor is arranged at the boundary between the second pixel and the third pixel, and The arrangement of transistors in the second pixel, excluding the second sub-transistor of the fourth transistor, and the arrangement of transistors in the third pixel, excluding the second sub-transistor of the fourth transistor, are symmetrical about the boundary between the second pixel and the third pixel.

20. The display device according to claim 11, wherein, Each of the plurality of pixels further includes: The seventh transistor is connected to the drive voltage line; The eighth transistor is connected to the second terminal of the first transistor and the light-emitting element; and The ninth transistor is connected to the light-emitting element and the second initialization voltage line. The plurality of pixels further includes a third pixel adjacent to the second pixel, and Wherein, the second pixel and the third pixel share the contact area where the ninth transistor of the second pixel and the ninth transistor of the third pixel are connected to the second initialization voltage line.

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