High-yield LED chip preparation structure

Abstract

The utility model provides a high yield LED chip preparation structure, comprising an insulating layer, a photoresist layer arranged on the insulating layer, and a mask plate arranged on the photoresist layer, the mask plate is provided with a pattern hole and a plurality of exposure through holes, the pattern hole comprises a longitudinal edge and a transverse edge, and the longitudinal edge is provided with a plurality of exposure through holes. The exposure through hole is located between the transverse edge and the outer edge of the mask plate, and the exposure through hole is arranged around the transverse edge. According to the high-yield LED chip preparation structure provided by the utility model, the special mask plate is adopted and the hot reflux characteristic of photoresist is utilized, so that the edge of the prepared photoresist pattern has a gradient and is relatively mild, the gradient of the side wall of the insulating layer is reduced during ICP etching, the side wall is etched to have a relatively mild gradient, and the yield of the LED chip is improved. And the metal electrode film is uniformly deposited on the side wall, so that uniformly distributed current is obtained, the condition of open circuit is avoided, and the reliability of the LED chip is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technical field especially relates to a high yield's LED chip preparation structure. BACKGROUND

[0002] With the rapid development of semiconductor lighting technology, light emitting diode (LED) has become the mainstream choice of new generation lighting light source because of its high efficiency, energy saving, environmental protection and other advantages. Among many LED technologies, flip-chip LED (FCLED) gradually attracts widespread attention in the industry because of its superior thermal management performance and high light efficiency. The emerging LED application market is being continuously explored, and the LED industry still has good development prospects in the future. LED devices with higher efficiency and longer service life are still the current research focus.

[0003] For the reliability of LED chip, the uniformity and continuity of the prepared metal electrode are crucial. When the insulating layer is thick, the insulating layer sidewall angle after deep etching is often steep. After depositing metal electrode on the steep sidewall, the thickness distribution of the sidewall metal is uneven, and even delamination may occur at the bottom, resulting in uneven distribution of its resistance value. When an external current is applied, due to the uneven distribution of resistance, the metal thin place is heated to burn out when the current increases to a certain extent, resulting in LED failure, and then the situation of turn-on and open circuit occurs. SUMMARY

[0004] In view of the deficiencies of the prior art, the purpose of the utility model is to provide a high yield LED chip preparation structure, aiming at solving the technical problems mentioned in the background art.

[0005] In order to achieve the above purpose, the utility model is realized by the following technical scheme:

[0006] A high yield LED chip preparation structure, comprising an insulating layer, a photoresist layer on the insulating layer, and a mask plate on the photoresist layer, the mask plate is provided with a pattern hole and a plurality of exposure through holes, the pattern hole comprises a longitudinal edge and a transverse edge, the exposure through hole is located between the transverse edge and the outer edge of the mask plate, and the exposure through hole is arranged around the transverse edge.

[0007] According to one aspect of the above technical scheme, the exposure through hole is provided with a plurality of sub-through hole layers from the transverse edge to the outer edge of the mask plate, and each sub-through hole layer comprises a plurality of single sub-through holes.

[0008] According to one aspect of the above technical scheme, the spacing of a plurality of sub-through hole layers is consistent, and the spacing of a plurality of single sub-through holes in each sub-through hole layer is consistent.

[0009] According to an aspect of the above technical solution, the pitch of the plurality of single sub-via holes in each sub-via hole layer increases from the lateral edge to the outer edge of the mask plate, and the aperture of the plurality of single sub-via holes in each sub-via hole layer decreases from the lateral edge to the outer edge of the mask plate.

[0010] According to an aspect of the above technical solution, the aperture of the single sub-via hole is less than 1.5um.

[0011] According to an aspect of the above technical solution, the lateral edge is in an arc shape, and the exposure via hole is in a fan shape along the arc-shaped lateral edge.

[0012] According to an aspect of the above technical solution, the lateral edge is in a stepped shape, and the exposure via hole is in a stepped shape along the stepped lateral edge, and the exposure via hole and the lateral edge are arranged in a nested manner.

[0013] According to an aspect of the above technical solution, the lateral edge is arranged in a straight line, and the exposure via hole is arranged in a rectangular shape along the straight lateral edge.

[0014] According to an aspect of the above technical solution, the insulating layer is made of silicon oxide material.

[0015] According to an aspect of the above technical solution, the thickness of the photoresist layer is 6um.

[0016] Compared with the prior art, the beneficial effects of the utility model lie in:

[0017] By setting a pattern hole and a plurality of exposure via holes on the mask plate, the exposure via hole is located between the lateral edge and the outer edge of the mask plate, and the exposure via hole is arranged around the lateral edge. When it is necessary to etch the photoresist layer to make a pattern, the mask plate is arranged on the photoresist layer, and ultraviolet light is irradiated on the mask plate. The ultraviolet light can expose the photoresist layer through the pattern hole and the exposure via hole. The photoresist layer under the pattern hole forms a pattern. Since the size of the exposure via hole is small, when the ultraviolet light is irradiated on the photoresist layer under the exposure via hole, the exposure intensity of the ultraviolet light can be reduced as much as possible by using the diffraction of light. After development, only part of the photoresist layer can be removed. By using the heat reflow characteristics of the photoresist, the side angle of the photoresist is smaller. Finally, the side wall angle of the insulating layer after etching is smaller, which prevents the steep side wall of the insulating layer from reducing the yield of the LED. At the same time, the structure can improve the side angle of the photoresist pattern after development, and further improve the reliability of the LED chip.

[0018] This invention employs a special photomask and utilizes the thermal reflow characteristics of photoresist to create a photoresist pattern with a gentle slope at the edges. During ICP etching, the inclination of the insulating layer sidewalls decreases, resulting in a gentler slope etched onto the sidewalls. This facilitates the uniform deposition of the metal electrode film on the sidewalls, thereby obtaining a uniformly distributed current, avoiding open circuits, and improving the reliability of the LED chip. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure at the mask plate in the prior art;

[0020] Figure 2 This is a schematic diagram of the structure of the mask plate in the first embodiment of this utility model;

[0021] Figure 3 for Figure 2 Enlarged view of the through hole in the middle;

[0022] Figure 4 This is a schematic diagram of the structure of the mask plate in the second embodiment of this utility model;

[0023] Figure 5 This is a schematic diagram of the structure of the mask plate in the third embodiment of this utility model;

[0024] Explanation of key component symbols:

[0025]

[0026] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this utility model. Detailed Implementation

[0027] To facilitate understanding of this utility model, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of this utility model are shown in the drawings. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this utility model will be more thorough and complete.

[0028] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] Please refer to the mask plate 10 in the prior art. Figure 1 It does not have an exposure via 30.

[0031] Please see Figures 2-3 The image shows a high-yield LED chip fabrication structure according to the first embodiment of the present invention, including an insulating layer, a photoresist layer on the insulating layer, and a mask 10 on the photoresist layer. The mask 10 is provided with patterned holes 20 and a plurality of exposure through holes 30. The patterned holes 20 include a longitudinal edge 21 and a transverse edge 22. The exposure through holes 30 are located between the transverse edge 22 and the outer edge of the mask 10, and the exposure through holes 30 are arranged around the transverse edge 22.

[0032] Understandably, this invention provides patterned holes 20 and multiple exposure vias 30 on a photomask 10. The exposure vias 30 are located between the lateral edge 22 and the outer edge of the photomask 10, surrounding the lateral edge 22. When etching the photoresist layer to create a pattern, the photomask 10 is placed on the photoresist layer, and ultraviolet light is irradiated onto the photomask 10. The ultraviolet light exposes the photoresist layer through the patterned holes 20 and the exposure vias 30. A pattern is formed on the photoresist layer below the patterned holes 20, while the exposure vias 30... Due to its small size, when ultraviolet light shines on the photoresist layer below the exposure via 30, the exposure intensity of the ultraviolet light can be reduced as much as possible by the diffraction of the light, so that only part of the photoresist layer can be removed after development. Then, by utilizing the thermal reflow characteristics of the photoresist, the side tilt angle of the photoresist will be smaller, which will ultimately make the side wall tilt angle of the insulating layer after etching smaller, preventing the steep side wall of the insulating layer from reducing the LED yield. At the same time, this structure ensures that the morphology of the photoresist layer will not be affected after development, while also improving the side tilt angle of the photolithographic pattern, further improving the reliability of the LED chip.

[0033] This invention employs a special photomask and utilizes the thermal reflow characteristics of photoresist to create a photoresist pattern with a gentle slope at the edges. During ICP etching, the inclination of the insulating layer sidewalls decreases, resulting in a gentler slope etched onto the sidewalls. This facilitates the uniform deposition of the metal electrode film on the sidewalls, thereby obtaining a uniformly distributed current, avoiding open circuits, and improving the reliability of the LED chip.

[0034] Specifically, in this embodiment, the exposure via 30 is provided with a plurality of sub-via layers 31 sequentially from the lateral edge 22 to the outer edge of the mask plate 10, and each sub-via layer 31 includes a plurality of single sub-vias 32; the spacing between the plurality of sub-via layers 31 is consistent, and the spacing between the plurality of single sub-vias 32 in each sub-via layer 31 is consistent; the spacing between the plurality of single sub-vias 32 in each sub-via layer 31 increases sequentially from the lateral edge 22 to the outer edge of the mask plate 10, and the aperture of the plurality of single sub-vias 32 in each sub-via layer 31 decreases sequentially from the lateral edge 22 to the outer edge of the mask plate 10.

[0035] Understandably, this arrangement of the vias 30 allows the photoresist layer to maintain a smoother slope after development. If each layer's individual vias 32 are identical, it can easily cause the slope of the photoresist layer to become concave, thereby affecting the etching effect of the insulating layer's sidewalls and ultimately impacting the performance of the LED chip.

[0036] Preferably, the aperture of the single sub-through hole 32 is less than 1.5 μm.

[0037] It is understandable that if the aperture of a single sub-via 32 is too large, it can easily lead to excessive intensity of ultraviolet light, which in turn can cause abnormal patterns of the photoresist below the patterned hole 20.

[0038] Furthermore, in this embodiment, the lateral edge 22 is arc-shaped, and the exposure vias 30 are distributed in a fan shape along the arc-shaped lateral edge 22.

[0039] Understandably, when the lateral edge 22 is arc-shaped, if the exposure vias 30 are still rectangularly distributed, the angle of the photoresist can only be improved from one direction, which can easily lead to a large difference between the side and end angles of the photoresist. Therefore, the exposure vias 30 are designed to be fan-shaped, so that the angle transition of the photoresist at the arc is smoother, which can ensure that the mask pattern after development is consistent with the designed pattern, thereby making the performance of the LED chip closer to the preset performance.

[0040] Preferably, as an embodiment of the present invention, the insulating layer is made of silicon oxide; the thickness of the photoresist layer is 6 μm.

[0041] This invention only makes structural improvements in the photoresist exposure and development process. The overall fabrication method of the LED chip is summarized as follows:

[0042] Step 1: The sapphire substrate was ultrasonically cleaned for 5 minutes using a mixed solution of deionized water, ammonia, and hydrogen peroxide to remove organic matter and particulate matter from the surface. Then, a 1µm gallium nitride buffer layer, a 4µm n-GaN layer, and three cycles of InGaN (3nm) / GaN (12nm) MQWs layers were grown sequentially on the sapphire substrate using MOCVD technology. Finally, a 20nm thick p-AlGaN layer and a p-GaN layer were grown to obtain a GaN epitaxial wafer, which was then cleaned with an organic solution.

[0043] Step 2: Create a pattern on the epitaxial wafer using photolithography, and use photoresist as a mask to etch the epitaxial layer to the N-type GaN layer using a dry etching process;

[0044] Step 3: Deposit a silicon oxide insulating layer with a thickness of 1500 nm using a PECVD device;

[0045] Step 4 (Steps involved in this utility model): Spin-coat a photoresist with a thickness of 6um onto the insulating layer, use a mask, expose with ultraviolet light at an exposure dose of 550mj, develop after exposure, and the hot plate temperature is 140℃ to obtain a preset pattern on the insulating layer.

[0046] Step 5: Using photoresist as a mask, dry etching is used to remove excess insulating layer and create conductive vias;

[0047] Step 6: Deposit multiple metal thin films (Ti / Al / Ni / Au) on the conductive vias using an electron beam evaporation device to form N-type and P-type electrodes, thus completing the chip fabrication.

[0048] In summary, the high-yield LED chip fabrication structure in the above embodiments of this utility model employs a special photomask and utilizes the thermal reflow characteristics of the photoresist, resulting in a gently sloping edge on the prepared photoresist pattern. During ICP etching, the inclination of the insulating layer sidewalls decreases, leading to a gentler slope etched onto the sidewalls. This facilitates the uniform deposition of the metal electrode film on the sidewalls, thereby obtaining a uniformly distributed current, avoiding open circuits, and improving the reliability of the LED chip.

[0049] Please refer to Figure 4 The diagram shows a high-yield LED chip fabrication structure in the second embodiment of this invention. The difference between this embodiment and the first embodiment is that:

[0050] The lateral edge 22 is stepped, and the exposure through-holes 30 are distributed in a stepped manner along the stepped lateral edge 22. The exposure through-holes 30 and the lateral edge 22 are interlocked.

[0051] Understandably, when the lateral edge 22 is stepped, the exposure via 30 is also designed to be stepped and fitted with the lateral edge 22. The principle is the same as described in the first embodiment, which is to make the angle transition of the photoresist at the stepped shape smoother, so as to ensure that the mask pattern after development is consistent with the designed pattern.

[0052] This embodiment further illustrates the importance of the exposure via 30 being positioned around the lateral edge 22.

[0053] Please see Figure 5 The diagram shows a high-yield LED chip fabrication structure in the third embodiment of this utility model. The difference between this embodiment and the first embodiment is that:

[0054] The lateral edge 22 is arranged in a straight line, and the exposure through hole 30 is arranged in a rectangular shape along the lateral edge 22.

[0055] Understandably, when the lateral edge 22 is set in a straight line, the bevel of the photoresist only appears in one direction (the direction parallel to the lateral edge 22). Therefore, the exposure vias 30 only need to be distributed in a rectangular shape. If there are too many exposure vias 30, the exposure of ultraviolet light will be greater, which will lead to abnormal patterns of the photoresist below the patterned holes 20.

[0056] It should be noted that when the lateral edge 22 is curved, the single sub-via 32 is a circular hole; when the lateral edge 22 is stepped or straight, the single sub-via 32 is a square hole. The purpose is to improve the smoothness of the photoresist layer slope.

[0057] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0058] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A high-yield LED chip fabrication structure, characterized in that, The device includes an insulating layer, a photoresist layer on the insulating layer, and a mask on the photoresist layer. The mask has patterned holes and a plurality of exposure vias. The patterned holes include a longitudinal edge and a transverse edge. The exposure vias are located between the transverse edge and the outer edge of the mask and are arranged around the transverse edge.

2. The high-yield LED chip fabrication structure according to claim 1, characterized in that, The exposure via is provided with a plurality of sub-via layers from the lateral edge to the outer edge of the mask, and each sub-via layer includes a plurality of single sub-vias.

3. The high-yield LED chip fabrication structure according to claim 2, characterized in that, The spacing between the multiple sub-via layers is consistent, and the spacing between the multiple individual sub-vias in each sub-via layer is consistent.

4. The high-yield LED chip fabrication structure according to claim 3, characterized in that, The spacing between the plurality of individual sub-vias in each sub-via layer increases sequentially from the lateral edge to the outer edge of the mask, and the aperture of the plurality of individual sub-vias in each sub-via layer decreases sequentially from the lateral edge to the outer edge of the mask.

5. The high-yield LED chip fabrication structure according to claim 4, characterized in that, The diameter of the single sub-through hole is less than 1.5 μm.

6. The high-yield LED chip fabrication structure according to claim 4, characterized in that, The lateral edge is arc-shaped, and the exposure vias are distributed in a fan shape along the arc-shaped lateral edge.

7. The high-yield LED chip fabrication structure according to claim 4, characterized in that, The lateral edge is stepped, and the exposure vias are distributed in a stepped manner along the stepped lateral edge. The exposure vias and the lateral edge are interlocked.

8. The high-yield LED chip fabrication structure according to claim 4, characterized in that, The lateral edges are arranged in a straight line, and the exposure vias are arranged in a rectangular pattern along the lateral edges of the straight lines.

9. The high-yield LED chip fabrication structure according to claim 1, characterized in that, The insulating layer is made of silicon oxide.

10. The high-yield LED chip fabrication structure according to claim 1, characterized in that, The thickness of the photoresist layer is 6 μm.

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