Semiconductor device structure

Abstract

The utility model discloses a semiconductor device structure. Comprising a substrate, a first insulating layer positioned above the substrate, a conductive cylinder positioned above the substrate and embedded in the first insulating layer, and a second insulating layer positioned above the first insulating layer and the conductive cylinder, a conductive via structure passing through the second insulating layer and connected to the conductive pillar; and a wire over the conductive via structure and the second insulating layer. In a first overlook angle of the conductive via structure, the conductive via structure has a first elongated shape.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to a semiconductor device structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to generation after generation of ICs. Each generation of circuits is smaller and more complex than the last. However, these advancements have increased the complexity of IC processes and manufacturing.

[0003] In the evolution of integrated circuits (ICs), functional density (i.e., the number of interconnects per chip area) has generally increased, while geometric dimensions (i.e., the smallest components (or lines) that can be formed using manufacturing processes) have decreased. This miniaturization process typically improves production efficiency and reduces associated costs.

[0004] However, as the size of feature components continues to shrink, the manufacturing process continues to become more difficult. Therefore, forming increasingly smaller and more reliable semiconductor devices has become a challenge. Utility Model Content

[0005] The purpose of this invention is to provide a semiconductor device structure to solve at least one of the above-mentioned problems.

[0006] In some embodiments, a semiconductor device structure is provided, comprising: a substrate; a first insulating layer located above the substrate; a conductive pillar located above the substrate and embedded in the first insulating layer; a second insulating layer located above the first insulating layer and the conductive pillar; a conductive via structure passing through the second insulating layer and connected to the conductive pillar, wherein, in a first top view angle, the conductive via structure has a first elongated shape; and a wire located above the conductive via structure and the second insulating layer.

[0007] According to one embodiment of the present invention, in a second top view of the conductive via structure and the wire, the wire has a second elongated shape, and a first long axis of the conductive via structure is parallel to a second long axis of the wire.

[0008] According to one embodiment of the present invention, in a second top view angle, the conductive column has a second elongated shape.

[0009] According to one embodiment of the present invention, the conductive through-hole structure is wider than the conductive pillar.

[0010] According to one embodiment of the present invention, the conductive pillar extends into the conductive through-hole structure.

[0011] In some embodiments, a semiconductor device structure is provided, comprising: a substrate; a first insulating layer located above the substrate; a conductive pillar located above the substrate and embedded in the first insulating layer; a conductive via structure connected to an upper surface of the conductive pillar, wherein the conductive via structure has a first elongated shape in a first top view angle; and a wire located above the conductive via structure, wherein the wire has a second elongated shape in a second top view angle of the conductive via structure and the wire.

[0012] According to one embodiment of the present invention, in a third top view angle of the conductive through-hole structure and the conductive column, a first major axis of the conductive through-hole structure is parallel to a second major axis of the conductor.

[0013] According to one embodiment of the present invention, it further includes: a second insulating layer located on the first insulating layer and surrounding the conductive via structure.

[0014] According to one embodiment of the present invention, the conductive pillar is wider than the conductive through-hole structure.

[0015] According to one embodiment of the present invention, the conductive column is wider than the wire. Attached Figure Description

[0016] FIG. 1A , FIG. 1B , FIG. 1C and FIG. 1D The diagram shows cross-sectional schematics of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0017] FIG. 1C-1 Illustrations based on some embodiments FIG. 1C A top view of the structure of a semiconductor device.

[0018] FIG. 1D-1 Illustrations based on some embodiments FIG. 1D A top view of the structure of a semiconductor device.

[0019] FIG. 2A , FIG. 2B , FIG. 2C and FIG. 2D The diagram shows cross-sectional schematics of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0020] FIG. 2C-1 Illustrations based on some embodiments FIG. 2C A top view of the structure of a semiconductor device.

[0021] FIG. 2D-1Illustrations based on some embodiments FIG. 2D A top view of the structure of a semiconductor device.

[0022] FIG. 3A , FIG. 3B , FIG. 3C , FIG. 3D , FIG. 3E and FIG. 3F Cross-sectional views are shown of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0023] FIG. 3E-1 Illustrations based on some embodiments FIG. 3E A top view of the structure of a semiconductor device.

[0024] FIG. 3F-1 Illustrations based on some embodiments FIG. 3F A top view of the structure of a semiconductor device.

[0025] FIG. 4A , FIG. 4B , FIG. 4C , FIG. 4D and FIG. 4E The diagram shows cross-sectional schematics of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0026] FIG. 4D-1 Illustrations based on some embodiments FIG. 4D A top view of the structure of a semiconductor device.

[0027] FIG. 4E-1 Illustrations based on some embodiments FIG. 4E A top view of the structure of a semiconductor device.

[0028] FIG. 5A , FIG. 5B , FIG. 5C , FIG. 5D and FIG. 5E The diagram shows cross-sectional schematics of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0029] FIG. 5D-1 Illustrations based on some embodiments FIG. 4D A top view of the structure of a semiconductor device.

[0030] FIG. 5E-1 Illustrations based on some embodiments FIG. 4E A top view of the structure of a semiconductor device.

[0031] FIG. 6 A cross-sectional schematic diagram of a packaging structure according to some embodiments is shown.

[0032] The attached figures are labeled as follows:

[0033] 10: Rewiring Structure

[0034] 100, 200, 300, 400, 500: Semiconductor device structure

[0035] 110: Base

[0036] 112: Semiconductor substrate

[0037] 114: Internal Connection Structure

[0038] 116: Joint Pad

[0039] 116a, 120a, 130a, 142, 160b1, 180b1, 614: Upper surface

[0040] 118: Passivation protective layer

[0041] 118a, 122a: Opening

[0042] 120, 150, 170, 190: Insulation layer

[0043] 122, 124: Membrane layer

[0044] 130,632: Conductive pillars

[0045] 130b: Sidewall

[0046] 132,162,182,212: Seed layer

[0047] 134, 164, 184, 214: Conductive layer

[0048] 140: Molding layer

[0049] 150a: Insulation material layer

[0050] 150a1,152b,152u,S2: Upper part

[0051] 150a2,152a,152l,S1: lower part

[0052] 152, 172, 192: Holes

[0053] 152s: Inner wall

[0054] 160, 180, 210: Conductive structure

[0055] 160a, 180a, 210a: Conductive through-hole structure

[0056] 160a1: Bottom section

[0057] 160as,S: Sidewall

[0058] 160b, 180b, 210b: Conductor

[0059] 600: Package structure

[0060] 610: Line base

[0061] 612: Lower surface

[0062] 620, 634, 650, 680: Solder balls

[0063] 630: Package

[0064] 640: Chip

[0065] 660, 720, 730: Base coat

[0066] 670: Structure containing chips

[0067] 690: Ring structure

[0068] 710: Top Cover

[0069] 740, 750: Adhesive layer

[0070] 760: Thermal conductive layer

[0071] A1, A2, A3: Major axis

[0072] L1: Length

[0073] R: Groove

[0074] R1: Inner wall

[0075] T1, T2, T3, T4: Thickness

[0076] W1: Width

[0077] θ1,θ2,θ1',θ2': Angles Detailed Implementation

[0078] The following disclosure provides many different embodiments or examples to implement different features of the present invention. The following disclosure provides specific examples of the various components and their arrangements to simplify the present invention. Of course, these are merely illustrative examples and are not intended to define the present invention. For example, if the following disclosure describes forming a first feature on or above a second feature, it indicates that it includes embodiments where the first and second feature are in direct contact, and also includes embodiments where additional feature components may be formed between the first and second feature components, so that the first and second feature components may not be in direct contact. Furthermore, reference numerals and / or text are repeated in various examples of the present invention. This repetition is for simplification and clarity, and not to specify the relationships between the various embodiments and / or configurations discussed.

[0079] Furthermore, spatial terms such as "below," "under," "down," "above," and "upper" are used here to readily express the relationship between the device or feature shown in the accompanying drawings and other devices or features. These spatial terms cover not only the orientation shown in the drawings but also different orientations of the device during use or operation. The device may have different orientations (rotated 90 degrees or other orientations), and the spatial symbols used herein also have corresponding explanations.

[0080] The use of the term "substantially," such as "substantially flat" or "substantially coplanar," in this description will be understood by those skilled in the art. In some embodiments, the adjective "substantially" may be omitted. Where applicable, the term "substantially" may also include embodiments with words such as "entire," "completely," or "all." Where applicable, the term "substantially" may also relate to 90% or higher, such as 95% or higher, particularly 99% or higher, including 100%. Furthermore, the terms "substantially parallel" or "substantially perpendicular" are interpreted as not excluding minor deviations from a specific arrangement, such as a deviation of no more than 10°. The word "substantially" does not exclude "complete," for example, a composition "substantially free of" Y may be completely free of Y.

[0081] The term "about" can vary across different technologies and is within the range of deviations understood by a person skilled in the art. The term "about" in relation to a specific distance or size should be interpreted as not excluding minor deviations from the specific distance or size, and may include, for example, deviations up to 10%, but the invention is not limited thereto. The term "about" in relation to the numerical value x can refer to x ± 5 or 10%.

[0082] The following describes some embodiments of the present invention. Additional operational steps may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or omitted. Additional features may be added to the semiconductor device structure. Some of the features described below may be replaced or omitted for different embodiments. Although some embodiments are described with operation in a specific order, these operations may be performed in another logical order.

[0083] Other features and processes may also be included in this invention. For example, a test structure may be included to assist in the acceptance testing of a three-dimensional package or a three-dimensional integrated circuit device. This test structure may include, for example, multiple test pads formed in a redistribution layer or on a substrate, enabling testing of the three-dimensional package or three-dimensional integrated circuit device, using probes and / or probe cards, and similar functions. The acceptance testing can be performed on intermediate-stage structures as well as on the final structure. Furthermore, the structures and methods disclosed herein can be combined with intermediate acceptance testing methods incorporating known-good dies to increase yield and reduce costs.

[0084] FIG. 1A , FIG. 1B , FIG. 1C and FIG. 1D This diagram illustrates cross-sectional schematics of various stages of a process for forming a semiconductor device structure, according to some embodiments. FIG. 1A As shown, according to some embodiments, a substrate 110, an insulating layer 120, a conductive pillar 130, and a molding layer 140 are provided.

[0085] According to some embodiments, substrate 110 includes a semiconductor substrate 112, devices, an internal interconnect structure 114, a bonding pad 116, and a passivation layer 118 located above the semiconductor substrate 112. For simplicity and clarity, these devices are not shown in the figures.

[0086] The semiconductor substrate 112 is made of an elemental semiconductor material (including silicon or germanium) and has a single-crystal, polycrystalline, or amorphous structure. In some other embodiments, the semiconductor substrate 112 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, alloy semiconductors (e.g., SiGe or GaAsP), or combinations thereof. The semiconductor substrate 112 may also include multilayer semiconductors, semiconductor-on-insulator (SOI) (e.g., silicon-on-insulator or germanium-on-insulator), or combinations thereof.

[0087] In some embodiments, the device is formed within and / or on the semiconductor substrate 112. Examples of various devices include active devices, passive devices, other suitable devices, or combinations thereof. Active devices may include transistors or diodes formed on the surface of the semiconductor substrate 112. Passive devices include resistors, capacitors, or other suitable passive devices.

[0088] For example, a transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET) or a complementary metal-oxide-semiconductor transistor (CMOS).

[0089] Complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel transistors, and / or n-channel field-effect transistors (PFETs / NFETs), etc. Various device components are formed using processes such as front-end (FEOL) semiconductor manufacturing processes. FEOL semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or combinations thereof.

[0090] In some embodiments, isolation components (not shown) are formed within a semiconductor substrate 112. The isolation components define active regions and electrically isolate various devices formed within and / or above the semiconductor substrate 112 in the active regions. In some embodiments, the isolation components include shallow trench isolation (STI) components, local oxidation of silicon (LOCOS) components, other suitable isolation components, or combinations thereof.

[0091] According to some embodiments, an internal connection structure 114 is formed above the device and the semiconductor substrate 112. According to some embodiments, the internal connection structure 114 includes a dielectric layer, a circuit layer, and a conductive via. According to some embodiments, the circuit layer and the conductive via are located within the dielectric layer. According to some embodiments, the conductive via is electrically connected between the circuit layer and the device.

[0092] The dielectric layer is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)) or a combination thereof.

[0093] Alternatively, according to some embodiments, the dielectric layer comprises a low-k-value material or a porous dielectric material, having a k-value lower than that of silicon oxide, or lower than about 3.0 or about 2.5. According to some embodiments, the circuit layer and conductive vias are made of conductive materials, such as metals (e.g., copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0094] According to some embodiments, bonding pad 116 is formed above the internal connection structure 114. According to some embodiments, bonding pad 116 is electrically connected to the wiring layer and conductive vias of the internal connection structure 114. According to some embodiments, bonding pad 116 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0095] According to some embodiments, a passivation sheath 118 is located above the inner connection structure 114 and the bonding pad 116. According to some embodiments, the passivation sheath 118 has an opening 118a. According to some embodiments, the opening 118a exposes the upper surface 116a of the bonding pad 116. According to some embodiments, the passivation sheath 118 is made of a dielectric material containing a nitride material (e.g., silicon nitride).

[0096] According to some embodiments, an insulating layer 120 and a conductive pillar 130 are formed above a substrate 110. According to some embodiments, the conductive pillar 130 is embedded within the insulating layer 120. According to some embodiments, the upper surface 130a of the conductive pillar 130 is exposed outside the insulating layer 120.

[0097] According to some embodiments, the insulating layer 120 includes film layers 122 and 124. According to some embodiments, the conductive pillar 130 includes a seed layer 132 and a conductive layer 134. According to some embodiments, film layer 122 is formed over substrate 110. According to some embodiments, film layer 122 has an opening 122a. According to some embodiments, opening 122a exposes the upper surface 116a of bonding pad 116.

[0098] According to some embodiments, a seed layer 132 is formed over the film layer 122 and over the upper surface 116a of the bonding pad 116. According to some embodiments, a conductive layer 134 is formed over the seed layer 132. According to some embodiments, the film layer 124 is formed over the film layer 122 and surrounds the conductive pillar 130.

[0099] According to some embodiments, the insulating layer 120 is made of a dielectric material, such as a polymer (e.g., polyimide or the like). According to some embodiments, the seed layer 132 is made of a conductive material such as a metal or alloy (e.g., TiCu). According to some embodiments, the conductive layer 134 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0100] According to some embodiments, the molding layer 140 surrounds the substrate 110, the insulating layer 120, and the conductive pillar 130. In some embodiments, the upper surfaces 142, 120a, and 130a of the molding layer 140, the insulating layer 120, and the conductive pillar 130 are substantially flush with each other.

[0101] According to some embodiments, the formation of the molding layer 140 includes forming a molding material layer (not shown) over and around the substrate 110, the insulating layer 120, and the conductive pillar 130; removing the molding material layer over the insulating layer 120 and the conductive pillar 130 using a polishing process; and performing a cleaning process on the conductive pillar 130 to remove oxides from the upper surface 130a of the conductive pillar 130.

[0102] like FIG. 1A As shown, according to some embodiments, an insulating material layer 150a is formed over the insulating layer 120, the conductive pillar 130, and the molding layer 140. According to some embodiments, the insulating material layer 150a is made of a photoresist material, such as a negative photoresist material.

[0103] According to some embodiments, an insulating material layer 150a is formed using a coating process. Then, according to some embodiments, the insulating material layer 150a is subjected to a baking process. According to some embodiments, the baking process temperature is in the range of approximately 110°C to 120°C. According to some embodiments, the baking process time is in the range of approximately 2 minutes to 5 minutes.

[0104] According to some embodiments, due to the high process temperature of the soft baking process, the upper part 150a1 and the lower part 150a2 of the insulating material layer 150a harden at different speeds, resulting in the upper part 150a1 and the lower part 150a2 having different material properties.

[0105] For example, according to some embodiments, the insulating material layer 150a is made of a negative photoresist material, and after a soft bake process, the upper part 150a1 has a lower photoresist sensitizer concentration than the lower part 150a2.

[0106] like FIG. 1A and FIG. 1B As shown, according to some embodiments, the insulating material layer 150a above the conductive pillar 130 is partially removed to form a hole 152. According to some embodiments, the remaining insulating material layer 150a forms the insulating material layer 150. According to some embodiments, the hole 152 exposes the upper surface 130a of the conductive pillar 130.

[0107] According to some embodiments, the hole 152 has an inner wall 152s. According to some embodiments, the inner wall 152s has a lower portion 152a and an upper portion 152b. According to some embodiments, the lower portion 152a is located between the upper portion 152b and the conductive pillar 130.

[0108] According to some embodiments, the lower portion 152a is steeper than the upper portion 152b. According to some embodiments, the lower portion 152a of the inner wall 152s is substantially perpendicular to the upper surface 130a of the conductive pillar 130.

[0109] According to some embodiments, the angle θ1 between the lower portion 152a of the inner wall 152s and the upper surface 130a of the conductive pillar 130 is approximately in the range of 88 degrees to 92 degrees. According to some embodiments, the angle θ1 is approximately 90 degrees.

[0110] According to some embodiments, the angle θ2 between the lower portion 152a and the upper portion 152b of the inner wall 152s is approximately in the range of 120 degrees to 170 degrees. According to some embodiments, the removal process includes a photolithography process.

[0111] According to some embodiments, since the upper portion 150a1 of the insulating material layer 150a has a lower photoresist sensitizer concentration than the lower portion 150a2 of the insulating material layer 150a, the upper portion 150a1 is easier to remove than the lower portion 150a2 in the photolithography process. Therefore, according to some embodiments, the upper portion 152u of the hole 152 in the upper portion 150a1 is wider than the lower portion 152l of the hole 152 in the lower portion 150a2.

[0112] According to some embodiments, the (wider) upper portion 152u can facilitate the formation of a seed layer within the hole 152 and above the upper surface 130a of the conductive pillar 130 using a sputtering process.

[0113] Subsequently, according to some embodiments, the insulating material layer 150 is subjected to a curing process. According to some embodiments, the process temperature of the curing process is in the range of approximately 210°C to 250°C.

[0114] Subsequently, according to some embodiments, a slag removal process is performed to remove residues from the conductive pillar 130. According to some embodiments, the slag removal process includes an etching process, such as a plasma etching process.

[0115] FIG. 1C-1 Illustrations based on some embodiments FIG. 1C A top view of the structure of a semiconductor device. FIG. 1C The following is shown according to some embodiments. FIG. 1C-1 A cross-sectional schematic diagram of the semiconductor device structure along section I-I'. (See diagram for reference.) FIG. 1C and FIG. 1C-1 As shown, according to some embodiments, a conductive structure 160 is formed within the hole 152 and above the insulating layer 150. For simplicity, FIG. 1C-1 Only the conductive pillar 130 and conductive structure 160 according to some embodiments are shown.

[0116] According to some embodiments, the conductive structure 160 includes a conductive via structure 160a and a wire 160b. According to some embodiments, the conductive via structure 160a is formed within a hole 152. According to some embodiments, the conductive via structure 160a passes through the insulating layer 150 and connects to the conductive pillar 130. According to some embodiments, the wire 160b is formed above the conductive via structure 160a and the insulating layer 150.

[0117] According to some embodiments, the conductive via structure 160a has a sidewall S. According to some embodiments, the sidewall S has a lower portion S1 and an upper portion S2. According to some embodiments, the lower portion S1 is located between the upper portion S2 and the conductive pillar 130.

[0118] According to some embodiments, the lower portion S2 is steeper than the upper portion S1. According to some embodiments, the lower portion S2 is substantially perpendicular to the upper surface 130a of the conductive pillar 130.

[0119] According to some embodiments, the angle θ1' between the lower portion S1 and the upper surface 130a of the conductive pillar 130 is approximately in the range of 88 degrees to 92 degrees. According to some embodiments, the angle θ1' is approximately 90 degrees. According to some embodiments, the angle θ2' between the lower portion S1 and the upper portion S2 is approximately in the range of 120 degrees to 170 degrees.

[0120] According to some embodiments, based on simulation results, if the angle θ1' is approximately 90 degrees, cracks caused by the difference in the coefficients of thermal expansion between the conductive via structure 160a and the insulating layer 150 can be prevented.

[0121] According to some embodiments, the conductive structure 160 includes a seed layer 162 and a conductive layer 164. According to some embodiments, the seed layer 162 is formed over the upper surface 130a of the insulating layer 150 and the conductive pillar 130. According to some embodiments, the conductive layer 164 is formed over the seed layer 162.

[0122] According to some embodiments, the seed layer 162 is made of a conductive material, such as a metal or alloy (e.g., TiCu). According to some embodiments, the conductive layer 164 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0123] like FIG. 1D As shown, according to some embodiments, an insulating layer 170 is formed over the insulating layer 150 and the conductor 160b. According to some embodiments, the insulating layer 170 has holes 172 exposing the conductor 160b. According to some embodiments, the insulating layer 170 is made of a polymeric material, such as a photoresist material (e.g., a negative photoresist material), polyimide, or the like.

[0124] FIG. 1D-1 Illustrations based on some embodiments FIG. 1D A top view of the structure of a semiconductor device. FIG. 1D The following is shown according to some embodiments. FIG. 1D-1 A cross-sectional schematic diagram of the semiconductor device structure along section I-I'. (See diagram for reference.) FIG. 1D and FIG. 1D-1 As shown, according to some embodiments, a conductive structure 180 is formed within the hole 172 and above the insulating layer 170.

[0125] According to some embodiments, the conductive structure 180 includes a conductive via structure 180a and a wire 180b. For simplicity, FIG. 1D-1 Only the conductive pillar 130, conductive structure 160, and conductive through-hole structure 180a according to some embodiments are shown.

[0126] According to some embodiments, a conductive via structure 180a is formed within the hole 172. According to some embodiments, the conductive via structure 180a passes through the insulating layer 170 and is connected to the wire 160b. According to some embodiments, the wire 180b is formed above the conductive via structure 180a and the insulating layer 170.

[0127] According to some embodiments, the conductive structure 180 includes a seed layer 182 and a conductive layer 184. According to some embodiments, the seed layer 182 is formed above the upper surface 160b1 of the insulating layer 170 and the conductor 160b. According to some embodiments, the conductive layer 184 is formed above the seed layer 182.

[0128] According to some embodiments, the seed layer 182 is made of a conductive material, such as a metal or alloy (e.g., TiCu). According to some embodiments, the conductive layer 184 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0129] like FIG. 1D As shown, according to some embodiments, an insulating layer 190 is formed over the insulating layer 170 and the conductor 180b. According to some embodiments, the insulating layer 190 has holes 192 exposing the conductor 180b. According to some embodiments, the insulating layer 190 is made of a polymeric material, such as a photoresist material (e.g., a negative photoresist material), polyimide, or the like.

[0130] like FIG. 1D and FIG. 1D-1 As shown, according to some embodiments, a conductive structure 210 is formed within the aperture 192 and above the insulating layer 190. According to some embodiments, the conductive structure 210 includes a conductive via structure 210a and a wire 210b. According to some embodiments, the conductive via structure 210a is formed within the aperture 192.

[0131] According to some embodiments, the conductive via structure 210a passes through the insulating layer 190 and connects to the conductor 180b. According to some embodiments, the conductor 210b is formed above the conductive via structure 210a and the insulating layer 190. According to some embodiments, the insulating layers 150, 170, and 190, the conductive via structures 160a, 180a, and 210a, and the conductors 160b, 180b, and 210b together form the redistribution structure 10.

[0132] According to some embodiments, the conductive structure 210 includes a seed layer 212 and a conductive layer 214. According to some embodiments, the seed layer 212 is formed above the upper surface 180b1 of the insulating layer 190 and the conductor 180b. According to some embodiments, the conductive layer 214 is formed above the seed layer 212.

[0133] According to some embodiments, the average width of the conductive via structure 160a is less than or equal to the average width of the conductive via structure 180a. According to some embodiments, the average width of the conductive via structure 180a is less than or equal to the average width of the conductive via structure 210a.

[0134] According to some embodiments, the seed layer 212 is made of a conductive material, such as a metal or alloy (e.g., TiCu). According to some embodiments, the conductive layer 214 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof. According to some embodiments, in this step, a semiconductor device structure 100 is substantially formed.

[0135] FIG. 2A ,FIG. 2B , FIG. 2C and FIG. 2D This diagram illustrates cross-sectional schematics of various stages in the process of forming a semiconductor device structure according to some embodiments. FIG. 2A As shown, according to some embodiments, FIG. 1A The steps are to form a substrate 110, an insulating layer 120, a conductive pillar 130, a molding layer 140, and an insulating material layer 150a.

[0136] like FIG. 2B As shown, according to some embodiments, the insulating material layer 150a above the conductive pillar 130 is partially removed to form a hole 152. According to some embodiments, the remaining insulating material layer 150a forms an insulating layer 150. According to some embodiments, the hole 152 exposes the upper surface 130a of the conductive pillar 130.

[0137] FIG. 2C-1 Illustrations based on some embodiments FIG. 2C A top view of the structure of a semiconductor device. FIG. 2C The following is shown according to some embodiments. FIG. 2C-1 A cross-sectional schematic diagram of the semiconductor device structure with section line I-I' in the figure.

[0138] like FIG. 2C and FIG. 2C-1 As shown, according to some embodiments, FIG. 1C The steps are as follows to form the conductive structure 160. For simplicity, FIG. 2C-1 Only the conductive pillar 130 and conductive structure 160 according to some embodiments are shown.

[0139] like FIG. 1C-1 and FIG. 2C-1 As shown, FIG. 2C-1 The shape of the conductive pillar 130 and the conductive through-hole structure 160a are similar to FIG. 1C-1 The differences. According to some embodiments, FIG. 2C-1 The conductive column 130 has an elongated shape (or an elliptical shape).

[0140] According to some embodiments, FIG. 2C-1 The conductive via structure 160a has an elongated shape (or an elliptical shape). For example... FIG. 2C-1 As shown, according to some embodiments, the major axis A1 of the conductive via structure 160a is substantially parallel to the major axis A2 of the conductive pillar 130.

[0141] In some embodiments, the difference between the width Wl and the length Ll of the conductive via structure 160a is approximately in the range of 0.6 μm to 5 μm. In some embodiments, the ratio of the width W1 to the length L1 is approximately in the range of 1 to 5.

[0142] According to some embodiments, since both the conductive pillar 130 and the conductive through-hole structure 160a have an elongated shape, the contact area between the conductive pillar 130 and the conductive through-hole structure 160a is increased, thereby preventing cracks between the conductive pillar 130 and the conductive through-hole structure 160a.

[0143] According to some embodiments, since the conductive pillar 130 has an elongated shape, the contact area between the conductive pillar 130 and the insulating layer 150 is increased, thus preventing cracks between the conductive pillar 130 and the insulating layer 150. Therefore, according to some embodiments, the reliability of the semiconductor device structure having the conductive pillar 130 and the conductive via structure 160a is improved.

[0144] FIG. 2D-1 Illustrations based on some embodiments FIG. 2D A top view of the structure of a semiconductor device. FIG. 2D The following is shown according to some embodiments. FIG. 2D-1 A cross-sectional schematic diagram of the semiconductor device structure along section I-I'. (See diagram for reference.) FIG. 2D and FIG. 2D-1 As shown, according to some embodiments, FIG. 1D The steps are to form an insulating layer 170, a conductive via structure 180a, a wire 180b, an insulating layer 190, a conductive via structure 210a, and a wire 210b.

[0145] For the sake of simplicity, FIG. 2D-1 Only the conductive pillar 130, conductive structure 160, and conductive via structure 180a according to some embodiments are shown. According to some embodiments, insulating layers 150, 170, and 190, conductive via structures 160a, 180a, and 210a, and conductors 160b, 180b, and 210b together form a redistribution structure 10. According to some embodiments, in this step, a semiconductor device structure 200 is substantially formed.

[0146] FIG. 3A , FIG. 3B , FIG. 3C , FIG. 3D , FIG. 3E and FIG. 3F This diagram illustrates cross-sectional schematics of various stages in the process of forming a semiconductor device structure according to some embodiments. FIG. 3A As shown, according to some embodiments, FIG. 1A The steps are to form a substrate 110, an insulating layer 120, conductive pillars 130, and a molding layer 140. According to some embodiments, a groove R exists between the film layer 124 of the insulating layer 120 and the conductive pillars 130.

[0147] like FIG. 3BAs shown, according to some embodiments, an insulating material layer 150a is formed above the insulating layer 120 and the conductive pillar 130, and within the groove R. Then, according to some embodiments, a soft-bake process is performed on the insulating material layer 150a. According to some embodiments, the process temperature of the soft-bake process is approximately in the range of 100°C to 120°C.

[0148] like FIG. 3C As shown, according to some embodiments, the insulating material layer 150a above the conductive pillar 130 is partially removed to form a hole 152. According to some embodiments, the remaining insulating material layer 150a forms the insulating material layer 150.

[0149] According to some embodiments, the hole 152 is wider than the conductive pillar 130. According to some embodiments, the hole 152 exposes the upper surface 130a and sidewall 130b of the conductive pillar 130, as well as a portion of the insulating layer 120.

[0150] Subsequently, according to some embodiments, such as FIG. 3D As shown, the insulating layer 150 undergoes a curing process. According to some embodiments, the curing process temperature is approximately in the range of 210°C to 250°C.

[0151] Subsequently, according to some embodiments, such as FIG. 3D As shown, a slag removal process is performed to remove residues from the conductive pillar 130. According to some embodiments, the slag removal process includes an etching process, such as plasma etching. According to some embodiments, the slag removal process removes portions of the insulating layers 120 and 150.

[0152] FIG. 3E-1 Illustrations based on some embodiments FIG. 3E A top view of the structure of a semiconductor device. FIG. 3E The following is shown according to some embodiments. FIG. 3E-1 A cross-sectional schematic diagram of the semiconductor device structure with section line I-I' in the figure.

[0153] like FIG. 3E and FIG. 3E-1 As shown, according to some embodiments, FIG. 1C The steps are as follows to form the conductive structure 160. For simplicity, FIG. 3E-1 Only the conductive pillar 130 and conductive structure 160 according to some embodiments are shown.

[0154] like FIG. 1C-1 and FIG. 3E-1 According to some embodiments, FIG. 3E-1 The shapes of the conductive via structure 160a and the wire 160b are different. FIG. 1C-1 The shape of the conductive via structure 160a and the wire 160b. According to some embodiments, FIG. 3E-1The conductor 160b has a strip shape (or an oval shape). According to some embodiments, FIG. 3E-1 The conductive via structure 160a has an elongated shape (or an elliptical shape).

[0155] like FIG. 3E-1 As shown, according to some embodiments, the major axis A1 of the conductive via structure 160a is substantially parallel to the major axis A3 of the conductor 160b. According to some embodiments, the conductive via structure 160a is wider than the conductive pillar 130. According to some embodiments, the conductor 160b is wider than the conductive pillar 130.

[0156] According to some embodiments, since both the conductive via structure 160a and the wire 160b have an elongated shape, the contact area between the conductive via structure 160a and the wire 160b is increased, thus preventing cracks between them. Therefore, according to some embodiments, the reliability of the semiconductor device structure having the conductive via structure 160a and the wire 160b is improved.

[0157] In some embodiments, the bottom portion 160a1 of the conductive via structure 160a is embedded within the insulating layer 120. According to some embodiments, the bottom portion 160a1 of the conductive via structure 160a is in direct contact with the sidewall 130b of the conductive pillar 130.

[0158] According to some embodiments, the conductive pillar 130 extends into the conductive via structure 160a, which increases the contact area between the conductive pillar 130 and the conductive via structure 160a, preventing cracks between them. Therefore, according to some embodiments, the reliability of the semiconductor device structure having the conductive via structure 160a is improved.

[0159] FIG. 3F-1 Illustrations based on some embodiments FIG. 3F A top view of the structure of a semiconductor device. FIG. 3F The following is shown according to some embodiments. FIG. 3F-1 A cross-sectional schematic diagram of the semiconductor device structure with section line I-I' in the figure.

[0160] like FIG. 3F and FIG. 3F-1 As shown, according to some embodiments, FIG. 1D The steps are to form an insulating layer 170, a conductive via structure 180a, a wire 180b, an insulating layer 190, a conductive via structure 210a, and a wire 210b.

[0161] For the sake of simplicity, FIG. 3F-1Only the conductive pillar 130, conductive structure 160, and conductive via structure 180a according to some embodiments are shown. According to some embodiments, insulating layers 150, 170, and 190, conductive via structures 160a, 180a, and 210a, and conductors 160b, 180b, and 210b together form a redistribution structure 10. According to some embodiments, in this step, a semiconductor device structure 300 is substantially formed.

[0162] FIG. 4A , FIG. 4B , FIG. 4C , FIG. 4D and FIG. 4E This diagram illustrates cross-sectional schematics of various stages in the process of forming a semiconductor device structure according to some embodiments. FIG. 4A As shown, according to some embodiments, FIG. 3A and FIG. 3B The steps involve forming a substrate 110, an insulating layer 120, conductive pillars 130, a molding layer 140, and an insulating material layer 150a. According to some embodiments, FIG. 4A The thickness T2 of the insulating material layer 150a is greater than FIG. 3B The thickness T1 of the insulating material layer is 150a.

[0163] like FIG. 4B As shown, according to some embodiments, the insulating material layer 150a above the conductive pillar 130 is partially removed to form a hole 152.

[0164] like FIG. 4B and FIG. 4C As shown, according to some embodiments, the insulating material layer 150a is subjected to a curing process.

[0165] Subsequently, according to some embodiments, such as FIG. 4C As shown, a slag removal process is performed to remove residue from the conductive pillar 130. According to some embodiments, the slag removal process also removes portions of the insulating layers 120 and 150 to widen the holes 152 and grooves R. According to some embodiments, after the slag removal process, the remaining insulating material layer 150a forms the insulating layer 150. According to some embodiments, the insulating layer 150 is thinned after the slag removal process.

[0166] According to some embodiments, the slag removal process includes an isotropic etching process. According to some embodiments, after the isotropic etching process, the roughness of the inner wall 152a of the hole 152 is greater than the roughness of the upper surface 130a of the conductive pillar 130.

[0167] According to some embodiments, after an isotropic etching process, the roughness of the inner wall R1 of the groove R is greater than the roughness of the upper surface 130a of the conductive pillar 130. According to some embodiments, the inner wall R1 is a curved inner wall.

[0168] FIG. 4D-1 Illustrations based on some embodiments FIG. 4D A top view of the structure of a semiconductor device. FIG. 4D The following is shown according to some embodiments. FIG. 4D-1 A cross-sectional schematic diagram of the semiconductor device structure with section line I-I' in the figure.

[0169] like FIG. 4D and FIG. 4D-1 As shown, according to some embodiments, FIG. 1C The steps are as follows to form the conductive structure 160. For simplicity, FIG. 4D-1 Only the conductive pillar 130 and conductive structure 160 according to some embodiments are shown.

[0170] like FIG. 1C-1 and FIG. 4D-1 As shown, according to some embodiments, FIG. 4D-1 The shapes of the conductive via structure 160a and the wire 160b are different. FIG. 1C-1 The shape of the conductive via structure 160a and the wire 160b. According to some embodiments, FIG. 4D-1 The conductor 160b has a strip shape (or an oval shape). According to some embodiments, FIG. 4D-1 The conductive via structure 160a has an elongated shape (or an elliptical shape).

[0171] like FIG. 4D-1 As shown, according to some embodiments, the major axis A1 of the conductive via structure 160a is substantially parallel to the major axis A3 of the conductor 160b. According to some embodiments, the conductive via structure 160a is wider than the conductive pillar 130. According to some embodiments, the conductor 160b is wider than the conductive pillar 130.

[0172] In some embodiments, the bottom portion 160a1 of the conductive via structure 160a is embedded within the insulating layer 120. According to some embodiments, the bottom portion 160a1 of the conductive via structure 160a is in direct contact with the sidewall 130b of the conductive pillar 130.

[0173] According to some embodiments, the conductive pillar 130 extends into the conductive via structure 160a. For example... FIG. 4D As shown, according to some embodiments, the conductive via structure 160a has curved sidewalls 160as.

[0174] FIG. 4E-1 Illustrations based on some embodiments FIG. 4E A top view of the structure of a semiconductor device. FIG. 4E The following is shown according to some embodiments. FIG. 4E-1 A cross-sectional schematic diagram of the semiconductor device structure with section line I-I' in the figure.

[0175] like FIG. 4E and FIG. 4E-1 As shown, proceed FIG. 1D The steps are as follows: to form an insulating layer 170, a conductive via structure 180a, a wire 180b, an insulating layer 190, a conductive via structure 210a, and a wire 210b. According to some embodiments. For simplicity, FIG. 4E-1 Only the conductive pillar 130, conductive structure 160, and conductive through-hole structure 180a according to some embodiments are shown.

[0176] According to some embodiments, insulating layers 150, 170, and 190, conductive via structures 160a, 180a, and 210a, and conductors 160b, 180b, and 210b together form a redistribution structure 10. According to some embodiments, in this step, a semiconductor device structure 400 is substantially formed.

[0177] FIG. 5A , FIG. 5B , FIG. 5C , FIG. 5D and FIG. 5E This diagram illustrates cross-sectional schematics of various stages in the process of forming a semiconductor device structure according to some embodiments. FIG. 5A As shown, according to some embodiments, FIG. 3A and FIG. 3B The steps involve forming a substrate 110, an insulating layer 120, conductive pillars 130, a molding layer 140, and an insulating material layer 150a. According to some embodiments, FIG. 5A The thickness T3 of the 150a insulating material layer is greater than FIG. 3B The thickness T1 of the insulating material layer is 150a.

[0178] According to some embodiments, after the baking process, the insulating material layer 150a is annealed to improve the adhesion between the insulating material layer 150a and the conductive pillar 130. According to some embodiments, the annealing temperature is higher than the baking temperature. According to some embodiments, the annealing temperature is in the range of approximately 130°C to 150°C.

[0179] like FIG. 5B As shown, according to some embodiments, the insulating material layer 150a above the conductive pillar 130 is partially removed to form a hole 152.

[0180] Because the annealing process improves the adhesion between the insulating material layer 150a and the conductive pillar 130, a portion of the insulating material layer 150a remains above the insulating layer 120 and the conductive pillar 130.

[0181] like FIG. 5CAs shown, according to some embodiments, the insulating material layer 150a undergoes a curing process. Then, as... FIG. 5C As shown, according to some embodiments, a portion of the insulating material layer 150a remaining above the insulating layer 120 and the conductive pillar 130 is removed. According to some embodiments, after the slag removal process, the remaining insulating material layer 150a forms the insulating layer 150.

[0182] In some embodiments, a portion of the insulating layer 150 remains within the groove R between the insulating layer 120 and the conductive pillar 130. According to some embodiments, the removal process includes a slag removal process. According to some embodiments, after the slag removal process, the insulating layer 150 is thinned. That is, according to some embodiments, the thickness T4 of the insulating layer 150 is less than... FIG. 5A or FIG. 5B The thickness T3 of the insulating material layer is 150a.

[0183] According to some embodiments, the slag removal process includes an isotropic etching process. According to some embodiments, after the isotropic etching process, the roughness of the inner wall 152a of the hole 152 is greater than the roughness of the upper surface 130a of the conductive pillar 130.

[0184] According to some embodiments, after an isotropic etching process, the roughness of the upper surface 120a of the insulating layer 120 is greater than the roughness of the upper surface 130a of the conductive pillar 130.

[0185] FIG. 5D-1 Illustrations based on some embodiments FIG. 5D A top view of the structure of a semiconductor device. FIG. 5D The following is shown according to some embodiments. FIG. 5D-1 A cross-sectional schematic diagram of the semiconductor device structure with section line I-I' in the figure.

[0186] like FIG. 5D and FIG. 5D-1 As shown, according to some embodiments, FIG. 1C The steps are as follows to form the conductive structure 160. For simplicity, FIG. 5D-1 Only the conductive pillar 130 and conductive structure 160 according to some embodiments are shown.

[0187] like FIG. 1C-1 and FIG. 5D-1 As shown, according to some embodiments, FIG. 5D-1 The shapes of the conductive via structure 160a and the wire 160b are different. FIG. 1C-1 The shape of the conductive via structure 160a and the wire 160b. According to some embodiments, FIG. 5D-1 The conductor 160b has a strip shape (or an oval shape). According to some embodiments, FIG. 5D-1The conductive via structure 160a has an elongated shape (or an elliptical shape).

[0188] like FIG. 5D-1 As shown, according to some embodiments, the major axis A1 of the conductive via structure 160a is substantially parallel to the major axis A3 of the conductor 160b. According to some embodiments, the conductive via structure 160a is wider than the conductive pillar 130. According to some embodiments, the conductor 160b is wider than the conductive pillar 130. FIG. 5D As shown, according to some embodiments, the entire conductive via structure 160a is located above the insulating layer 120.

[0189] FIG. 5E-1 Released according to some embodiments FIG. 5E A top view of the structure of a semiconductor device. FIG. 5E The following is shown according to some embodiments. FIG. 5E-1 A cross-sectional schematic diagram of the semiconductor device structure with section line I-I' in the figure.

[0190] like FIG. 5E and FIG. 5E-1 As shown, proceed FIG. 1D The steps are as follows: to form an insulating layer 170, a conductive via structure 180a, a wire 180b, an insulating layer 190, a conductive via structure 210a, and a wire 210b. According to some embodiments, for simplicity, FIG. 5E-1 Only the conductive pillar 130, conductive structure 160, and conductive through-hole structure 180a according to some embodiments are shown.

[0191] According to some embodiments, insulating layers 150, 170, and 190, conductive via structures 160a, 180a, and 210a, and conductors 160b, 180b, and 210b together form a redistribution structure 10. According to some embodiments, in this step, a semiconductor device structure 500 is substantially formed.

[0192] FIG. 6 A cross-sectional schematic diagram of a package structure 600 according to some embodiments is shown. For example... FIG. 6 As shown, according to some embodiments, the package structure 600 includes a circuit substrate 610, solder balls 620, a package body 630, a chip 640, solder balls 650, a base adhesive layer 660, a chip-containing structure 670, solder balls 680, a ring structure 690, a top cover 710, base adhesive layers 720 and 730, adhesive layers 740 and 750, and a thermally conductive layer 760.

[0193] According to some embodiments, the circuit substrate 610 includes an insulating layer (not shown) and a circuit structure (not shown) within the insulating layer. According to some embodiments, solder balls 620 are formed above the lower surface 612 of the circuit substrate 610. According to some embodiments, the solder balls 620 are electrically connected to the circuit structure of the circuit substrate 610.

[0194] According to some embodiments, the package 630 is bonded to the upper surface 614 of the circuit substrate 610. According to some embodiments, the package 630 is electrically connected to the circuit structure of the circuit substrate 610. According to some embodiments, the package 630 is similar to... FIG. 1D , FIG. 2D , FIG. 3F , FIG. 4E or FIG. 5E The semiconductor device structures are 100, 200, 300, 400 or 500, however the package 630 has two substrates 110.

[0195] According to some embodiments, the package 630 includes a substrate 110 of a semiconductor device structure 100, 200, 300, 400 or 500, an insulating layer 120, conductive pillars 130, a molding layer 140 and a redistribution structure 10.

[0196] According to some embodiments, the package 630 further includes conductive pillars 632 and solder balls 634. According to some embodiments, the conductive pillars 632 are formed above the redistribution structure 10. According to some embodiments, the solder balls 634 are connected between the conductive pillars 632 and the circuit substrate 610.

[0197] According to some embodiments, chip 640 is bonded to redistribution structure 10 via solder balls 650. According to some embodiments, an undercoat layer 660 is formed between redistribution structure 10 and chip 640.

[0198] According to some embodiments, the chip-containing structure 670 is bonded to the redistribution structure 10 via solder balls 680. According to some embodiments, a ring structure 690 is bonded to the redistribution structure 10 and surrounds the package 630 and the chip-containing structure 670. According to some embodiments, a top cover 710 is bonded to the ring structure 690.

[0199] According to some embodiments, solder balls 620, 634, 650, and 680 are made of metal or alloys thereof (e.g., tin alloys). According to some embodiments, conductive pillar 632 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0200] According to some embodiments, the base adhesive layer 660 is made of an insulating material, such as a polymer. According to some embodiments, the top cover 710 and the annular structure 690 are made of metal or alloy.

[0201] According to some embodiments, an adhesive layer 720 is formed between the circuit substrate 610 and the package 630. According to some embodiments, the adhesive layer 720 surrounds the conductor 210b, the conductive pillar 632, the solder ball 634, the chip 640, and the adhesive layer 660.

[0202] According to some embodiments, a primer layer 730 is formed between the circuit substrate 610 and the corresponding chip-containing structure 670. According to some embodiments, the primer layer 730 surrounds the corresponding solder balls 680. According to some embodiments, primer layers 720 and 730 are made of an insulating material, such as a polymer.

[0203] According to some embodiments, adhesive layer 740 is formed between annular structure 690 and circuit substrate 610. According to some embodiments, adhesive layer 750 is formed between annular structure 690 and top cover 710. According to some embodiments, adhesive layers 740 and 750 are made of adhesive material, such as polymer material.

[0204] According to some embodiments, a thermally conductive layer 760 is formed between the top cover 710 and the package 630. According to some embodiments, the thermally conductive layer 760 is made of a thermally conductive material (e.g., indium (In), tin (Sn)) or a suitable material with good thermal conductivity and thermal diffusivity. According to some embodiments, the material of the thermally conductive layer 760 has a thermal conductivity greater than or equal to 50 W / (m·K).

[0205] According to some embodiments, a method for forming a package structure 600 includes: bonding a package body 630 to a circuit substrate 610; forming an adhesive layer 720 between the circuit substrate 610 and the package body 630; bonding a chip-containing structure 670 to the circuit substrate 610; forming an adhesive layer 730 between the circuit substrate 610 and the chip-containing structure 670; bonding an annular structure 690 to the circuit substrate 610 via an adhesive layer 740; bonding a top cover 710 to the annular structure 690 and the package body 630 via an adhesive layer 750 and a thermally conductive layer 760; and forming solder balls 620 above a lower surface 612 of the circuit substrate 610. According to some embodiments, these steps are performed sequentially.

[0206] The processes and materials used to form semiconductor device structures 200, 300, 400 and 500 may be similar to or the same as the processes and materials used to form semiconductor device structure 100. FIG. 1A to FIG. 6 Components marked with the same or similar designations have the same or similar structure and materials. Therefore, their detailed descriptions will not be repeated here.

[0207] According to some embodiments, a semiconductor device structure and a method for forming the same are provided. This method (for forming the semiconductor device structure) forms an elongated conductive via structure to increase the contact area between the conductive via structure and the conductive pillar below it (or the conductor above it), thereby preventing cracks from forming between the conductive via structure and the conductive pillar below it (or the conductor above it).

[0208] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes: providing a substrate, a first insulating layer, and a conductive pillar located above the substrate. The conductive pillar is embedded within the first insulating layer, and its upper surface is exposed above the first insulating layer. The method further includes: forming a second insulating layer above the first insulating layer and the conductive pillar. The second insulating layer has a hole located above the upper surface of the conductive pillar. The method also includes: forming a conductive via structure within the hole and forming a conductive wire above the conductive via structure and the second insulating layer. In a first top view angle, the conductive via structure has a first elongated shape.

[0209] According to some embodiments, in a second top view of the conductive pillar, the conductive pillar has a second elongated shape. According to some embodiments, in a third top view of the conductive via structure and the conductive pillar, the first major axis of the conductive via structure is substantially parallel to the second major axis of the conductive pillar. According to some embodiments, the conductive via structure is wider than the conductive pillar. According to some embodiments, the holes in the second insulating layer expose one sidewall of the conductive pillar. According to some embodiments, the bottom portion of the conductive via structure is embedded within the first insulating layer. According to some embodiments, the bottom portion of the conductive via structure is in direct contact with the sidewall of the conductive pillar. According to some embodiments, in a cross-sectional view of the conductive via structure, the conductive via structure has curved sidewalls. According to some embodiments, forming the second insulating layer above the first insulating layer and the conductive pillar includes: forming an insulating material layer above the first insulating layer and the conductive pillar; partially removing the insulating material layer above the conductive pillar to form a hole; performing a curing process on the insulating material layer; and partially removing the insulating material layer to widen the hole, wherein the insulating material layer forms the second insulating layer after widening the hole. According to some embodiments, locally removing the insulating material layer to widen the aperture includes performing an isotropic etching process on the insulating material layer. According to some embodiments, after the isotropic etching process, the first roughness of the inner wall of the aperture is greater than the second roughness of the upper surface of the conductive pillar. According to some embodiments, after the isotropic etching process, the first roughness of the upper surface of the first insulating layer is greater than the second roughness of the upper surface of the conductive pillar. According to some embodiments, in a second top view of the conductive via structure and the conductor, the conductor has a second elongated shape, and the first major axis of the conductive via structure is substantially parallel to the second major axis of the conductor.

[0210] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes: providing a substrate, a first insulating layer, and a conductive pillar located above the substrate. The conductive pillar is embedded within the first insulating layer, and its upper surface is exposed above the first insulating layer. The method further includes: forming a second insulating layer above the first insulating layer and the conductive pillar. The second insulating layer has a hole exposing the upper surface of the conductive pillar. The hole has an inner wall with an upper portion and a lower portion, the lower portion being located between the upper portion and the conductive pillar, and the lower portion being steeper than the upper portion. The method also includes: forming a conductive via structure within the hole and forming a conductive wire above the conductive via structure and the second insulating layer.

[0211] According to some embodiments, the lower part of the inner wall is substantially perpendicular to the upper surface of the conductive pillar.

[0212] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first insulating layer located above the substrate. The semiconductor device structure includes a conductive pillar located above the substrate and embedded within the first insulating layer. The semiconductor device structure includes a second insulating layer located above the first insulating layer and the conductive pillar. The semiconductor device structure includes a conductive via structure passing through the second insulating layer and connected to the conductive pillar. In a first top view angle, the conductive via structure has a first elongated shape. The semiconductor device structure includes a conductive wire located above the conductive via structure and the second insulating layer.

[0213] According to some embodiments, in a second top view of the conductive via structure and the conductor, the conductor has a second elongated shape, and the first major axis of the conductive via structure is substantially parallel to the second major axis of the conductor. According to some embodiments, in a second top view of the conductive pillar, the conductive pillar has a second elongated shape. According to some embodiments, the conductive via structure is wider than the conductive pillar. According to some embodiments, the conductive pillar extends into the conductive via structure.

[0214] The foregoing provides a brief overview of the characteristic components of several embodiments of this utility model, enabling those skilled in the art to more readily understand the nature of this utility model. Anyone skilled in the art should understand that this utility model can be readily used as a basis for modifications or designs to other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. It will also be understood by anyone skilled in the art that equivalent structures described above do not depart from the spirit and scope of this utility model, and that modifications, substitutions, and refinements can be made without departing from its spirit and scope.

Claims

1. A semiconductor device structure, characterized in that, include: One base; A first insulating layer is located above the substrate; A conductive pillar is located above the substrate and embedded in the first insulating layer; A second insulating layer is located above the first insulating layer and the conductive pillar; A conductive via structure passes through the second insulating layer and is connected to the conductive pillar, wherein the conductive via structure has a first elongated shape in a first top view angle; as well as A wire is located above the conductive via structure and the second insulating layer.

2. The semiconductor device structure as described in claim 1, characterized in that, In a second top view of the conductive via structure and the conductor, the conductor has a second elongated shape, and a first major axis of the conductive via structure is parallel to a second major axis of the conductor.

3. The semiconductor device structure as described in claim 1, characterized in that, In a second top view, the conductive column has a second elongated shape.

4. The semiconductor device structure according to any one of claims 1-3, characterized in that, The conductive via structure is wider than the conductive pillar.

5. The semiconductor device structure as described in claim 4, characterized in that, The conductive pillar extends into the conductive through-hole structure.

6. A semiconductor device structure, characterized in that, include: One base; A first insulating layer is located above the substrate; A conductive pillar is located above the substrate and embedded in the first insulating layer; A conductive via structure is connected to an upper surface of the conductive pillar, wherein the conductive via structure has a first elongated shape in a first top view angle; as well as A wire is located above the conductive via structure, wherein the wire has a second elongated shape in a second top view of the conductive via structure and the wire.

7. The semiconductor device structure as described in claim 6, characterized in that, In a third top view of the conductive via structure and the conductive pillar, a first major axis of the conductive via structure is parallel to a second major axis of the conductor.

8. The semiconductor device structure as described in claim 6 or 7, characterized in that, Also includes: A second insulating layer is located on the first insulating layer and surrounds the conductive via structure.

9. The semiconductor device structure as described in claim 6 or 7, characterized in that, The conductive pillar is wider than the conductive via structure.

10. The semiconductor device structure as described in claim 6 or 7, characterized in that, The conductive column is wider than the wire.

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