Chip packaging structure and electronic equipment
By configuring an anti-electromigration barrier layer and a seed layer in the UBM layer, the problem of electromigration in conductive lines under high current density is solved, thereby improving the reliability of the chip.
Patent Information
- Application Number
- CN202520074932.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-13
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2035-01-13
AI Technical Summary
Under high current density, electromigration can easily occur in the conductive layer circuitry on the wafer, leading to open circuit failures and affecting chip reliability.
An anti-electromigration barrier layer, including an anti-electromigration barrier layer and a seed layer, is configured in the UBM layer, covering the conductive layer and connected to it through bumps to form a structure with strong anti-electromigration capability.
It effectively prevents electromigration of conductive lines under high current density, avoids open circuit faults, and improves chip reliability.
Smart Images
Figure CN223786534U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to chip packaging technical field especially, and relates to a chip packaging structure and electronic equipment. BACKGROUND
[0002] At present, in the chip integrated circuit (IC) packaging structure, the barrier layer of UBM (Under Bump Metallization, bump bottom metallization) layer can prevent atomic diffusion between the conductive layer circuit on the wafer and silicon or oxide in the process of high temperature processing.
[0003] In practical application, with the improvement of high-end chip integration, due to the high-speed signal demand of high-end chip, the upper limit of current required by the chip increases, which increases the current density of the conductive layer circuit on the wafer, so that the degree of electromigration of the conductive layer circuit on the wafer is aggravated, thereby leading to the chip prone to open circuit failure. Therefore, how to prevent the conductive layer circuit on the wafer from electromigration under high current density and lead to chip open circuit failure to improve the reliability of the chip has become a problem to be solved. SUMMARY
[0004] The utility model provides a kind of chip packaging structure and electronic equipment, can prevent the conductive layer circuit on wafer from electromigration under high current density, avoids the situation of open circuit failure, to improve the reliability of the chip.
[0005] The utility model discloses a chip packaging structure in the first aspect, the chip packaging structure includes:
[0006] Wafer, the target side of the wafer is provided with circuit slot;
[0007] Conductive layer, the conductive layer is filled in the circuit slot of the wafer;
[0008] UBM layer, the UBM layer includes anti-electromigration barrier layer and seed layer, the anti-electromigration barrier layer is covered on the conductive layer, and the seed layer is arranged on the side of the anti-electromigration barrier layer away from the conductive layer;
[0009] Bump, the bump is arranged on the side of the seed layer away from the anti-electromigration barrier layer.
[0010] As an optional implementation, in the first aspect of the utility model, the composition material of the anti-electromigration barrier layer includes: any one of tungsten, titanium tungsten, titanium nitride, tantalum and tantalum nitride.
[0011] As an optional implementation, in the first aspect of the utility model, the bump includes:
[0012] a first electroplated layer disposed on a side of the seed layer distal from the electromigration resistant barrier layer;
[0013] a second electroplated layer disposed on a side of the first electroplated layer distal from the seed layer.
[0014] As an optional implementation, in the first aspect of the utility model, the first electroplated layer is composed of palladium, and the second electroplated layer is composed of gold.
[0015] As an optional implementation, in the first aspect of the utility model, the seed layer is composed of any one of gold and silver.
[0016] As an optional implementation, in the first aspect of the utility model, the seed layer is composed of any one of copper, nickel and aluminum.
[0017] As an optional implementation, in the first aspect of the utility model, the seed layer is composed of palladium.
[0018] As an optional implementation, in the first aspect of the utility model, the chip packaging structure further comprises:
[0019] a passivation layer covering a target side of the wafer, wherein the passivation layer is provided with a bare area at a position corresponding to the conductive layer, and the electromigration resistant barrier layer covers the conductive layer through the bare area.
[0020] As an optional implementation, in the first aspect of the utility model, the conductive layer is composed of any one of aluminum and copper.
[0021] The second aspect of the utility model discloses an electronic device, which comprises a device main body and the chip packaging structure disclosed in the first aspect of the utility model.
[0022] Compared with the prior art, the utility model has the following beneficial effects:
[0023] The chip packaging structure provided by the utility model can prevent the conductive circuit on the wafer from electromigration under high current density by configuring the electromigration resistant barrier layer in the UBM layer, avoids the open circuit failure, and thus improves the reliability of the chip.
[0024] The electronic device provided by the utility model adopts the above chip packaging structure, can prevent the conductive circuit on the wafer from electromigration under high current density by configuring the electromigration resistant barrier layer in the UBM layer of the chip packaging structure, avoids the open circuit failure, and thus improves the reliability of the chip in the electronic device. BRIEF DESCRIPTION OF DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.
[0026] Figure 1 is a structural schematic diagram of a chip packaging structure disclosed by the embodiments of the present application.
[0027] Reference signs:
[0028] wafer 100, conductive layer 200, UBM layer 300, electromigration resistance barrier layer 301, seed layer 302, bump 400, first electroplating layer 401, second electroplating layer 402, passivation layer 500. DETAILED DESCRIPTION
[0029] In order to make the personnel in the technical field better understand the present application scheme, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0030] The terms "first", "second", etc. in the specification and claims of the present application and the above drawings are used to distinguish different objects, not to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or end including a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or optionally includes other steps or units inherent to the process, method, product or end.
[0031] In addition, the terms "mount", "set", "provided with", "connect", "connected" should be broadly understood. For example, it can be fixedly connected, detachably connected, or integrally configured; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two devices, elements or components. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0032] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all referring to a common set of embodiments. It is expressly understood that the embodiments described herein are merely examples from a great array of possible embodiments.
[0033] At present, in the chip packaging structure, the barrier layer of the UBM layer can prevent atomic diffusion between the conductive layer circuit on the wafer and silicon or oxide in the process of high temperature processing.
[0034] In practical application, with the improvement of the integration of high-end chips, due to the high-speed signal demand of high-end chips, the upper limit of the current required by the chip increases, so that the current density of the conductive layer circuit on the wafer increases, which causes the degree of electromigration of the conductive layer circuit on the wafer to increase, thereby causing the chip to easily appear open circuit failure. Therefore, how to prevent the conductive layer circuit on the wafer from appearing electromigration under high current density and causing chip open circuit failure to improve the reliability of the chip has become a problem to be solved.
[0035] To this end, the utility model discloses a kind of chip packaging structure and electronic equipment, can prevent the conductive layer circuit on wafer from electromigration under high current density, avoid the situation of appearing open circuit failure, thereby improve the reliability of chip.
[0036] As shown in Figure 1 The utility model discloses a kind of chip packaging structure, the chip packaging structure includes: wafer 100, conductive layer 200, UBM layer 300 and bump 400.Wafer 100 target side is equipped with circuit slot;Conductive layer 200 is filled in the circuit slot of wafer 100;UBM layer 300 includes anti-electromigration barrier layer 301 and seed layer 302, anti-electromigration barrier layer 301 is covered on conductive layer 200, seed layer 302 is set to the side of anti-electromigration barrier layer 301 away from conductive layer 200;Bump 400 is set to the side of seed layer 302 away from anti-electromigration barrier layer 301.
[0037] In the embodiment, wafer 100 is in target side (i.e. Figure 1The conductive layer 200 is filled in the circuit groove on the upper surface of the wafer 100, that is, the conductive layer 200 is a conductive circuit on the wafer 100. The electromigration-resistant barrier layer 301 of the UBM layer 300 covers the conductive layer 200, so that the lower surface of the electromigration-resistant barrier layer 301 is connected with the upper surface of the conductive layer 200. The seed layer 302 of the UBM layer 300 covers the electromigration-resistant barrier layer 301, so that the lower surface of the seed layer 302 is connected with the upper surface of the electromigration-resistant barrier layer 301. The bump 400 is arranged on the upper side of the seed layer 302, and the lower surface of the bump 400 is connected with the upper surface of the seed layer 302.
[0038] Further, in the preparation process of the packaging structure, the electromigration-resistant barrier layer 301, the seed layer 302 and the bump 400 are sequentially formed above the conductive layer 200, so that the structure of the conductive layer 200, the electromigration-resistant barrier layer 301, the seed layer 302 and the bump 400 is sequentially stacked from bottom to top. By arranging the seed layer 302 between the bump 400 and the electromigration-resistant barrier layer 301, a good conductive surface can be provided for the electroplating process of the metal of the bump 400, and the adhesion between the lower metal of the seed layer 302 and the metal layer of the bump 400 can be strengthened, preventing delamination, falling off or even cracking in the later process.
[0039] The electromigration-resistant barrier layer 301 adopts a metal with strong electromigration resistance, and the electromigration-resistant barrier layer 301 is arranged on the conductive layer 200, preventing the conductive layer 200 from electromigration under high current density, so as to ensure that the conductive circuit on the wafer 100 will not be open-circuit failure, thereby improving the reliability of the chip.
[0040] As can be seen, the chip packaging structure of the utility model can prevent the conductive circuit on the wafer 100 from electromigration under high current density by configuring the electromigration-resistant barrier layer 301 in the UBM layer 300, avoiding the open-circuit failure, thereby improving the reliability of the chip.
[0041] As shown in the figure, Figure 1 In an optional embodiment, the chip packaging structure further comprises a passivation layer 500, the passivation layer 500 covers the target side of the wafer 100, the passivation layer 500 is provided with an exposed area at the position corresponding to the conductive layer 200, and the electromigration-resistant barrier layer 301 covers the conductive layer 200 through the exposed area.
[0042] In this embodiment, the target side of the wafer 100 is covered with a passivation layer 500, and the passivation layer 500 is provided with an exposed area above the corresponding area of the conductive layer 200, so that the electromigration resistance barrier layer 301 can be formed on one side above the conductive layer 200 through the exposed area. The passivation layer 500 has the functions of preventing oxidation, corrosion, etc. Covering the passivation layer 500 on the surface of the wafer 100 can protect the surface of the wafer 100 from the external environment, prevent the wafer 100 from being oxidized, corroded and contaminated, etc., thereby improving the stability and reliability of the wafer 100.
[0043] In an optional embodiment, the composition of the conductive layer 200 includes any one of aluminum and copper.
[0044] In an optional embodiment, the composition of the electromigration resistance barrier layer 301 includes any one of titanium tungsten, tungsten, titanium nitride, tantalum and tantalum nitride.
[0045] In this optional embodiment, the material properties of tungsten, titanium nitride, tantalum and titanium nitride are introduced first. Table 1 below is a comparison table of the related material properties:
[0046] Table 1:
[0047]
[0048]
[0049] As can be seen from Table 1, titanium (Ti) has weak electromigration resistance and relatively high resistivity, which is only suitable for application in low-end chips with low signal transmission rate requirements. However, in high-end chips with increasingly high-speed signal requirements, titanium cannot meet the requirements of high current density on electromigration resistance due to its weak electromigration resistance, and thus cannot effectively ensure the reliability of the chip.
[0050] Tungsten (W), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN) have strong electromigration resistance and low resistivity. In high-end chips with increasingly high-speed signal requirements, they can meet the requirements of preventing electromigration under high current density, thereby ensuring that the conductive circuit on the wafer 100 will not be open-circuit failure due to electromigration caused by high current density, thereby improving the reliability of the chip.
[0051] Further, using tungsten as the electromigration resistance barrier layer 301 also has the advantage of low cost, and in combination with other low-cost materials to form a seed layer 302, the cost of the chip can be further reduced.
[0052] Titanium tungsten has good chemical stability and corrosion resistance in addition to stronger electromigration resistance and conductivity than titanium, and is low in cost, so it is cost-effective to use titanium tungsten as the material of the electromigration resistance barrier layer 301 in high-end chips. At the same time, titanium tungsten has strong metal adhesion, so using titanium tungsten as the material of the electromigration resistance barrier layer 301 can improve the structural stability between the electromigration resistance barrier layer 301 and the seed layer 302 and the conductive layer 200, respectively.
[0053] Titanium nitride is a hard ceramic material that also has good chemical stability, corrosion resistance, and mechanical strength, and high metal adhesion, so using titanium nitride as the electromigration resistance barrier layer 301 can provide good mechanical support for the bump 400, and the relatively low atomic mass of titanium nitride can also reduce the overall weight of the chip structure.
[0054] Tantalum also has good chemical stability and corrosion resistance, and is highly resistant to corrosion by most acids, including aqua regia. At the same time, tantalum can maintain the above-mentioned strong electromigration resistance, chemical stability, and corrosion resistance under high-temperature conditions, so tantalum can also maintain high reliability in chips under high-temperature environments.
[0055] Tantalum nitride also has excellent chemical stability, and its metal adhesion is higher than that of titanium nitride, so using tantalum nitride as the electromigration resistance barrier layer 301 is very suitable for high-end chip products such as AI chips and memory chips that have high bandwidth and low latency. At the same time, the relatively large atomic mass of tantalum nitride allows it to be quickly deposited on the bottom and walls of through-silicon vias (TSVs) in a sputtering process, and the tantalum nitride barrier layer formed has a thin thickness, making it suitable for use in silicon vias of chips with a size of 10 nm or less.
[0056] In an optional embodiment, the bump 400 includes a first electroplated layer 401 and a second electroplated layer 402. The first electroplated layer 401 is disposed on the side of the seed layer 302 away from the electromigration resistance barrier layer 301, and the second electroplated layer 402 is disposed on the side of the first electroplated layer 401 away from the seed layer 302. In this embodiment, as shown in FIG. 4B, the first electroplated layer 401 is disposed on the side above the seed layer 302, the lower surface of the first electroplated layer 401 is connected to the upper surface of the seed layer 302, the second electroplated layer 402 is disposed on the side above the first electroplated layer 401, and the lower surface of the second electroplated layer 402 is connected to the upper surface of the first electroplated layer 401. Figure 1
[0057] In an optional embodiment, the first electroplated layer 401 is composed of palladium, and the second electroplated layer 402 is composed of gold.
[0058] The following seed layer 302 can be used in the material: gold, silver, copper, nickel, aluminum and palladium material performance described, the following table 2 is a comparison table of the relevant material properties:
[0059] Table 2:
[0060]
[0061] In an alternative embodiment, the seed layer 302 of the composition of the material includes: any of gold (Au), silver (Ag). Referring to table 2, the resistivity of gold and silver is low, that is, gold and silver have high conductivity. At the same time, the metal of the first electroplated layer 401 is easy to electroplate on the upper side of the gold or silver as the seed layer 302, so the use of gold or silver as the seed layer 302 can reduce the process difficulty, thereby improving the production efficiency.
[0062] In an alternative embodiment, the seed layer 302 of the composition of the material includes: any of copper (Cu), nickel (Ni) and aluminum (Al). Referring to table 2, copper and aluminum have good conductivity, nickel has strong chemical stability, and copper is also easy to electroplate the first electroplated layer 401. At the same time, copper, nickel and aluminum are low in price, and as the composition of the seed layer 302, the cost of the chip package can be reduced.
[0063] In an alternative embodiment, the seed layer 302 of the composition of the material is palladium (Pd). In this alternative embodiment, when the composition of the first electroplated layer 401 is selected as palladium, the seed layer 302 also uses palladium as the composition of the material, at this time the first electroplated layer 401 and the seed layer 302 are the same in material, the first electroplated layer 401 is more easily formed on the seed layer 302 in the electroplating process, and the adhesion between the first electroplated layer 401 and the seed layer 302 after formation is good. At the same time, palladium itself has high hardness and very high metal adhesion, so the palladium seed layer 302 has high structural stability between the barrier layer and the bump 400 as the composition of the seed layer 302.
[0064] In some specific embodiments, the composition of the material used in the electromigration resistant barrier layer 301 in the UBM layer 300 and the composition of the material used in the seed layer 302 can be respectively selected from the materials listed in the above alternative embodiments to form a combination, and the combination effect of each UBM layer 300 formed can be referred to the above description of the corresponding material embodiment. For example, in some specific embodiments, the composition of the material of the electromigration resistant barrier layer 301 uses titanium tungsten, and the composition of the material of the seed layer 302 uses gold. The chip packaging structure can prevent open circuit failure caused by electromigration under high current density through the titanium tungsten layer, and due to the easy electroplating characteristics of gold, the process difficulty of the chip packaging structure can be reduced, thereby improving the production efficiency. At the same time, titanium tungsten has high metal adhesion, so the structural stability between the titanium tungsten layer and the gold layer can also be improved.
[0065] The electronic device disclosed by the embodiment of the utility model, the electronic device includes device main part and the chip package structure described in the embodiment of the utility model.
[0066] It can be seen that the electronic device of the utility model can prevent electromigration from occurring under high current density by configuring an electromigration resistance barrier layer in the UBM layer, avoid open circuit failure, and improve the reliability of the chip in the electronic device.
[0067] Finally, it should be noted that: the chip package structure and the electronic device disclosed by the embodiment of the utility model are only the preferred embodiment of the utility model, and are used to illustrate the technical scheme of the utility model, not to limit it; although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand; the technical scheme recorded in the foregoing embodiments can still be modified, or some technical features can be replaced; and these modifications or replacements do not make the essence of the corresponding technical scheme deviate from the spirit and scope of the technical scheme of the embodiments of the utility model.
Claims
1. A chip package structure, characterized by, The chip packaging structure comprises: a wafer, a target side of the wafer being provided with a circuit groove; a conductive layer, the conductive layer being filled in the circuit groove of the wafer; a UBM layer, the UBM layer comprising an electromigration resistance barrier layer and a seed layer, the electromigration resistance barrier layer being covered on the conductive layer, the seed layer being arranged on a side of the electromigration resistance barrier layer away from the conductive layer; a bump, the bump being arranged on a side of the seed layer away from the electromigration resistance barrier layer.
2. The chip package structure of claim 1, wherein, The composition material of the electromigration resistance barrier layer comprises any one of tungsten, titanium tungsten, titanium nitride, tantalum and tantalum nitride.
3. The chip package structure of claim 2, wherein, The bump comprises: a first electroplated layer, the first electroplated layer being arranged on a side of the seed layer away from the electromigration resistance barrier layer; a second electroplated layer, the second electroplated layer being arranged on a side of the first electroplated layer away from the seed layer.
4. The chip package structure of claim 3, wherein, The composition material of the first electroplated layer is palladium, and the composition material of the second electroplated layer is gold.
5. The chip package structure of claim 2, wherein, The composition material of the seed layer comprises any one of gold and silver.
6. The chip package structure of claim 2, wherein, The composition material of the seed layer comprises any one of copper, nickel and aluminum.
7. The chip package structure of claim 4, wherein, The composition material of the seed layer is palladium.
8. The chip package structure of any one of claims 1 to 7, wherein, The chip packaging structure further comprises: a passivation layer, the passivation layer being covered on the target side of the wafer, the passivation layer being provided with an exposed area at a position corresponding to the conductive layer; wherein the electromigration resistance barrier layer is covered on the conductive layer through the exposed area.
9. The chip package structure of any one of claims 1 to 7, wherein, The composition material of the conductive layer comprises any one of aluminum and copper.
10. An electronic device, comprising: The device body and the chip packaging structure as claimed in any one of claims 1 to 9 are comprised. The chip packaging structure comprises: a wafer, a target side of the wafer being provided with a circuit groove; a conductive layer, the conductive layer being filled in the circuit groove of the wafer; a UBM layer, the UBM layer comprising an electromigration resistance barrier layer and a seed layer, the electromigration resistance barrier layer being covered on the conductive layer, the seed layer being arranged on a side of the electromigration resistance barrier layer away from the conductive layer; a bump, the bump being arranged on a side of the seed layer away from the electromigration resistance barrier layer. The composition material of the electromigration resistance barrier layer comprises any one of tungsten, titanium tungsten, titanium nitride, tantalum and tantalum nitride. The bump comprises: a first electroplated layer, the first electroplated layer being arranged on a side of the seed layer away from the electromigration resistance barrier layer; a second electroplated layer, the second electroplated layer being arranged on a side of the first electroplated layer away from the seed layer. The composition material of the first electroplated layer is palladium, and the composition material of the second electroplated layer is gold. The composition material of the seed layer comprises any one of gold and silver. The composition material of the seed layer comprises any one of copper, nickel and aluminum. The composition material of the seed layer is palladium. The chip packaging structure further comprises: a passivation layer, the passivation layer being covered on the target side of the wafer, the passivation layer being provided with an exposed area at a position corresponding to the conductive layer; wherein the electromigration resistance barrier layer is covered on the conductive layer through the exposed area. The composition material of the conductive layer comprises any one of aluminum and copper. The device body and the chip packaging structure as claimed in any one of claims 1 to 9 are comprised.