Device and system for superconducting quantum computing control, reading and feedback

Abstract

The utility model relates to the technical field of quantum computing, in particular to a device and a system for controlling, reading and feeding back superconducting quantum computing, and the device for controlling, reading and feeding back superconducting quantum computing comprises a clock module and one or more acquisition modules, the clock module is used for providing a clock synchronization signal to each acquisition module so as to realize clock synchronization among the acquisition modules; each acquisition module is connected to the quantum chip and the clock module, and each acquisition module is used for receiving a measurement signal output by the quantum chip and outputting a driving signal to drive the quantum chip to perform quantum operation. According to the embodiment of the utility model, the stimulation modules are synchronized through the clock synchronization signals, and the delay between the acquisition modules can be reduced, so that the low-delay control of the quantum chip is realized.

Description

Technical Field

[0001] This utility model relates to the field of quantum computing technology, and in particular to a device and system for superconducting quantum computing control, readout and feedback. Background Technology

[0002] With the rapid development of superconducting quantum computing, the number of qubits on quantum chips has exceeded 50. This increase in the number of qubits places higher demands on the measurement and control systems of quantum chips. Previously, quantum chip measurement and control systems mainly consisted of commercially available arbitrary waveform generators (AWGs) and data acquisition cards (DAQ-cards). As the number of qubits increases, the scale of the measurement and control system also grows linearly. This presents more challenges to experiments in terms of cost, convenience, and the latency of real-time feedback. Utility Model Content

[0003] According to one aspect of this utility model, a device for controlling, reading, and providing feedback in superconducting quantum computing is provided. The device includes a clock module and one or more acquisition modules, wherein...

[0004] The clock module is used to provide clock synchronization signals to each acquisition module in order to achieve clock synchronization between the acquisition modules.

[0005] Each acquisition module is connected to the quantum chip and the clock module. Each acquisition module is used to receive the measurement signal output by the quantum chip and output a drive signal to drive the quantum chip to perform quantum operations.

[0006] In one possible implementation, the acquisition module includes a radio frequency signal output module, a radio frequency signal input module, a pulse signal output module, a pulse signal input module, a logic control module, and a timing synchronization module, wherein...

[0007] The output terminal of the radio frequency signal output module is connected to the input terminal of the quantum chip and is used to output the driving signal;

[0008] The input terminal of the radio frequency signal input module is connected to the output terminal of the quantum chip and is used to receive the measurement signal;

[0009] The pulse signal output module is used to output pulse signals;

[0010] The pulse signal input module is used to receive pulse signals;

[0011] The timing synchronization module is used to receive clock synchronization signals in order to achieve clock synchronization with other acquisition modules;

[0012] The logic control module is connected to the radio frequency signal output module, the radio frequency signal input module, the pulse signal output module, the pulse signal input module, and the timing synchronization module.

[0013] In one possible implementation, the radio frequency signal output module includes a digital-to-analog converter for converting the received digital drive information into an analog-to-digital signal and obtaining the drive signal.

[0014] The radio frequency signal input module includes an analog-to-digital converter and a comparison circuit. The analog-to-digital converter is used to convert the measurement signal into a digital operation signal. The comparison circuit is used to perform a comparison operation between the digital operation signal and a preset signal to determine the state of the quantum bit based on the comparison result.

[0015] In one possible implementation, the logic control module is used for:

[0016] The digital drive information is output based on the state of the quantum bit and the pulse signal received by the pulse signal input module.

[0017] In one possible implementation, the logic control module is used for:

[0018] The state of the qubit is converted into a pulse signal and output through the pulse signal output module.

[0019] In one possible implementation, the clock module includes an atomic clock signal input module, a clock synchronization signal output module, a trigger signal input module, and a trigger signal output module, wherein,

[0020] The clock signal input terminal of the atomic clock signal input module is used to receive atomic clock signals and configure clock signals for the clock module;

[0021] The clock synchronization signal output module is used to output the clock synchronization signal;

[0022] The trigger signal input module is connected to a host computer or an external triggering device and is used to receive a first trigger signal sent by the host computer or a second trigger signal sent by the external triggering device.

[0023] The trigger signal output module is used to output one or more third trigger signals.

[0024] In one possible implementation, the clock module further includes a rubidium atomic clock, the clock signal input terminal of the atomic clock signal input module is connected to the output terminal of the rubidium atomic clock, and the output terminal of the rubidium atomic clock is used to output the atomic clock signal.

[0025] In one possible implementation, the sampling rates of both the radio frequency signal output module and the radio frequency signal input module are greater than 1 Gsps.

[0026] In one possible implementation, both the acquisition module and the clock module are implemented based on a field-programmable gate array (FPGA).

[0027] According to one aspect of the present invention, a system for superconducting quantum computing control, readout and feedback is provided, the system comprising one or more of the aforementioned devices and quantum chips for superconducting quantum computing control, readout and feedback.

[0028] The device for control, reading, and feedback of superconducting quantum computing according to this embodiment includes a clock module and one or more acquisition modules. The clock module provides a clock synchronization signal to each acquisition module to achieve clock synchronization between the acquisition modules. Each acquisition module is used to receive the measurement signal output by the quantum chip and output a drive signal to drive the quantum chip to perform quantum operations. By synchronizing the stimulation modules through the clock synchronization signal, the delay between acquisition modules can be reduced, thereby achieving low-latency control of the quantum chip.

[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the present invention. Other features and aspects of the present invention will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and, together with the specification, serve to explain the technical solutions of the present invention.

[0031] Figure 1 A block diagram of a device for superconducting quantum computing control, readout, and feedback according to an embodiment of the present invention is shown.

[0032] Figure 2 A block diagram of the acquisition module in a device for superconducting quantum computing control, readout, and feedback according to an embodiment of the present invention is shown.

[0033] Figure 3A block diagram of a clock module in a device for superconducting quantum computing control, readout, and feedback according to an embodiment of the present invention is shown. Detailed Implementation

[0034] Various exemplary embodiments, features, and aspects of the present invention will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0035] In the description of this utility model, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0037] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0038] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0039] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0040] Furthermore, to better illustrate this utility model, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this utility model can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this utility model.

[0041] Please see Figure 1 , Figure 1 A block diagram of a device for superconducting quantum computing control, readout, and feedback according to an embodiment of the present invention is shown.

[0042] like Figure 1 As shown, the device for superconducting quantum computing control, readout, and feedback includes a clock module 10 and one or more acquisition modules 20, wherein...

[0043] The clock module 10 is used to provide clock synchronization signals to each acquisition module 20 in order to achieve clock synchronization between each acquisition module 20.

[0044] Each acquisition module 20 is connected to the quantum chip 30 and the clock module 10. Each acquisition module 20 is used to receive the measurement signal output by the quantum chip 30 and output a drive signal to drive the quantum chip 30 to perform quantum operations.

[0045] The device for superconducting quantum computing control, reading, and feedback according to this embodiment includes a clock module 10 and one or more acquisition modules 20. The clock module 10 provides a clock synchronization signal to each acquisition module 20 to achieve clock synchronization between the acquisition modules 20. Each acquisition module 20 is used to receive the measurement signal output by the quantum chip 30 and output a drive signal to drive the quantum chip 30 to perform quantum operations. By synchronizing the stimulation modules through the clock synchronization signal, the delay between the acquisition modules 20 can be reduced, thereby achieving low-latency control of the quantum chip 30 using the acquisition modules.

[0046] This embodiment of the invention does not limit the type of quantum chip 30, or the specific implementation of the clock module 10 and one or more acquisition modules 20. Those skilled in the art can set them according to actual conditions and needs. The quantum chip 30, clock module 10, and one or more acquisition modules 20 can all be implemented by hardware circuits. The quantum chip is the core structure for realizing quantum computing. A large number of qubit structures are set on the quantum chip. Each qubit is composed of specific hardware circuits set on the quantum chip. Each qubit has at least two distinguishable logical states. Based on quantum algorithms, the logical states of qubits can undergo controllable changes, thereby realizing quantum computing.

[0047] The device for superconducting quantum computing control, reading and feedback according to this embodiment may further include a device body, such as a square chassis, with each module disposed within the device body. Of course, the shape of the device body may also be other, and this embodiment does not limit this. Those skilled in the art can set it according to actual conditions and needs.

[0048] For example, the device for controlling, reading, and providing feedback in superconducting quantum computing according to this embodiment can be connected to a quantum system. The core of the quantum system is a quantum chip 30 located inside a refrigerator, which can realize quantum computing. The entire system includes external devices for both room temperature and low temperature (below 4K). To control the quantum chip 30, a radio frequency electromagnetic drive signal is required. For example, a data acquisition module 20 can emit a radio frequency signal of about 100 MHz and some trigger signals (e.g., which can be used to control other room temperature devices). After passing through a series of microwave devices, it can control one channel of the quantum chip 30. Multiple data acquisition cards can be used in conjunction to control the entire quantum chip 30.

[0049] The preferred implementation methods of the acquisition module 20 and the clock module 10 are described below as examples.

[0050] Please see Figure 2 , Figure 2 A block diagram of the acquisition module 20 in a device for superconducting quantum computing control, readout and feedback according to an embodiment of the present invention is shown.

[0051] In one possible implementation, such as Figure 2 As shown, the acquisition module 20 may include an RF signal output module 220, an RF signal input module 210, a pulse signal output module 230, a pulse signal input module 240, a logic control module 260, and a timing synchronization module 250, wherein...

[0052] The output terminal of the radio frequency signal output module 220 is connected to the input terminal of the quantum chip 30 and is used to output the driving signal;

[0053] The input terminal of the radio frequency signal input module 210 is connected to the output terminal of the quantum chip 30 and is used to receive the measurement signal;

[0054] The pulse signal output module 230 is used to output pulse signals;

[0055] The pulse signal input module 240 is used to receive pulse signals;

[0056] The timing synchronization module 250 is used to receive clock synchronization signals in order to achieve clock synchronization with other acquisition modules 20.

[0057] The logic control module 260 is connected to the radio frequency signal output module 220, the radio frequency signal input module 210, the pulse signal output module 230, the pulse signal input module 240, and the timing synchronization module 250.

[0058] This embodiment of the present invention does not limit the specific implementation of the radio frequency signal output module 220, radio frequency signal input module 210, pulse signal output module 230, pulse signal input module 240, logic control module 260, and timing synchronization module 250. Those skilled in the art can set them according to actual conditions and needs. For example, the radio frequency signal output module 220, radio frequency signal input module 210, pulse signal output module 230, and pulse signal input module 240 all include hardware interfaces. This embodiment of the present invention does not limit the type of hardware interface or the protocol used. Those skilled in the art can set them according to actual conditions and needs.

[0059] In one possible implementation, the radio frequency signal output module 220 may include a digital-to-analog converter (DAC) for converting the received digital drive information into an analog-to-digital signal and obtaining the drive signal. This embodiment of the present invention does not limit the specific implementation of the DAC or the specific parameters (such as accuracy) of the DAC. Those skilled in the art can use a suitable DAC according to the actual situation and needs.

[0060] For example, the radio frequency signal output module 220 is capable of outputting signals at a sampling rate of at least 1 Gsps, which can be used to drive quantum chips in a quantum system, where Gsps (Giga Samples per Second) is a unit of sampling rate, representing the number of samples collected per second in the billions.

[0061] In one possible implementation, the radio frequency signal input module 210 may include an analog-to-digital converter (ADC) and a comparison circuit. The ADC is used to convert the measurement signal from analog to digital to obtain a digital operation signal. The comparison circuit is used to perform a comparison operation between the digital operation signal and a preset signal to determine the state of the qubit based on the comparison result. This embodiment of the invention does not limit the specific implementation of the ADC and the comparison circuit, nor does it limit the specific parameters (such as accuracy) of the ADC. Those skilled in the art can use a suitable ADC according to the actual situation and needs. As an example, the comparison circuit may include a comparator and related peripheral circuits. Those skilled in the art can refer to relevant technologies for its specific implementation.

[0062] For example, the radio frequency (RF) signal input module 210 can acquire RF input signals at a sampling rate of at least 1 Gsps, which can be used to obtain information output by the quantum system. This RF signal input module 210 has demodulation and analysis capabilities, enabling it to analyze the state of the qubits from the acquired data. The ADC chip used in the RF signal input module 210 can convert analog signals into digital signals. The RF signal input module 210 processes the obtained digital signals and compares them with preset values ​​to determine the state of the qubits.

[0063] For example, the pulse signal output module 230 can output pulse signals (such as 0 / 2V signals), and the pulse signal input module 240 can input pulse signals (such as 0 / 2V signals), where 0V represents bit 0 and 2V represents bit 1. Of course, other preset logic can also be used for output, which is not limited in this embodiment. The logic control module 260 and the timing control module are directly programmed on the FPGA. Additional functionalities are described below. They all have dedicated logic circuits. Dedicated conversion chips are used for both radio frequency signal input / output and pulse signal input / output.

[0064] For example, the pulse signal output module 230 can output a 0V or 2V pulse signal. The pulse signal output module 230 outputs according to logic preset by the experimenter (for example, one acquisition module 20 can contain multiple pulse signal output modules 230). This logic can be output sequentially according to a preset instruction sequence (e.g., 0V*20ns, 2V*100ns, 0V*40ns), or it can be the output of the logic control module 260. This pulse signal can be used to control other devices or send signals to other acquisition modules 20. When used to control other devices, it mainly acts as a trigger signal, similar to a switch. When sending relevant signals (such as bit status) to other acquisition modules 20, 0V can represent bit 0, 2V can represent bit 1, or other preset logic can be used for output.

[0065] In one possible implementation, the logic control module 260 is used for:

[0066] The quantum bit state is converted into a pulse signal and output through the pulse signal output module 230, for example, converted into a 0 / 2V signal as a pulse signal output.

[0067] For example, the pulse signal input module 240 can receive pulse signals. Specifically, it can receive the signal output by the pulse signal output module 230 in other acquisition modules 20 and send the result to the logic control module 260. Other acquisition modules 20 can send the quantum bit state obtained by the radio frequency signal input module 210 to the pulse signal input module 240 of this acquisition module 20 through the pulse signal output module 230, thereby transmitting the bit information of the quantum bit between the acquisition modules 20.

[0068] This embodiment of the invention does not limit the specific implementation of the logic control module 260. Those skilled in the art can implement it using relevant technologies according to actual conditions and needs. For example, the logic control module 260 may include processing components, which may include, but are not limited to, a single processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0069] Preferably, the logic control module 260 of this utility model embodiment is implemented using FPGA, which can improve the processing capability of the quantum chip 30 with an increased number of qubits and increase the scale of the measurement and control system. The technical solution of this utility model embodiment is applied to an FPGA-based system, which can solve the problems of high cost and cumbersome control in traditional measurement and control systems, and can achieve quantum real-time feedback at the level of hundreds of nanoseconds. Furthermore, this utility model embodiment can solve the problem of real-time feedback in multiple chassis and multiple nested structures.

[0070] In one possible implementation, the logic control module 260 can be used to:

[0071] The digital drive information is output based on the state of the quantum bit and the pulse signal received by the pulse signal input module 240.

[0072] This embodiment of the invention does not limit the specific implementation of outputting the digital driving information based on the state of the quantum bit and the pulse signal received by the pulse signal input module 240. Those skilled in the art can refer to relevant technologies to implement it according to actual conditions and needs.

[0073] For example, the logic control module 260 can use the measurement signal received by the radio frequency signal input module 210 and the pulse signal received by the pulse signal input module 240 to determine the current state of the quantum system (the state of the qubit) and the next operation required, thereby controlling the output waveform of the drive signal of the radio frequency signal output module 220 to control the quantum system, and sending the result (generally, transmitting the qubit information obtained by the radio frequency signal input module 210) to other acquisition modules 20 and / or other devices through the pulse signal output module 230.

[0074] For example, the radio frequency signal input module 210 can analyze the acquired waveform (measurement result) to obtain information about the qubit controlled by the current acquisition module 20, and the pulse signal input module 240 can obtain information about the qubit controlled by other acquisition modules 20 (for example, there is another acquisition module 20 that obtains the qubit signal through its own radio frequency signal input module 210, analyzes and obtains the 01 state of the qubit, and then transmits it to the pulse signal input module 240 of the current acquisition module 20 through the pulse signal output module 230). The logic control module 260 can combine the signals from the radio frequency signal input module 210 and the pulse signal input module 240 to obtain the qubit state according to the preset logic operation. Of course, the specific type of preset logic operation is not limited in this embodiment of the invention, and those skilled in the art can set it according to the actual situation and needs.

[0075] For example, the state of the qubit can be transmitted to other acquisition modules 20 by the pulse signal output module 230, thereby obtaining the state of the entire quantum chip 30 and performing the next feedback operation.

[0076] Of course, the above description of the functions of the logic control module 260 is exemplary and should not be regarded as a limitation on the embodiments of this utility model. Those skilled in the art can use the logic control module 260 to control other modules according to actual conditions and needs.

[0077] This embodiment of the invention does not limit the specific implementation of the timing synchronization module 250. Those skilled in the art can configure it according to actual conditions and needs. For example, the timing synchronization module 250 can cooperate with subsequent control and triggering systems to finely adjust the system's timing. Specifically, to improve the measurement and control accuracy of the quantum chip 30, this embodiment of the invention requires alignment of the measurement and control signals at the picosecond level. Due to factors such as line length, the signals emitted from the room-temperature device are not naturally aligned when they reach the superconducting chip. Therefore, this embodiment of the invention requires fine adjustment of the start-up times of different acquisition modules 20. The timing synchronization module 250 can adjust the trigger times of different acquisition modules 20 at the picosecond level and ensure that they remain synchronized throughout the experiment with consistent mutual delays, thereby improving the experimental timing accuracy.

[0078] Please see Figure 3 , Figure 3 A block diagram of a clock module 10 in a device for superconducting quantum computing control, readout, and feedback according to an embodiment of the present invention is shown.

[0079] In one possible implementation, such as Figure 3 As shown, the clock module 10 may include an atomic clock signal input module 110, a clock synchronization signal output module 120, a trigger signal input module 130, and a trigger signal output module 140, wherein...

[0080] The clock signal input terminal of the atomic clock signal input module 110 is used to receive atomic clock signals and configure clock signals for the clock module 10;

[0081] The clock synchronization signal output module 120 is used to output the clock synchronization signal to achieve synchronization and calibration of different acquisition modules 20. For example, the clock module 10 may also include a synchronization signal generation circuit. When the atomic clock signal input module 110 receives an atomic clock signal (e.g., a 10MHz signal), the synchronization signal generation circuit can generate multiple mutually synchronized clock synchronization signals (e.g., a 125MHz signal) based on the atomic clock signal. These signals are then output from different clock synchronization signal output modules 120 (clock synchronization signal output ports) to each acquisition module 20. Since the clock synchronization signals are synchronized, synchronization and calibration of different acquisition modules 20 can be achieved.

[0082] The trigger signal input module 130 is connected to a host computer or an external triggering device and is used to receive a first trigger signal sent by the host computer or a second trigger signal sent by the external triggering device. Thus, the trigger signal input module 130 of this embodiment can select internal triggering or external triggering functions. Internal triggering means that the host computer program controls the trigger clock module 10 through the first trigger signal; external triggering means that the clock module 10 waits for the second trigger signal from the trigger input port to trigger other devices.

[0083] The trigger signal output module 140 is used to output one or more third trigger signals. Thus, through the trigger signal output module 140, this embodiment of the invention can simultaneously trigger multiple clock modules 10 or acquisition modules 20. Clock module 10 triggering clock module 10 can achieve multi-level triggering. For example, if the current clock module 10 receives a second trigger signal from another clock module 10 or a first trigger signal sent by the host computer, it can immediately generate and output one or more third trigger signals, triggering the acquisition module 20 and other connected clock modules 10. Of course, the trigger delay (the duration between receiving the first trigger signal and the second trigger signal and generating and outputting one or more third trigger signals) is adjustable (i.e., it can be set to wait for a period of time (ns) after receiving the trigger signal before triggering the next level). Simultaneously, which acquisition modules 20 and clock modules 10 are triggered can also be set; this embodiment of the invention does not limit this.

[0084] The present invention does not limit the specific implementation of the atomic clock signal input module 110, the clock synchronization signal output module 120, the trigger signal input module 130, and the trigger signal output module 140. Those skilled in the art can set them according to actual conditions and needs.

[0085] In one possible implementation, such as Figure 3 As shown, the clock module 10 may further include a rubidium atomic clock 100. The clock signal input terminal of the atomic clock signal input module 110 is connected to the output terminal of the rubidium atomic clock 100, and the output terminal of the rubidium atomic clock 100 is used to output the atomic clock signal.

[0086] This embodiment of the invention improves the clock output accuracy of the clock module 10 by providing a precise clock signal (the atomic clock signal) through the setting of a rubidium atomic clock 100.

[0087] In one possible implementation, the sampling rates of both the RF signal output module 220 and the RF signal input module 210 are greater than 1 Gsps.

[0088] The apparatus for superconducting quantum computing control, reading, and feedback according to embodiments of this utility model may further include other modules. This utility model does not limit the scope of the embodiments in this regard, and those skilled in the art can configure them according to actual conditions and needs. For example, the apparatus for superconducting quantum computing control, reading, and feedback may further include a storage module for storing data. In one example, the storage module may include a computer-readable storage medium, which can be a tangible device capable of holding and storing instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), programmable read-only memory (PROM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media as used herein is not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0089] In one possible implementation, both the acquisition module 20 and the clock module 10 are implemented based on a field-programmable gate array (FPGA).

[0090] According to one aspect of the present invention, a system for superconducting quantum computing control, readout and feedback is provided, the system comprising one or more of the aforementioned devices for superconducting quantum computing control, readout and feedback and quantum chip 30.

[0091] The device for superconducting quantum computing control, readout, and feedback according to the embodiments of this utility model has the following advantages compared with the prior art:

[0092] I. This utility model embodiment realizes real-time feedback across multiple cards in a chassis, has good scalability, and can be used to realize large-scale quantum bit feedback experiments.

[0093] II. The present invention provides a customized integrated system based on FPGA, which significantly improves cost, convenience and real-time feedback latency.

[0094] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A device for control, readout, and feedback in superconducting quantum computing, characterized in that, The device for superconducting quantum computing control, readout, and feedback includes a clock module and one or more acquisition modules, wherein... The clock module is used to provide clock synchronization signals to each acquisition module in order to achieve clock synchronization between the acquisition modules. Each acquisition module is connected to the quantum chip and the clock module. Each acquisition module is used to receive the measurement signal output by the quantum chip and output a drive signal to drive the quantum chip to perform quantum operations.

2. The device for superconducting quantum computing control, readout, and feedback according to claim 1, characterized in that, The acquisition module includes an RF signal output module, an RF signal input module, a pulse signal output module, a pulse signal input module, a logic control module, and a timing synchronization module. The output terminal of the radio frequency signal output module is connected to the input terminal of the quantum chip and is used to output the driving signal; The input terminal of the radio frequency signal input module is connected to the output terminal of the quantum chip and is used to receive the measurement signal; The pulse signal output module is used to output pulse signals; The pulse signal input module is used to receive pulse signals; The timing synchronization module is used to receive clock synchronization signals in order to achieve clock synchronization with other acquisition modules; The logic control module is connected to the radio frequency signal output module, the radio frequency signal input module, the pulse signal output module, the pulse signal input module, and the timing synchronization module.

3. The device for superconducting quantum computing control, readout, and feedback according to claim 2, characterized in that, The radio frequency signal output module includes a digital-to-analog converter, used to convert the received digital drive information into digital-to-analog data and obtain the drive signal; The radio frequency signal input module includes an analog-to-digital converter and a comparison circuit. The analog-to-digital converter is used to convert the measurement signal into a digital operation signal. The comparison circuit is used to perform a comparison operation between the digital operation signal and a preset signal to determine the state of the quantum bit based on the comparison result.

4. The device for superconducting quantum computing control, readout, and feedback according to claim 3, characterized in that, The logic control module is used for: The digital drive information is output based on the state of the quantum bit and the pulse signal received by the pulse signal input module.

5. The device for superconducting quantum computing control, readout, and feedback according to claim 3, characterized in that, The logic control module is used for: The state of the qubit is converted into a pulse signal and output through the pulse signal output module.

6. The apparatus for superconducting quantum computing control, readout, and feedback according to claim 1, characterized in that, The clock module includes an atomic clock signal input module, a clock synchronization signal output module, a trigger signal input module, and a trigger signal output module, wherein... The clock signal input terminal of the atomic clock signal input module is used to receive atomic clock signals and configure clock signals for the clock module; The clock synchronization signal output module is used to output the clock synchronization signal; The trigger signal input module is connected to a host computer or an external triggering device and is used to receive a first trigger signal sent by the host computer or a second trigger signal sent by the external triggering device. The trigger signal output module is used to output one or more third trigger signals.

7. The apparatus for superconducting quantum computing control, readout, and feedback according to claim 6, characterized in that, The clock module also includes a rubidium atomic clock. The clock signal input terminal of the atomic clock signal input module is connected to the output terminal of the rubidium atomic clock, and the output terminal of the rubidium atomic clock is used to output the atomic clock signal.

8. The apparatus for superconducting quantum computing control, readout, and feedback according to claim 2, characterized in that, The sampling rates of both the radio frequency signal output module and the radio frequency signal input module are greater than 1 Gsps.

9. The apparatus for superconducting quantum computing control, readout, and feedback according to claim 1, characterized in that, Both the acquisition module and the clock module are implemented based on a field-programmable gate array (FPGA).

10. A system for control, readout, and feedback in superconducting quantum computing, characterized in that, The system for superconducting quantum computing control, readout, and feedback includes one or more devices and quantum chips for superconducting quantum computing control, readout, and feedback as described in any one of claims 1-9.

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