Address allocation circuit of battery management system

Abstract

The utility model relates to an address distribution circuit of a battery management system in the field of battery management systems, which comprises an ID distribution module, a distribution completion module and an MCU, compared with the prior art, the MCU sends an ID distribution signal to the ID distribution module, the ID distribution module sends a first electric signal to an address to-be-distributed module, and the address to-be-distributed module sends a second electric signal to the address to-be-distributed module. The address to-be-distributed module sends a second electric signal to the distribution completion module, and the distribution completion module sends a third signal to the MCU, so that the automatic ID distribution process is realized, the distribution efficiency and accuracy are greatly improved, and the complexity of manual operation is reduced. Through the design, manual intervention and configuration time are reduced, so that the operation and maintenance cost is remarkably reduced, and the overall reliability and efficiency of the system are improved.

Description

Technical Field

[0001] This utility model relates to the field of battery management systems, and in particular to an address allocation circuit for a battery management system. Background Technology

[0002] In modern battery systems, the battery management system (BMS) plays a crucial role. The BMS monitors battery status in real time, preventing overcharging and over-discharging, thereby extending battery life and improving its utilization. A single BMS typically manages multiple battery cluster management units (BCUs) and configures each BCU with an independent physical address to enable communication between the system and the battery clusters.

[0003] Current technology relies on hardware settings, configuring addresses via DIP switches. However, when a BCU needs to be replaced, because the address is fixed, the BCU to be replaced must first be identified, and then a new BCU with the same address must be used to replace it. This process results in high manual configuration and update costs.

[0004] Therefore, there is an urgent need for a battery management system address allocation circuit. Utility Model Content

[0005] To address the aforementioned technical problems, this invention proposes a battery management system address allocation circuit, reducing manual intervention and configuration time, thereby significantly lowering operating and maintenance costs and improving the overall reliability and efficiency of the system. The technical solution of this invention is as follows:

[0006] This utility model proposes a battery management system address allocation circuit, including:

[0007] The ID allocation module has its input end connected to the MCU and its output end connected to the address allocation module. It is used to send the first electrical signal to the address allocation module after receiving the ID allocation signal from the MCU.

[0008] The allocation completion module has its input end connected to the address to be allocated module and its output end connected to the MCU. It is configured to receive the second electrical signal from the address to be allocated module after completing ID transmission, and to output a third electrical signal to the MCU after receiving the second electrical signal.

[0009] The MCU is configured to send an ID allocation signal to the ID allocation module, receive a third electrical signal, and determine whether the ID allocation is complete based on the third electrical signal.

[0010] In one possible implementation, the ID allocation module includes:

[0011] The first input unit is used to receive the ID allocation signal, which is a high-level initialization signal.

[0012] The first step-down unit, whose input terminal is connected to the first input unit, is used to reduce the voltage value of the initialization high-level signal.

[0013] The first output unit has its input terminal connected to the first step-down unit and its output terminal connected to the address allocation module. It is used to send a first electrical signal to the address allocation module according to the electrical signal output by the first step-down unit.

[0014] With the above settings, the electrical signal received by the first input unit is a high-level signal. After being stepped down by the first step-down unit, the first output unit sends the first electrical signal to the address allocation module according to the stepped-down electrical signal.

[0015] In one possible implementation, the first buck unit includes a first MOSFET, the gate of which receives the high-level signal, the source of which is grounded, and the drain of which is connected to the first output unit. The first buck unit further includes a first filter component, the input of which is connected to the first input unit, and the output of which is connected to the gate of the first MOSFET. The first filter component includes a first resistor, a second resistor, and a first capacitor. The first end of the first resistor is connected to the first input unit, the second end of which is connected to the first end of the second resistor, and the second end of the second resistor is grounded. The first end of the first capacitor is connected to the second end of the first resistor, and the second end of the first capacitor is grounded.

[0016] In one possible implementation, the first output unit includes a first optocoupler and a third resistor. The first end of the third resistor is connected to a first power supply, the second end of the third resistor is connected to the second input terminal of the first optocoupler, the first input terminal of the first optocoupler is connected to the drain of the first MOS transistor, the first output terminal of the first optocoupler is connected to the address allocation module, and the second output terminal of the first optocoupler is coupled to a second power supply.

[0017] In one possible implementation, the first output unit further includes a second filtering component connected between the second power supply and the first optocoupler. The second filtering component includes a fourth resistor and a second capacitor. The first end of the fourth resistor is connected to the second power supply, the second end of the fourth resistor is connected to the second output terminal of the first optocoupler, the first end of the second capacitor is connected to the second end of the fourth resistor, and the second end of the second capacitor is grounded.

[0018] In one possible implementation, the allocation completion module includes: a second input unit for receiving the second electrical signal from the address to be allocated module, wherein the second electrical signal is a high-level signal.

[0019] The second step-down unit has its input terminal connected to the output terminal of the second input unit and is used to reduce the voltage value of the second electrical signal.

[0020] The second output unit has its input terminal connected to the output terminal of the second buck unit and its output terminal connected to the MCU. It is configured to continuously output a high level to the MCU and output a low level to the MCU according to the electrical signal output by the second buck unit.

[0021] The MCU is used to detect changes in the level of the third electrical signal output by the second output unit.

[0022] In one possible implementation, the second buck unit includes a second MOSFET, the gate of which is coupled to the second input unit, the source of which is grounded, and the drain of which is connected to the second output unit.

[0023] In one possible implementation, the second buck unit further includes a third filter component. The input terminal of the third filter component is connected to the second input unit, and the output terminal of the third filter component is connected to the gate of the second MOS transistor. The third filter component includes a fifth resistor, a sixth resistor, and a third capacitor. The first terminal of the fifth resistor is connected to the second input unit, the second terminal of the fifth resistor is connected to the first terminal of the sixth resistor, and the second terminal of the sixth resistor is grounded. The first terminal of the third capacitor is connected to the second terminal of the sixth resistor, and the second terminal of the third capacitor is grounded.

[0024] In one possible implementation, the second output unit includes a second optocoupler, a seventh resistor, an eighth resistor, and a diode. The first input terminal of the second optocoupler is connected to the drain of the second MOSFET. The second input terminal of the second optocoupler is connected to the first terminal of the seventh resistor. The second terminal of the seventh resistor is connected to a third power supply. The first output terminal of the second optocoupler is grounded. The second output terminal of the second optocoupler is connected to the MCU and the first terminal of the eighth resistor. The second terminal of the eighth resistor is connected to a fourth power supply. The anode of the diode is connected to the second terminal of the seventh resistor, and the cathode of the diode is connected to the gate of the second MOSFET.

[0025] In one possible implementation, the second output unit further includes a fourth filtering component connected between the second optocoupler and the MCU. The fourth filtering component includes a ninth resistor and a fourth capacitor. The first end of the ninth resistor is connected to the second output terminal of the second optocoupler, the second end of the ninth resistor is connected to the MCU, the first end of the fourth capacitor is connected to the second end of the ninth resistor, and the second end of the fourth capacitor is grounded.

[0026] The advantages of this utility model are as follows:

[0027] 1. This utility model designs an ID allocation module, which realizes an automated ID allocation process by sending an electrical signal to the address to be allocated module, greatly improving allocation efficiency and accuracy, and reducing the complexity of manual operation.

[0028] 2. This utility model ensures the stability and reliability of signal transmission by setting up multi-stage step-down, filtering and optocoupler components in the ID allocation module and allocation completion module, effectively filtering out noise in the signal and improving the overall performance of the system.

[0029] 3. This utility model uses a variety of components such as MOSFETs, optocouplers, and diodes to ensure high integration between modules. At the same time, the size of the battery cell slot can be customized according to different battery cell designs, which enhances the compatibility and adaptability of the system.

[0030] 4. This utility model effectively isolates high and low voltage signals through filtering and isolation components, and sets up multiple protection mechanisms in the circuit to ensure the safe and stable operation of the system under various complex working conditions and reduce the probability of failure. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only one embodiment of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Identical parts are indicated by the same reference numerals. It should be noted that the terms "front," "rear," "left," "right," "up," and "down" used in the following description refer to directions in the accompanying drawings, while the terms "bottom surface," "top surface," "inner," and "outer" refer to directions toward or away from the geometric center of a specific part, respectively.

[0033] Figure 1 This is a schematic diagram of the battery management system address allocation circuit in an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of the ID allocation module structure in an embodiment of this utility model;

[0035] Figure 3 This is a circuit diagram of the ID allocation module in an embodiment of this utility model;

[0036] Figure 4 This is a schematic diagram of the allocation completion module structure in an embodiment of this utility model;

[0037] Figure 5 This is a circuit diagram of the allocation completion module in an embodiment of this utility model.

[0038] The meanings of the reference numerals in the above figures are as follows:

[0039] 1. ID allocation module; 11. First input unit; 12. First buck unit; 121. First MOSFET; 122. First filter component; 1221. First resistor; 1222. Second resistor; 1223. First capacitor; 13. First output unit; 131. First optocoupler; 132. Third resistor; 133. Second filter component; 1331. Fourth resistor; 1332. Second capacitor; 134. Fuse;

[0040] 2. Address to be assigned module;

[0041] 3. Allocation Completion Module; 31. Second Input Unit; 32. Second Buck Unit; 321. Second MOSFET; 322. Third Filter Component; 3221. Fifth Resistor; 3222. Sixth Resistor; 3223. Third Capacitor; 33. Second Output Unit; 331. Second Optocoupler; 332. Seventh Resistor; 333. Eighth Resistor; 334. Diode; 335. Fourth Filter Component; 3351. Ninth Resistor; 3352. Fourth Capacitor;

[0042] 4. MCU;

[0043] U1, first power supply; U2, second power supply; U3, third power supply; U4, fourth power supply. Detailed Implementation

[0044] The technical solution of this utility model will be clearly and completely described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0045] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used in the detailed description is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms “comprising” and “having” and any variations thereof in the specification, claims and foregoing description of the invention are intended to cover non-exclusive inclusion.

[0046] In the description of the specific embodiments of this utility model, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this utility model, "multiple" means two or more, unless otherwise explicitly defined.

[0047] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0048] In the description of this utility model embodiment, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, in this utility model, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0049] Throughout this invention, numerical values ​​represent approximate measurements or limits of a range to cover minute deviations from a given value, as well as embodiments having approximately the mentioned value and embodiments having the exact mentioned value. Except for the working examples provided at the end of the detailed description, all numerical values ​​of parameters, quantities, or conditions in the appended claims should be understood to be modified in all cases by the term “about,” regardless of whether “about” actually appears before the numerical value. “About” indicates that the stated numerical value allows for some minute inaccuracy that is somewhat close to the exact value of the value; approximately or reasonably close to the value; almost. If the inaccuracy provided by “about” is not otherwise understood in this common sense in the art, then “about” as used in this invention at least indicates a variation that can be produced by common methods of measuring and using such parameters. For example, “about” may include a variation of less than or equal to 5%, optionally less than or equal to 4%, optionally less than or equal to 3%, optionally less than or equal to 2%, optionally less than or equal to 1%, optionally less than or equal to 0.5%, and in some respects, optionally less than or equal to 0.1%.

[0050] Additionally, the disclosure of the range includes the disclosure of all values ​​across the entire range and the disclosure of further subdivided ranges, including the endpoints and subranges given for these ranges.

[0051] The embodiments of the present invention will be described in more detail below through examples. It should be noted that the embodiments of the present invention are not limited to these examples.

[0052] Example

[0053] This embodiment proposes an address allocation circuit for a battery management system, such as... Figure 1 As shown, it includes an ID allocation module 1, an address allocation module 2, an MCU 4, and an allocation completion module 3. Among them,

[0054] ID allocation module 1 has its input end connected to MCU4 and its output end connected to address allocation module 2. It is used to send a first electrical signal to address allocation module 2 after receiving the ID allocation signal from MCU4.

[0055] The allocation completion module 3 has its input end connected to the address to be allocated module 2 and its output end connected to the MCU4. It is configured to receive the second electrical signal from the address to be allocated module 2 after completing the ID transmission, and to output a third electrical signal to the MCU4 after receiving the second electrical signal.

[0056] MCU4 is configured to send an ID allocation signal to ID allocation module 1, receive a third electrical signal, and determine whether the ID allocation is complete based on the third electrical signal.

[0057] With the above settings, after initialization, ID allocation module 1 sends a first electrical signal to address allocation module 2, triggering address allocation module 2 to perform ID allocation. After address allocation module 2 completes ID allocation, it sends a second electrical signal to allocation completion module 3. Allocation completion module 3 sends a third electrical signal to MCU based on the received second electrical signal, so that MCU can know that address allocation module 2 has completed ID allocation based on the received third electrical signal.

[0058] In some specific implementation methods, such as Figure 2 As shown, the ID allocation module includes:

[0059] The first input unit 11 is used to receive the ID allocation signal, which is a high-level initialization signal.

[0060] The first step-down unit 12 is connected to the first input unit 11 and is used to reduce the voltage value of the initial high-level signal.

[0061] The first output unit 13 has its input terminal connected to the first step-down unit 12 and its output terminal connected to the address allocation module 2. It is used to send a first electrical signal to the address allocation module 2 according to the electrical signal output by the first step-down unit 12.

[0062] The electrical signal received by the first input unit 11 is a high-level signal. After being stepped down by the first step-down unit 12, the first output unit 11 sends the first electrical signal to the address allocation module 2 according to the stepped-down electrical signal.

[0063] With the above settings, the electrical signal received by the first input unit 11 is a high-level signal. After being stepped down by the first step-down unit 12, the first output unit 13 sends a first electrical signal to the address allocation module 2 according to the stepped-down electrical signal, so as to trigger the ID allocation of the address allocation module 2.

[0064] In some specific implementation methods, such as Figure 3 As shown, the first step-down unit 12 includes a first switching component, which includes a first MOSFET 121. The gate of the first MOSFET 121 receives an ID allocation signal, the source of the first MOSFET 121 is grounded, and the drain of the first MOSFET 121 is connected to the first output unit 13.

[0065] The first step-down unit 12 also includes a first filter component 122. The input terminal of the first filter component 122 is connected to the first input unit 11, and the output terminal of the first filter component 122 is connected to the first switching component, i.e., the gate of the first MOS transistor 121 is connected. The first filter component 122 includes a first resistor 1221, a second resistor 1222, and a first capacitor 1223. The first end of the first resistor 1221 is connected to the first input unit 11, the second end of the first resistor 1221 is connected to the first end of the second resistor 1222, the second end of the second resistor 1222 is grounded, the first end of the first capacitor 1223 is connected to the second end of the first resistor 1221, and the second end of the first capacitor 1223 is grounded.

[0066] With the above settings, after the circuit is initialized, the first filter component 122 receives the initialization high-level signal from the first input unit 11 and filters out noise in the signal to ensure the stability of the gate signal. The filtered high-level signal is transmitted to the gate of the first MOS transistor 121. When the gate of the first MOS transistor 121 receives the high-level signal, the first MOS transistor 121 is turned on. After being turned on, the first MOS transistor 121 forms a low-resistance channel between the source and the drain, allowing current to flow and causing its drain voltage to drop to a low level. The low-level signal is transmitted from the drain of the MOS transistor to the first output unit 13.

[0067] In some specific embodiments, the first output unit 13 includes a second switch assembly, the first end of which is connected to the first switch assembly and is configured to turn on after receiving a signal from the first switch assembly.

[0068] Specifically, such as Figure 3As shown, the second switching assembly includes a first optocoupler 131 and a third resistor 132. The first end of the third resistor 132 is connected to the first power supply U1, and the second end of the third resistor 132 is connected to the second input terminal of the first optocoupler 131. The first input terminal of the first optocoupler 131 is connected to the drain of the first MOSFET 121. The first output terminal of the first optocoupler 131 is connected to the address assignment module 2 through a fuse 134. The second output terminal of the first optocoupler 131 is coupled to the second power supply U2.

[0069] With the above settings, when the first MOS transistor 121 is turned on, its drain outputs a low-level signal, which is transmitted to the first input terminal of the first optocoupler 131. The low-level signal causes the first optocoupler 131 to turn on, and the LED inside the first optocoupler 131 emits light, triggering the phototransistor to turn on. After the first optocoupler 131 is turned on, the second power supply U2 transmits current through the first optocoupler 131 and sends the first signal to the address allocation module 2.

[0070] In some specific implementation methods, such as Figure 3 As shown, the first output unit 13 further includes a second filter component 133. The second filter component 133 is connected between the second power supply U2 and the first optocoupler 131. The second filter component 133 includes a fourth resistor 1331 and a second capacitor 1332. The first end of the fourth resistor 1331 is connected to the second power supply U2, and the second end of the fourth resistor 1331 is connected to the second output terminal of the first optocoupler 131. The first end of the second capacitor 1332 is connected to the second end of the fourth resistor 1331, and the second end of the second capacitor 1332 is grounded. The second filter component 133 is used to filter out noise from the output first signal.

[0071] In some specific implementation methods, such as Figure 4 As shown, the allocation completion module 3 includes:

[0072] The second input unit 31 is used to receive the second electrical signal from the address allocation module 2, and the second electrical signal is a high-level signal.

[0073] The second step-down unit 32 has its input terminal connected to the output terminal of the second input unit 31, and is used to reduce the voltage value of the second electrical signal;

[0074] The second output unit 33 has its input terminal connected to the output terminal of the second buck unit 32 and its output terminal connected to the MCU4. It is configured to continuously output a high level to the MCU4 and output a low level to the MCU4 according to the electrical signal output by the second buck unit 32.

[0075] MCU4 is used to detect the level change of the third electrical signal output by the second output unit 33.

[0076] With the above settings, the second electrical signal received by the second input power supply is a high-level signal. After being stepped down by the second step-down unit 32, it becomes a low-level signal. The second output unit 33 changes the third electrical signal output to the MCU according to the low level, so that the third electrical signal changes from a high level to a low level, so that the MCU can detect the change of the third electrical signal and determine that the address allocation module 2 has completed the ID allocation.

[0077] In some specific implementation methods, such as Figure 5 As shown, the second step-down unit 32 includes a third filter component 322 and a third switching component. The third switching component includes a second MOSFET 321. The gate of the second MOSFET 321 is coupled to the second input unit 31 through the third filter component 322. The source of the second MOSFET 321 is grounded, and the drain of the second MOSFET 321 is connected to the second output unit 33. The third filter component 322 is used to receive the second electrical signal from the address allocation module 2 and filter the second electrical signal.

[0078] With the above settings, after the address allocation module 2 completes the ID allocation, it sends a second electrical signal to the second input unit 31 of the allocation completion module 3. The second input unit 31 receives the second electrical signal and transmits it to the gate of the second MOS transistor 321. When the gate of the second MOS transistor 321 receives the second electrical signal, the gate voltage rises to or exceeds the threshold voltage of the MOS transistor, causing the second MOS transistor 321 to conduct. A low-impedance channel is formed between the source and the drain. After conduction, the current can flow freely, and the drain voltage of the second MOS transistor 321 drops rapidly to a low level. The second MOS transistor 321, after conduction, transmits the low-level signal from the drain to the second output unit 33.

[0079] In some specific embodiments, the input terminal of the third filter component 322 is connected to the second input unit 31, and the output terminal of the third filter component 322 is connected to the gate of the second MOS transistor 321. Specifically, the third filter component 322 includes a fifth resistor 3221, a sixth resistor 3222, and a third capacitor 3223. The first terminal of the fifth resistor 3221 is connected to the second input unit 31, the second terminal of the fifth resistor 3221 is connected to the first terminal of the sixth resistor 3222, and the second terminal of the sixth resistor 3222 is grounded. The first terminal of the third capacitor 3223 is connected to the second terminal of the sixth resistor 3222, and the second terminal of the third capacitor 3223 is grounded. The third filter component 322 is used to receive the second electrical signal from the second input unit 31 and filter out noise in the second electrical signal.

[0080] In some specific embodiments, the second output unit 33 includes a fourth switching component and a fourth filtering component 335. The input terminal of the fourth switching component is connected to the output terminal of the third switching component and is configured to turn on after receiving a signal from the third switching component. The output terminal of the fourth switching component is connected to the fourth filtering component 335, which is used to filter the output signal of the fourth switching component and output it to the MCU4.

[0081] Specifically, the fourth switching component includes a second optocoupler 331, a seventh resistor 332, and an eighth resistor 333. The first input terminal of the second optocoupler 331 is connected to the drain of the second MOSFET 321. The second input terminal of the second optocoupler 331 is connected to the first terminal of the seventh resistor 332. The second terminal of the seventh resistor 332 is connected to the third power supply U3. The first output terminal of the second optocoupler 331 is grounded. The second output terminal of the second optocoupler 331 is connected to the MCU and the first terminal of the eighth resistor 333. The second terminal of the eighth resistor 333 is connected to the fourth power supply U4.

[0082] With the above settings, after the second MOSFET 321 is turned on, its drain output low-level signal is transmitted to the first input terminal of the second optocoupler 331. The low-level signal causes the internal LED of the second optocoupler 331 to light up, triggering the phototransistor to turn on. After the optocoupler is turned on, the second power supply U2 transmits current through the seventh resistor 332, through the optocoupler, from the second input terminal to the second output terminal. The second output terminal of the second optocoupler 331 is connected to the MCU and the eighth resistor 333. When the second optocoupler 331 is turned on, the second output unit 33 sends a low-level signal to the MCU. After the MCU detects the change in the low-level signal, it determines that the address allocation module 2 has completed ID allocation.

[0083] In some specific embodiments, the second output unit 33 further includes a diode 334, the positive terminal of which is connected to the second terminal of the seventh resistor 332, and the negative terminal of which is connected to the gate of the second MOS transistor 321.

[0084] With the above settings, when the ID allocation module 1 receives the second level signal, the diode 334 ensures that the voltage at the second input terminal of the optocoupler is higher than the voltage at the first input terminal. This helps to stabilize the working state of the optocoupler and prevents false turn-on or false turn-off caused by signal fluctuations.

[0085] In some specific embodiments, the fourth filter component 335 includes a ninth resistor 3351 and a fourth capacitor 3352. The first end of the ninth resistor 3351 is connected to the second output terminal of the second optocoupler 331, and the second end of the ninth resistor 3351 is connected to the MCU. The first end of the fourth capacitor 3352 is connected to the second end of the ninth resistor 3351, and the second end of the fourth capacitor 3352 is grounded.

[0086] It should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A battery management system address assignment circuit, comprising: The application relates to an ID allocation module, which comprises an ID allocation module, an MCU, an address-to-be-allocated module and an allocation completion module. The ID allocation module is connected with the MCU at the input end and connected with the address-to-be-allocated module at the output end, and is configured to send a first electric signal to the address-to-be-allocated module after receiving an ID allocation signal of the MCU; The allocation completion module is connected with the address-to-be-allocated module at the input end and connected with the MCU at the output end, and is configured to receive a second electric signal of the address-to-be-allocated module completing ID transmission and output a third electric signal to the MCU after receiving the second electric signal; The MCU is configured to send the ID allocation signal to the ID allocation module, receive the third electric signal and judge whether the ID allocation is completed according to the third electric signal.

2. The battery management system address assignment circuit of claim 1, wherein, The ID allocation module comprises a first input unit, a first voltage reduction unit and a first output unit. The first input unit is used for receiving the ID allocation signal, and the ID allocation signal is a high-level initialization signal. The first voltage reduction unit is connected with the first input unit at the input end and is used for reducing the voltage value of the initialization high-level signal. The first output unit is connected with the first voltage reduction unit at the input end and connected with the address-to-be-allocated module at the output end, and is used for sending the first electric signal to the address-to-be-allocated module according to the electric signal output by the first voltage reduction unit. The electric signal received by the first input unit is a high-level signal, and the first voltage reduction unit is used for reducing the voltage value, so that the first output unit sends the first electric signal to the address-to-be-allocated module according to the reduced electric signal.

3. The battery management system address assignment circuit of claim 2, wherein, The first voltage reduction unit comprises a first MOS tube, the gate of the first MOS tube receives the high-level signal, the source of the first MOS tube is grounded, and the drain of the first MOS tube is connected with the first output unit. The first voltage reduction unit further comprises a first filter assembly, the input end of the first filter assembly is connected with the first input unit, and the output end of the first filter assembly is connected with the gate of the first MOS tube. The first filter assembly comprises a first resistor, a second resistor and a first capacitor, the first end of the first resistor is connected with the first input unit, the second end of the first resistor is connected with the first end of the second resistor, the second end of the second resistor is grounded, the first end of the first capacitor is connected with the second end of the first resistor, and the second end of the first capacitor is grounded.

4. The battery management system address assignment circuit of claim 3, wherein, The first output unit comprises a first optocoupler and a third resistor, the first end of the third resistor is connected with a first power supply, the second end of the third resistor is connected with the second input end of the first optocoupler, the first input end of the first optocoupler is connected with the drain of the first MOS tube, the first output end of the first optocoupler is connected with the address-to-be-allocated module, and the second output end of the first optocoupler is coupled with a second power supply.

5. The battery management system address assignment circuit of claim 4, wherein, The first output unit further comprises a second filter assembly, and the second filter assembly is connected between the second power supply and the first optocoupler. The second filter assembly comprises a fourth resistor and a second capacitor, the first end of the fourth resistor is connected with the second power supply, the second end of the fourth resistor is connected with the second output end of the first optocoupler, the first end of the second capacitor is connected with the second end of the fourth resistor, and the second end of the second capacitor is grounded.

6. The battery management system address assignment circuit of claim 1, wherein, The allocation completion module comprises a second input unit, a second voltage reduction unit and a second output unit. The second input unit is connected with the address-to-be-allocated module at the input end and connected with the MCU at the output end, and is configured to receive the second electric signal of the address-to-be-allocated module completing ID transmission. The second voltage reduction unit is connected with the second input unit at the input end and is used for reducing the voltage value of the second electric signal. The second output unit is connected with the second voltage reduction unit at the input end and connected with the MCU at the output end, and is configured to output the third electric signal to the MCU after receiving the second electric signal. The second input unit is configured to receive the second electrical signal of the address allocation module, and the second electrical signal is a high-level signal. The second voltage reduction unit is connected with the output end of the second input unit, and is configured to reduce the voltage value of the second electrical signal. The second output unit is connected with the output end of the second voltage reduction unit, and is configured to continuously output a high-level signal to the MCU and output a low-level signal to the MCU according to the electrical signal output by the second voltage reduction unit. The MCU is configured to detect the level change of the third electrical signal output by the second output unit.

7. The battery management system address assignment circuit of claim 6, wherein, The second voltage reduction unit comprises a second MOS tube, the gate of the second MOS tube is coupled with the second input unit, the source of the second MOS tube is grounded, and the drain of the second MOS tube is connected with the second output unit.

8. The battery management system address assignment circuit of claim 7, wherein, The second voltage reduction unit further comprises a third filter assembly, the input end of the third filter assembly is connected with the second input unit, and the output end of the third filter assembly is connected with the gate of the second MOS tube. The third filter assembly comprises a fifth resistor, a sixth resistor and a third capacitor, the first end of the fifth resistor is connected with the second input unit, the second end of the fifth resistor is connected with the first end of the sixth resistor, the second end of the sixth resistor is grounded, the first end of the third capacitor is connected with the second end of the sixth resistor, and the second end of the third capacitor is grounded.

9. The battery management system address assignment circuit of claim 7, wherein, The second output unit comprises a second optical coupler, a seventh resistor, an eighth resistor and a diode, the first input end of the second optical coupler is connected with the drain of the second MOS tube, the second input end of the second optical coupler is connected with the first end of the seventh resistor, and the second end of the seventh resistor is connected with a third power supply. The first output end of the second optical coupler is grounded, the second output end of the second optical coupler is connected with the MCU and the first end of the eighth resistor, and the second end of the eighth resistor is connected with a fourth power supply. The anode of the diode is connected with the second end of the seventh resistor, and the cathode of the diode is connected with the gate of the second MOS tube.

10. The battery management system address assignment circuit of claim 9, wherein, The second output unit further comprises a fourth filter assembly, and the fourth filter assembly is connected between the second optical coupler and the MCU. The fourth filter assembly comprises a ninth resistor and a fourth capacitor, the first end of the ninth resistor is connected with the second output end of the second optical coupler, the second end of the ninth resistor is connected with the MCU, the first end of the fourth capacitor is connected with the second end of the ninth resistor, and the second end of the fourth capacitor is grounded.

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