Power detection and self-calibration circuit and wireless communication equipment

Abstract

The utility model provides a power detection and self-calibration circuit and a wireless communication device in order to solve the problem that in the prior art, when ADC sampling data and signals are compared, signals need to be manually input through a signal source to be compared with antenna signals, and operation is inconvenient in an antenna receiving system. The circuit comprises an antenna signal processing module, a frequency source module, a selection switch, a self-calibration module and a main control chip FPGA. The circuit and the wireless communication equipment comprise the antenna signal processing module, the frequency source module, the selection switch and the self-calibration module, so that a self-check source does not need to be manually used for inputting a signal from an antenna input port for calibration, a test platform does not need to be additionally set up, and only the selection switch needs to be switched to the self-check source state through the FPGA, so that the self-calibration efficiency is greatly improved. Therefore, the antenna signal can be directly calibrated and detected, and the problems in the prior art are solved. When a plurality of antenna signal processing modules exist, the antenna signals are efficiently calibrated and detected through switching of the selection switch.

Description

TECHNICAL FIELD

[0001] The utility model belongs to wireless communication technical field especially relates to a power detection and self -calibrating circuit and wireless communication equipment. BACKGROUND

[0002] In the wireless communication field, power detection and automatic gain control are commonly used, since the signal power received by the antenna is unstable, the signal link gain is adjusted according to the antenna signal size, and the signal is too large to cause link saturation, which affects the signal quality, and the signal is too small to cause small gain, resulting in signal loss, so it is necessary to monitor the antenna signal power in real time and adjust the link gain.

[0003] The existing method for monitoring the antenna signal power and adjusting the link gain is to determine the input power according to the signal amplitude sampled by the ADC, and then adjust it using the attenuator. However, the comparison between the ADC sampling data and the signal requires manual input of the signal from the signal source to compare with the antenna signal, which is inconvenient to operate in the antenna receiving system. UTILITY MODEL CONTENTS

[0004] The utility model discloses to solve the problem that the comparison between the ADC sampling data and the signal needs manual input of the signal from the signal source to compare with the antenna signal in the prior art, and provides a power detection and self-calibrating circuit and wireless communication equipment.

[0005] The technical scheme adopted by the utility model is:

[0006] A power detection and self-calibrating circuit comprises:

[0007] At least one antenna signal processing module, each antenna signal processing module is used for processing antenna signal;

[0008] A frequency source module is used for generating a frequency signal;

[0009] A selection switch has the number of input terminals, which is the sum of the number of antenna signal processing modules and the number of frequency source modules; The input terminals of the selection switch are connected with the output terminals of each antenna signal processing module and the output terminals of the frequency source module respectively;

[0010] A self-calibrating module is connected with the output terminals of the selection switch; The output terminals of the self-calibrating module output the final signal;

[0011] A main control chip is connected with the control port of the selection switch and is used for controlling the switching of the state of the selection switch; The main control chip is connected with the self-calibrating module.

[0012] Further, the main control chip is FPGA.

[0013] Further, the antenna signal processing module comprises:

[0014] a filter A, an input end of the filter A receiving an antenna signal, the input end of the filter A being an input end of the antenna signal processing module;

[0015] an amplifier A, an input end of the amplifier A being connected with an output end of the filter A;

[0016] a power divider A, an input end of the power divider A being connected with an output end of the amplifier A;

[0017] a detector A, an input end of the detector A being connected with one output end of the power divider A, an output end of the detector A being an output end of the antenna signal processing module;

[0018] an amplifier B, an input end of the amplifier B being connected with another output end of the power divider A;

[0019] a filter B, an input end of the filter B being connected with an output end of the amplifier B, an output end of the filter B being another output end of the antenna signal processing module.

[0020] Further, the frequency source module comprises:

[0021] a self-checking source;

[0022] an amplifier C, an input end of the amplifier C being connected with an output end of the self-checking source;

[0023] an attenuator, an input end of the attenuator being connected with an output end of the amplifier C, an output end of the attenuator being an output end of the frequency source module.

[0024] Further, the self-calibration module comprises:

[0025] an amplifier D, an input end of the amplifier D being connected with an output end of the selection switch, the input end of the amplifier being an input end of the self-calibration module;

[0026] a digital attenuator, an input end of the digital attenuator being connected with an output end of the amplifier D, a control port of the digital attenuator being connected with the FPGA;

[0027] a power divider B, an input end of the power divider B being connected with an output end of the digital attenuator, one output end of the power divider B being one output end of the self-calibration module, for outputting a final signal;

[0028] a detector B, an input end of the detector B being connected with another output end of the power divider B, an output end of the detector B being another output end of the self-calibration module.

[0029] Further, the digital attenuator is HGC2001lP4 chip of Zhongke Haigao, which is used for realizing gain adjustment in the range of 0-31.5dB.

[0030] A wireless communication device comprises the power detection and self-calibration circuit.

[0031] The power detection and self-calibration circuit has the advantages that:

[0032] The power detection and self-calibration circuit and the wireless communication device disclosed by the utility model comprise an antenna signal processing module, a frequency source module, a selection switch, a self-calibration module and a master control chip FPGA. The calibration and detection of the antenna signal can be directly performed without manually inputting a signal from an antenna input port by using a self-checking source to perform calibration, and a test platform does not need to be additionally built. The problem that the operation is inconvenient in an antenna receiving system when manually inputting a signal by using a signal source to compare with the antenna signal when comparing the ADC sampling data with the signal is solved. In addition, when a plurality of antenna signal processing modules exist, the calibration and detection of the antenna signal can be efficiently performed through the switching of the selection switch. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0034] Figure 1 The circuit diagram of the power detection and self-calibration circuit disclosed by the present embodiment. DETAILED DESCRIPTION

[0035] In the description of the utility model, it is understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the utility model.

[0036] The following disclosure provides many different embodiments or examples for implementing various structures of this invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this invention.

[0037] The following is in conjunction with the appendix Figure 1 The embodiments of the utility model will be described in detail.

[0038] The power detection and self-calibration circuit disclosed in this embodiment includes the following modules and components: two antenna signal processing modules, a frequency source module, a selection switch, a self-calibration module, and an FPGA; in addition to the power detection and self-calibration circuit, this embodiment also provides two analog-to-digital converter chips, namely ADC1 and ADC2; the functions and connection relationships between the above modules and components are described as follows:

[0039] Each antenna signal processing module is used to process antenna signals.

[0040] Frequency source module: The frequency source module is used to generate frequency signals.

[0041] Select switch: Use 3 switches. The control ports of the 3 switches are connected to the FPGA, and the FPGA controls the state of the 3 switches. The input terminals of the 3 switches are connected to the output terminals of the two antenna signal processing modules and the output terminal of the frequency source module, respectively.

[0042] Self-calibration module; the output of the self-calibration module is connected to the output of the selector switch.

[0043] FPGA: The FPGA is connected to the selector switch control port to control the switching of the selector switch state; the FPGA is also connected to the self-calibration module.

[0044] In this embodiment, each antenna signal processing module contains the same components. To distinguish between the two different antenna signal processing modules, the component names are used for differentiation. The first antenna signal processing module includes the following components: filter A, amplifier A, power divider A, detector A, amplifier B, and filter B. The functions and connections between the above components are described as follows:

[0045] Filter A: The input terminal of filter A receives the antenna signal and is also the input terminal of the antenna signal processing module.

[0046] Amplifier A: The input terminal of amplifier A is connected to the output terminal of filter A.

[0047] Power divider A: The input terminal of power divider A is connected to the output terminal of amplifier A.

[0048] Detector A: The input of detector A is connected to one output of power divider A. The output of detector A is the output of the antenna signal processing module; the output of detector A is connected to the input of ADC1, and the output of ADC1 is connected to the FPGA, which analyzes the data input from ADC1.

[0049] Amplifier B: The input of amplifier B is connected to the other output of power divider A.

[0050] Filter B: The input of filter B is connected to the output of amplifier B, and the output of filter B is another output of the antenna signal processing module.

[0051] The second antenna signal processing module includes the following components: filter A1, amplifier A1, power divider A1, detector A1, amplifier B1, and filter B1. The functions and connections between these components are described below:

[0052] Filter A1: The input terminal of filter A1 receives the antenna signal and is the input terminal of the antenna signal processing module.

[0053] Amplifier A1: The input terminal of amplifier A1 is connected to the output terminal of filter A1.

[0054] Power divider A1: The input terminal of power divider A1 is connected to the output terminal of amplifier A1.

[0055] Detector A1: The input of detector A1 is connected to one output of power divider A1. The output of detector A1 is the output of the antenna signal processing module; the output of detector A1 is connected to the input of ADC2, and the output of ADC2 is connected to the FPGA. The FPGA analyzes the data input from ADC2.

[0056] Amplifier B1: The input terminal of amplifier B1 is connected to the other output terminal of power divider A1.

[0057] Filter B1: The input of filter B1 is connected to the output of amplifier B1, and the output of filter B1 is another output of the antenna signal processing module.

[0058] In this context, filter A1 in the second antenna signal processing module corresponds to filter A in the second antenna signal processing module.

[0059] Amplifier A1 in the second antenna signal processing module corresponds to amplifier A in the second antenna signal processing module.

[0060] The power divider A1 in the second antenna signal processing module corresponds to the power divider A in the second antenna signal processing module.

[0061] Detector A1 in the second antenna signal processing module corresponds to detector A in the second antenna signal processing module.

[0062] Amplifier B1 in the second antenna signal processing module corresponds to amplifier B in the second antenna signal processing module.

[0063] The filter B1 in the second antenna signal processing module corresponds to the filter B in the second antenna signal processing module.

[0064] The frequency source module includes the following components: a self-test source, amplifier C, and an attenuator. The functions and connections between these components are described below:

[0065] Self-test source: In this embodiment, the self-test source model is HMC835LP6GE.

[0066] Amplifier C: The input terminal of amplifier C is connected to the output terminal of the self-test source.

[0067] Attenuator: The input terminal of the attenuator is connected to the output terminal of amplifier C, and the output terminal of the attenuator is the output terminal of the frequency source module.

[0068] The self-calibration module includes: amplifier D, digitally controlled attenuator, power divider B, and detector B. The functions and connections between these components are described below:

[0069] Amplifier D: The input terminal of amplifier D is connected to the output terminal of the selector switch, and the input terminal of amplifier D is the input terminal of the self-calibration module.

[0070] Digitally controlled attenuator: The input terminal of the digitally controlled attenuator is connected to the output terminal of the amplifier D; the control port of the digitally controlled attenuator is connected to the FPGA, and the FPGA controls the attenuation value of the digitally controlled attenuator; the digitally controlled attenuator is the HGC2001lP4 chip of Zhongke Haigao, which is used to realize gain adjustment in the range of 0-31.5dB.

[0071] Power divider B: The input of power divider B is connected to the output of the digitally controlled attenuator. One output of power divider B is an output of the self-calibration module, used to output the final signal.

[0072] Detector B: The input of detector B is connected to the other output of power divider B. The output of detector B is the other output of the self-calibration module.

[0073] This embodiment also discloses a wireless communication device, which includes the power detection and self-calibration circuit disclosed in this embodiment.

[0074] The working principle of the power detection and self-calibration circuit disclosed in this embodiment is described in detail below:

[0075] Two antenna signals are input to two separate antenna signal processing modules. After filtering and amplification, signal monitoring is performed, and the signal is split into two paths. One path enters detector A (taking the first antenna signal processing module as an example) and is then amplified by amplifier A (taking the first antenna signal processing module as an example) to obtain a voltage value. This voltage value has a linear relationship with the signal power. The other path undergoes further filtering and amplification, and then passes through a selector switch. The self-test frequency source is input through the selector switch. After passing through the selector switch, the signal enters detector B to detect the signal power. Here, the power of the frequency source module and the antenna signal processing module is compared to accurately detect the input power of the antenna signal. The advantage here is that it eliminates the need for manual calibration by inputting a signal from the antenna input port using a self-test source, and it also eliminates the need to build a separate test platform. Simply switching the selector switch to self-test source mode via the FPGA allows for direct calibration and detection of the antenna signal. The signal enters the self-calibration module, undergoes amplification and attenuation processing, passes through power divider B, and outputs the final signal on one path. The other path enters detector B to obtain the final signal voltage value, which also has a linear relationship with the signal power.

[0076] The technical details of the power detection and self-calibration circuit disclosed in this embodiment are further described below:

[0077] The radio frequency signal obtained without passing through the detector is an analog signal containing a carrier wave, which cannot be transmitted into the FPGA for analysis. The analog signal containing the carrier wave is converted into a carrier-free voltage signal by the detector, and can only be transmitted into the FPGA for analysis after passing through ADC1 or ADC2 analog-to-digital conversion.

[0078] The amplifier and attenuator connected after the self-test source are used to match the strength of the antenna signal. This means that the antenna signal, after passing through filtering, amplification, and power divider devices, experiences signal loss. The amplifier and attenuator connected after the self-test source match this loss. For example, if the antenna signal is -30dBm, but the signal detected before the selector switch is only -40dBm, the link has a 10dB loss. The amplifier and attenuator connected after the self-test source match this loss, ensuring a total loss of 10dB. The ADC data obtained in self-test mode is compared with the ADC data obtained in antenna signal mode. When switching self-test modes, the attenuator connected to the self-test source changes, and the ADC data also changes, resulting in a linear relationship between signal strength and ADC data. Substituting the ADC data obtained in antenna signal mode into the linear relationship in self-test mode allows for an accurate determination of the antenna signal power.

[0079] FPGA, as the main control chip, has the advantages of flexible development and high speed. In the power detection and self-calibration circuit disclosed in this embodiment, FPGA has three functions: receiving and analyzing the voltage values ​​input from ADC1 and ADC2, controlling the switching of the selection switch state, and controlling the attenuation value of the digitally controlled attenuator.

Claims

1. A power detection and self-calibration circuit, characterized by, The power detection and self-calibration circuit comprises: at least one antenna signal processing module; each of the antenna signal processing modules is used for processing an antenna signal; a frequency source module; the frequency source module is used for generating a frequency signal; a selection switch; the number of input terminals of the selection switch is the sum of the number of the antenna signal processing modules and the number of the frequency source module; the input terminals of the selection switch are respectively connected with the output terminals of each of the antenna signal processing modules and the output terminal of the frequency source module; a self-calibration module; the input terminal of the self-calibration module is connected with the output terminal of the selection switch; the output terminal of the self-calibration module outputs a final signal; a master control chip; the master control chip is connected with the control terminal of the selection switch and is used for controlling the switching of the state of the selection switch; the master control chip is connected with the self-calibration module.

2. The power detection and self-calibration circuit of claim 1, wherein, The master control chip is an FPGA.

3. The power detection and self-calibration circuit of claim 1, wherein, The antenna signal processing module comprises: a filter A; the input terminal of the filter A receives an antenna signal, and the input terminal of the filter A is the input terminal of the antenna signal processing module; an amplifier A; the input terminal of the amplifier A is connected with the output terminal of the filter A; a power divider A; the input terminal of the power divider A is connected with the output terminal of the amplifier A; a detector A; the input terminal of the detector A is connected with one of the output terminals of the power divider A; and the output terminal of the detector A is the output terminal of the antenna signal processing module; an amplifier B; the input terminal of the amplifier B is connected with the other output terminal of the power divider A; a filter B; the input terminal of the filter B is connected with the output terminal of the amplifier B, and the output terminal of the filter B is the other output terminal of the antenna signal processing module.

4. The power detection and self-calibration circuit of any of claims 1-3, wherein, The frequency source module comprises: a self-checking source; an amplifier C; the input terminal of the amplifier C is connected with the output terminal of the self-checking source; an attenuator; the input terminal of the attenuator is connected with the output terminal of the amplifier C, and the output terminal of the attenuator is the output terminal of the frequency source module.

5. The power detection and self-calibration circuit of claim 2, wherein, The self-calibration module comprises: an amplifier D; the input terminal of the amplifier D is connected with the output terminal of the selection switch, and the input terminal of the amplifier is the input terminal of the self-calibration module; a digital attenuator; the input terminal of the digital attenuator is connected with the output terminal of the amplifier D; the control terminal of the digital attenuator is connected with the FPGA; a power divider B; the input terminal of the power divider B is connected with the output terminal of the digital attenuator; one of the output terminals of the power divider B is one of the output terminals of the self-calibration module and is used for outputting a final signal; a detector B; the input terminal of the detector B is connected with the other output terminal of the power divider B; the output terminal of the detector B is the other output terminal of the self-calibration module.

6. The power detection and self-calibration circuit of claim 5, wherein, The digital attenuator is an HGC2001lP4 chip of Zhongke Haigao, which is used for realizing gain adjustment in the range of 0-31.5 dB.

7. A wireless communication device, comprising: The power detection and self-calibration circuit comprises: the power detection and self-calibration circuit according to any one of claims 1-6.

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