Image sensor and electronic device
By forming regions with different doping types and concentrations around the trenches of the image sensor, the problem of electron transport being affected is solved, electron transport efficiency is improved, tailing phenomenon is reduced, and the performance of the image sensor is enhanced.
Patent Information
- Application Number
- CN202422916081.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2034-11-27
AI Technical Summary
In the manufacturing process of CMOS image sensors, electron transport is affected, making it difficult for electrons to be transferred smoothly through the channel to the memory node, resulting in a trailing phenomenon.
In the fabrication process of an image sensor, two regions with the same doping type but different doping concentrations are formed on the periphery of the trench. By adjusting the electron transport modulation region, the electron transport efficiency is improved.
Effective adjustment of electron transmission reduces trailing and improves the performance and efficiency of image sensors.
Smart Images
Figure CN223798587U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of image acquisition technology, and in particular relates to an image sensor and a corresponding electronic device. Background Technology
[0002] Image sensors are a crucial component of digital cameras. Based on the different components, they can be divided into two main categories: CCD (Charge Coupled Device) and CMOS (Complementary Metal-Oxide Semiconductor).
[0003] With the continuous development of CMOS integrated circuit manufacturing processes, especially the design and manufacturing processes of CMOS image sensors (CIS), CMOS image sensors have gradually replaced CCD image sensors as the mainstream. Compared with CCD, CMOS image sensors have advantages such as low voltage, low power consumption, low cost, and high integration, and have important application value in fields such as machine vision, consumer electronics, high-definition surveillance, and medical imaging.
[0004] However, in the manufacturing process of CIS, there are various ion implantation processes, and different processes can also interact with each other due to factors such as processing temperature. This may affect the potential distribution and charge transport, making it difficult for electrons to transfer smoothly through the channel to the storage node, resulting in the LAG tailing phenomenon.
[0005] Therefore, it is essential to provide an image sensor or electronic device that can effectively transmit electrons and design manufacturing processes in existing technologies.
[0006] The above background information is provided solely for the purpose of clearly and completely explaining the technical solutions of this utility model and facilitating understanding by those skilled in the art. It should not be assumed that these solutions are known to those skilled in the art simply because they have been described in the background section of this utility model. Utility Model Content
[0007] In view of the shortcomings of the prior art described above, the purpose of this utility model is to provide an image sensor and its preparation method, as well as an electronic device, to solve the problems of electronic transmission being affected in the prior art.
[0008] To achieve the above and other related objectives, this utility model provides a method for fabricating an image sensor, the method comprising:
[0009] A semiconductor substrate is provided, the semiconductor substrate including a device functional layer of a first doping type;
[0010] A first trench is formed in the functional layer of the device from a first surface of the semiconductor substrate;
[0011] A transmission modulation region is prepared on the periphery of the first trench, wherein:
[0012] The transmission modulation region includes at least a first region and a second region of a first doping type that are adjacent to each other, the second region being close to the first surface and the doping concentration of the first region being greater than that of the second region;
[0013] A semiconductor device is fabricated in the device functional layer from the first surface of the semiconductor substrate, the semiconductor device including a photoelectric conversion doped region of a second doping type different from the first doping type.
[0014] This utility model also provides an image sensor, which can be prepared by the preparation method described above, or by other methods. The image sensor includes:
[0015] A semiconductor substrate, the semiconductor substrate including a device functional layer of a first doping type;
[0016] A semiconductor device, located in the functional layer of the device, the semiconductor device including a photoelectric conversion doped region having a second doping type different from the first doping type;
[0017] A first trench is disposed in the functional layer of the device, and its periphery includes a transmission modulation region; wherein:
[0018] The transmission modulation region includes at least a first region and a second region of a first doping type, wherein the second region is closer to the first surface and the doping concentration of the first region is greater than that of the second region.
[0019] This invention also provides an electronic device, including an image sensor as described in any of the above embodiments.
[0020] As described above, the image sensor and electronic device of this application form at least two different regions with the same doping type but different doping concentrations on the periphery of the first trench, which not only protect the trench sidewalls and bottom but also effectively adjust the electron transport. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 The diagram shows the basic structure of an image sensor system.
[0023] Figure 2 The diagram shows a pixel circuit made of an image sensor.
[0024] Figure 3 The flowchart shown is a process for preparing the image sensor in an embodiment of this application.
[0025] Figure 4 The diagram shown illustrates the semiconductor substrate provided in the fabrication of the image sensor according to an embodiment of this application.
[0026] Figure 5 The diagram shown is a schematic diagram of the formation of the first mask layer in the fabrication of the image sensor according to an embodiment of this application.
[0027] Figure 6 The diagram shown illustrates the formation of the first trench during the fabrication of the image sensor according to an embodiment of this application.
[0028] Figure 7 The diagram shown is a schematic diagram of the formation of a surface oxide dielectric layer during the fabrication of an image sensor according to an embodiment of this application.
[0029] Figure 8 The diagram shown is a schematic diagram of the formation of the first region during the fabrication of the image sensor according to an embodiment of this application.
[0030] Figure 9 The diagram shown is a schematic diagram of the formation of the second mask layer in the fabrication of the image sensor according to an embodiment of this application.
[0031] Figure 10 The diagram shown is a schematic diagram of the formation of the second region during the fabrication of the image sensor according to an embodiment of this application.
[0032] Figure 11 The illustration shows the formation of the exposed first trench during the fabrication of the image sensor according to an embodiment of this application.
[0033] Figure 12 The diagram shown is a schematic diagram of the formation of an isolation material layer during the fabrication of an image sensor according to an embodiment of this application.
[0034] Figure 13 The diagram shown is a schematic diagram of the formation of the first isolation structure during the fabrication of the image sensor according to an embodiment of this application.
[0035] Figure 14 The diagram shown is a schematic diagram of the formation of the third mask layer in the fabrication of the image sensor according to an embodiment of this application.
[0036] Figure 15 The diagram illustrates the formation of photoelectric conversion doped regions during the fabrication of an image sensor according to an embodiment of this application.
[0037] Figure 16 The diagram shown is a schematic diagram of the formation of an isolation region during the fabrication of an image sensor according to an embodiment of this application.
[0038] Figure 17 The diagram shown is a schematic diagram of the formation of the second isolation structure during the fabrication of the image sensor according to an embodiment of this application.
[0039] Figure 18 The diagram shown is a pixel circuit schematic of a pixel unit of an image sensor in an embodiment of this application.
[0040] Figure 19 Displayed as Figure 18 The example shown is a schematic diagram of the layout design corresponding to the pixel circuit.
[0041] Figure 20 and Figure 21 The diagram shown is a simulation of the potential of the electron transfer process in the design and comparative design of this application.
[0042] Component designation explanation
[0043] 101-Semiconductor substrate; 102-First mask layer; 103-First trench; 104-Surface oxide dielectric layer; 105-First region; 106-Second mask layer; 107-Second region; 108-Transmission modulation region; 109-Isolation initial material layer; 110-First isolation structure; 111-Third mask layer; 112-Photoelectric conversion doped region; 113-Fourth mask layer; 114-Isolation region; 115-Transistor gate; 116-Interconnect structure layer; 117-Second isolation structure; 118-Passivation layer; 119-Gateway; 120-Color filter; 121-Microlens. Detailed Implementation
[0044] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.
[0045] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0046] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments. For ease of explanation in the detailed description of embodiments of the present invention, cross-sectional views illustrating the device structure may be partially enlarged without adhering to general scale; these schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, three-dimensional spatial dimensions of length, width, and depth should be included.
[0047] For ease of description, spatial relation terms such as "below," "below," "lower than," "below," "above," and "above" may be used herein to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more layers in between. The described structure of a first feature "above" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0048] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0049] Figure 1 The diagram shows a basic block structure of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. A functional logic unit is connected to the readout circuit, and the readout circuit and control circuit are connected to a status register to control the pixel array. The pixel array includes multiple pixels (P1, P2, P3) arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx). The pixel signals output by the pixel array are output to the readout circuit via column lines. In specific implementations, the readout circuit may include an analog-to-digital converter (ADC) and other circuits. In some applications, after the pixels acquire image data, they are read out using the readout mode specified by the status register and then transmitted to the functional logic unit.
[0050] In some applications, the status register may contain a programmed selection system to determine whether the readout system uses rolling shutter or global shutter exposure. The functional logic unit may store raw image data or image data after image processing. In some implementations, the readout circuitry may read one row of image data at a time along the readout column lines; other methods may also be used. The operation of the control circuitry can be determined by the current settings in the status register. For example, the control circuitry generates a shutter signal to control image acquisition. In some applications, this shutter signal may be a global shutter signal, allowing all pixels in the pixel array to acquire their image data simultaneously through a single acquisition window. In other applications, this shutter signal may be a rolling shutter signal, allowing pixels in each row of the pixel array to be continuously exposed and read through the acquisition window.
[0051] Figure 2 This diagram illustrates a pixel unit in an image sensor. As shown, each pixel unit includes a photoelectric conversion element (e.g., a photodiode) and pixel circuitry (shown as a transistor within the dashed box). The photodiode can be a buried photodiode (PPD) used in current image sensors. In one application example, the pixel circuitry includes a reset transistor (RST), a source follower transistor (SF), and a pixel select transistor (RS), connected to, for example... Figure 2 The diagram shows a transfer transistor (TX) and a photodiode. In some applications, the pixel circuitry is stacked, including a reset transistor, a source follower transistor, and a pixel select transistor on a first circuit chip, and a transfer transistor on a second circuit chip, where the photodiode is connected to other transistors on the first circuit chip via the transfer transistor. In further applications, the pixel circuitry may also include a gain control transistor (DCG) connected between the floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photocharge in response to incident light during exposure. The transfer transistor is connected to a transfer signal that controls the transfer transistor to transfer the accumulated charge in the photoelectric conversion element to the floating diffusion region. The reset transistor is connected between the power supply voltage and the floating diffusion region, and in response to a reset signal, resets the sensor pixel circuitry (e.g., discharges or charges the floating diffusion region and the photodiode to the current voltage). The floating diffusion region is connected to the gate of the source follower transistor, which is connected between the power supply voltage and the pixel select transistor, responding to and outputting the potential of the floating diffusion region. The pixel select transistor is connected to the source follower transistor and the bit line, and in response to a pixel select control signal, performs pixel selection readout and outputs it to the readout column.
[0052] However, in the manufacturing process of CIS, there are various ion implantation processes, and these processes can interact due to factors such as processing temperature, potentially affecting the potential distribution and causing difficulties in electron transport. Electrons may struggle to transfer smoothly through the channel to the storage node, resulting in a tailing phenomenon. This invention effectively improves these problems by designing the structure and process of the image sensor.
[0053] The following will describe the process in detail with reference to the embodiments.
[0054] Example 1:
[0055] Please see Figure 3 As shown, this embodiment provides a method for fabricating an image sensor. Figure 3 The flowchart shown is for the preparation method, which includes the following steps:
[0056] S1: Provide a semiconductor substrate, the semiconductor substrate including a device functional layer of a first doping type;
[0057] S2: A first trench is formed in the functional layer of the device from the first surface of the semiconductor substrate;
[0058] S3: A transmission modulation region is prepared on the periphery of the first trench, wherein:
[0059] The transmission modulation region includes at least a first region and a second region of a first doping type that are adjacent to each other, the second region being close to the first surface and the doping concentration of the first region being greater than that of the second region;
[0060] S4: A semiconductor device is fabricated in the device functional layer from the first surface, the semiconductor device including a photoelectric conversion doped region of a second doping type different from the first doping type.
[0061] In the image sensor and its fabrication in this embodiment, at least two distinct regions with the same doping type but different doping concentrations are formed on the periphery of the first trench. This protects the trench sidewalls and bottom while effectively regulating electron transport. It should be noted that the fabrication sequence in the above steps, corresponding to existing processes, can be modified according to actual needs without affecting the beneficial effects of this application.
[0062] The fabrication of the image sensor of this application will be described in detail below with reference to specific embodiments.
[0063] First, such as Figure 4As shown, in step S1, a semiconductor substrate 101 is provided. The semiconductor substrate 101 includes a device functional layer of a first doping type (not specifically shown in the figure). In this embodiment, the first doping type is described as P-type. Of course, in other examples, it can also be N-type according to actual needs.
[0064] Specifically, the semiconductor substrate 101 has a first surface 101a (upper surface) and a second surface 101b (lower surface). The semiconductor substrate 101 can be a structure composed of a single layer of material, including but not limited to a silicon substrate. The material can be monocrystalline silicon, monocrystalline germanium, polycrystalline silicon, amorphous silicon, or silicon-germanium compounds, etc. Of course, the semiconductor substrate 101 can also be silicon-on-insulator (SOI), etc. In addition, the semiconductor substrate 101 can also have N-type doped or P-type doped regions to meet practical requirements.
[0065] Furthermore, the semiconductor substrate 101, serving as the substrate for the image sensor, can also be a multilayer structure, such as including a semiconductor substrate and an epitaxial layer formed on the surface of the semiconductor substrate. The epitaxial layer serves as a functional layer for the device, enabling the fabrication of the image sensor device. In other embodiments, the semiconductor substrate 101 can be any structure used in the field of image sensors for fabricating the functional areas of the image sensor. The photosensitive element, individual transistors, and interconnect wiring of a CMOS image sensor can be fabricated based on the semiconductor substrate 101.
[0066] In one example, the device functional layer may be part of the semiconductor substrate 101, for example, it may be an epitaxial layer (EPI) formed on a semiconductor substrate (such as a silicon substrate). The epitaxial layer may be a P-type silicon epitaxial layer, which may be formed directly by an epitaxial process or by other methods using existing processes. In this case, the semiconductor substrate and the epitaxial layer constitute the semiconductor substrate 101.
[0067] In some implementations, the functional regions (including semiconductor devices) of the image sensor are fabricated within the device functional layer. In other examples, the semiconductor substrate 101 can be considered as a doped substrate, including the device functional layer of a first doping type, in which case the functional regions of the image sensor can be fabricated within the semiconductor substrate 101. Of course, if necessary, the required structure of the image sensor can also be fabricated within the semiconductor substrate or other material layers. Back-illuminated or front-illuminated image sensors can be fabricated based on this semiconductor substrate and device functional layer; this embodiment uses a back-illuminated image sensor as an example.
[0068] Next, as Figures 5-6 As shown, in step S2, a first trench 103 is prepared in the device functional layer from the first surface 101a of the semiconductor substrate 101.
[0069] In one example, the method for forming the first trench 103 may be:
[0070] First, a first mask layer 102 is formed on the first surface 101a of the semiconductor substrate 101, such as Figure 5 As shown; then etching is performed based on the first mask layer 102 to form the first trench 103, as follows. Figure 6 As shown.
[0071] Optionally, the material of the first mask layer 102 includes, but is not limited to, a hard mask layer, such as silicon nitride.
[0072] Next, as Figures 7-10 As shown, in step S3, a transmission modulation region 108 is prepared on the periphery of the first trench 103, wherein:
[0073] The transmission modulation region 108 includes at least a first region 105 and a second region 107 of a first doping type, which are adjacent to each other. The second region 107 is close to the first surface and the doping concentration of the first region 105 is greater than that of the second region 107.
[0074] As an example, such as Figure 7 As shown, after forming the first trench 103, the following steps are also included:
[0075] A surface oxide dielectric layer 104 is formed on the sidewalls and bottom of the first trench 103. This can be achieved by forming the surface oxide dielectric layer 104 on the sidewalls and bottom of the first trench 103 based on the first mask layer 102 while retaining the first mask layer 102. The transmission modulation region 108 is formed based on the first trench and the surface oxide dielectric layer.
[0076] Optionally, the surface oxide dielectric layer 104 includes, but is not limited to, a silicon oxide layer on the trench surface formed by a thermal oxidation process, to facilitate subsequent ion implantation processes based on the surface oxide dielectric layer 104.
[0077] In one example, a transmission modulation region 108 is formed on the periphery of the first trench 103 before forming the photoelectric conversion doped region. The step of forming the transmission modulation region 108 on the periphery of the first trench 103 includes:
[0078] First, such as Figure 7 As shown, a first mask layer 102 is formed on the first surface of a semiconductor substrate 101. In this example, the first mask layer 102 is the mask layer used when forming the first trench 103.
[0079] Next, as Figure 8 As shown, a first ion implantation is performed from the first surface 101a of the semiconductor substrate 101 based on the first mask layer 102 to form a first region 105 at least corresponding to the bottom of the first trench 103.
[0080] In this example, after forming the first mask layer 102 on the first surface 101a, the device functional layer is first etched based on the first mask layer 102 to form the first trench 103, and then the first region 105 is prepared based on the first mask layer 102 using a self-aligned ion access process. In addition, when a surface oxide dielectric layer 104 is present, the surface oxide dielectric layer 104 is also prepared based on the first mask layer 102, which can improve the process preparation accuracy and save costs.
[0081] Next, as Figure 9 As shown, a second mask layer 106 is formed on the first surface 101a of the semiconductor substrate 101;
[0082] Finally, as Figure 10 As shown, a second ion implantation is performed from the first surface 101a of the semiconductor substrate 101 based on the second mask layer 106 to form a second region 107 at least corresponding to the sidewall of the first trench 103.
[0083] As an example, such as Figure 9 As shown, the step of forming the second mask layer 106 on the first surface includes:
[0084] A second mask material layer (not shown) is formed on a semiconductor substrate on which the first mask layer 102 is formed; the second mask material layer is patterned to obtain a second mask layer 106, which includes a second mask opening corresponding to the first trench 103 and second mask units 106a located between the second mask openings, wherein:
[0085] The first mask layer 102 includes a first mask opening corresponding to the first trench 103 and a first mask unit 102a located between the first mask openings. A second mask unit 106a extends from the first mask unit 102a to the first trench 103 and has an overlapping area with the sidewall of the first trench 103. Figure 9 As shown by the dashed ellipse, an example of an overlapping region is illustrated. The second mask unit 106a extends a distance d from the first mask unit 102a, thereby enabling the second mask opening to be reduced relative to the first trench 103 based on this distance. This provides conditions for subsequent ion implantation to form the second region 107. In this example, the formed second region 107 has a gap with the first surface 101a of the semiconductor substrate.
[0086] As an example, such as Figure 10 As shown, the steps for performing the second ion implantation based on the second mask layer include:
[0087] Ion implantation is performed in the first to fourth directions at first to fourth angles relative to the normal of the semiconductor substrate 101, respectively, to form first to fourth sub-regions on the periphery of the first trench 103, such that the first to fourth sub-regions constitute the second region. In one example, the first to fourth directions correspond to the fabrication of the transmission modulation region regions of the four sidewalls of the first trench.
[0088] Specifically, Figure 10 The image shows ion implantation in two directions corresponding to two different angles; further details can be found in [reference needed]. Figure 19 As shown, ion implantation can be performed in four directions corresponding to four angles, which can realize the formation of the transport modulation region 108 on the periphery of the same first trench 103, and can simultaneously realize the formation of the transport modulation region 108 on the sidewall of different first trenches 103, which can simplify the process and improve the process stability.
[0089] In one example, the doping concentration of the second region 107 in the transmission modulation region 108 is lower than the doping concentration of the first region 105. Optionally, the ion doping concentration of the second region 107 is between 20% and 80% of the ion doping concentration of the first region 105, such as 30%, 40%, 50%, or 60% of the ion doping concentration of the first region 105. For example, the ion doping concentration of the first region 105 is 3e. 13 The ion doping concentration in the second region 105 can be 1e 13 1.5e 13 2e 13 Furthermore, the doping energy of the first region 105 can be higher than that of the second region 107, such that the second region 107 is located on and adjacent to the first region 105. In this example, both the first and second regions are p-type ion doped.
[0090] In one example, the maximum lateral width of the second region 107 in the direction parallel to the first surface of the semiconductor substrate is smaller than the maximum lateral width of the first region 105 in that direction. In a further example, the maximum lateral width of the second region in the direction parallel to the first surface of the semiconductor substrate is smaller than the minimum lateral width of the first region in that direction. This width-based design facilitates potential regulation.
[0091] like Figures 11-13 As shown, in one example, after forming the transmission modulation region 108, the step further includes: forming a filling material layer in the first trench 103 to obtain the first isolation structure 110.
[0092] The specific steps may be as follows: First, remove the mask layer forming the transmission modulation region 108 to expose the surface oxide dielectric layer 104 of the inner wall of the first trench 103, such as... Figure 11 As shown; next, an initial material layer 109 is deposited on the first trench 103 and the surrounding semiconductor substrate, including but not limited to a silicon oxide layer, such as... Figure 12 As shown; finally, the initial material layer 109 is chemically mechanically polished (CMP) to obtain the first isolation structure 110.
[0093] Next, as Figures 14-15 As shown, step S4 is performed: a semiconductor device is fabricated in the device functional layer from the first surface 101a of the semiconductor substrate 101, including a photoelectric conversion doped region 112 of a second doping type different from the first doping type; in this embodiment, the second doping type is described as N-type.
[0094] Specifically, the semiconductor device (not shown in the figure) may include photoelectric conversion elements and the corresponding transistors of the pixel circuit of the image sensor. The photoelectric conversion elements realize photoelectric conversion, and the photoelectric conversion doped region 112 is a component of the photoelectric conversion elements. Of course, it may also include other CIS pixel circuit devices in the prior art to realize the functions of image acquisition and subsequent imaging. For example, the pixel circuit may include transmission transistors, etc. See [reference needed]. Figure 17 As shown, the transmission control gate 115 is illustrated.
[0095] In one example, the steps of forming the photoelectric conversion doped region 112 of the second doping type include:
[0096] First, after the transmission modulation region 108 is formed, second type of ion implantation of the device functional layer is performed from the first surface 101a of the semiconductor substrate 101 to form an initial doped region.
[0097] Specifically, a third mask layer 111 may be formed first on the first surface of the semiconductor substrate on which the first isolation structure 110 is formed, and then ion implantation may be performed based on the third mask layer to form an initial doped region.
[0098] Next, the initial doped region is heat-treated to form the photoelectric conversion doped region 112.
[0099] Specifically, the heat treatment annealing temperature is between 900℃ and 1200℃. For example, the heat treatment temperature for the initial doped region can be 1050℃, 1100℃, or 1150℃.
[0100] In this example, after the formation of the transmission modulation region 108, a thermal annealing process is performed on the initial doped region. Since the concentration of the first doped type ions in the second region 107 is low, the impact on the initial doped region of the second doped type during thermal treatment is smaller than that on the lower first region 105. This results in less diffusion of the first type of doped ions near the front side of the semiconductor substrate, which is beneficial for overcoming the transmission barrier. This reduces the barrier on the charge transfer path below the transmission control gate, thereby improving transmission efficiency. Furthermore, the first region 105 with a higher doping concentration is formed at least at the bottom of the first trench 103, which can repair bottom defects during the etching process of the first trench. Since there are many defects at the bottom of the trench during etching, this process can significantly modify the etching defects of the first trench. That is, through the formation of the first transmission modulation region 108, based on the first and second regions with different doping concentrations, trench etching defects are significantly repaired while reducing the impact of the diffusion of doped ions of opposite doping types on the charge transport barrier during the thermal treatment process of the photoelectric conversion doped region 112 formation, thereby improving transmission efficiency, enhancing transistor performance, and reducing tailing.
[0101] Optionally, the bottom of the transmission modulation region 108 is closer to the first surface 101a than the bottom of the photoelectric conversion doped region 112, and the first isolation structure 110 formed by the first trench can be a shallow trench isolation structure (STI).
[0102] Please see Figure 16 As shown, in one example, the fabrication of the image sensor also includes the step of fabricating an isolation region 114 in the device functional layer from the first surface 101a of the semiconductor substrate 101.
[0103] Optionally, the isolation region 114 can be an ion-doped isolation region with a doping type opposite to that of the photoelectric conversion doping region 112, thereby achieving the isolation function. In this embodiment, the isolation region 114 is selected as a P-type doped isolation region with the same doping type as the transmission modulation region 108 and the opposite doping type to that of the photoelectric conversion doping region 112.
[0104] In one example, the isolation region 114 can be formed by ion doping. For example, the steps for forming the isolation region 114 may be: first, forming a fourth mask layer 113 on the first surface 101a of the semiconductor substrate 101, and then performing ion implantation based on the fourth mask layer 113 to form the isolation region 114. It should be noted that the materials of the various mask layers in this embodiment can be selected with reference to existing CIS fabrication processes.
[0105] In one example, the semiconductor substrate 101 includes a semiconductor substrate and an epitaxial layer, with the epitaxial layer serving as a functional layer for the device. An isolation region 114 penetrates the functional layer. Of course, in other implementations, the depth of the isolation region 114 can be set according to the location of the photoelectric conversion element or actual requirements for isolation. Figure 16 In the example shown, the bottom of the isolation region 114 is closer to the first surface 101a than the photoelectric conversion doped region 112.
[0106] In an alternative example, both the first trench 103 and the subsequent second trench correspond to the locations forming the isolation region 114. Thus, the structure formed by these three elements can be used to achieve device isolation as needed. For example, the location of the first trench 103 corresponding to the isolation region 114 can mean that the first trench 103 is completely within the range of the isolation region 114; that is, the periphery of the first trench 103 is the isolation region 114, or the edge of the first trench 103 is aligned with the edge of the isolation region 114.
[0107] Please see Figure 17 As shown, in one example, after forming the semiconductor device, the process further includes forming an interconnect structure layer 116 on one side of the first surface 101a of the semiconductor substrate 101. The interconnect structure layer 116 includes a dielectric layer and multiple interconnect layers, which can realize electrical interconnection and lead-out between semiconductor devices. In other examples, a support substrate or the like can be further formed on the interconnect structure layer 116 for subsequent processes.
[0108] Continue reading Figure 17 In one example, after forming the photoelectric conversion doped region 112, the following steps are also included:
[0109] A second trench is prepared from the second surface 101b of the semiconductor substrate opposite to the first surface, and a second isolation structure 117 is prepared based on the second trench, the second isolation structure 117 corresponding to the first trench 103.
[0110] Specifically, the aforementioned fabricated structure is flipped over, and subsequent processes are performed from the second surface 101b of the semiconductor substrate 101. This may involve thinning the semiconductor substrate 101 after flipping, for example, thinning it to the location with the photoelectric conversion doped region 112. In one implementation, it may involve thinning it to the epitaxial layer.
[0111] In one implementation of the formation of the second trench, firstly, a patterned mask for the deep trench isolation structure is formed by photolithography; then, an etching process is performed to fabricate the deep trench isolation structure in the back-side deep trench isolation structure region defined by the photolithography process, thereby obtaining the second trench; next, a filling material layer, including but not limited to silicon oxide, is prepared in the second trench to obtain the second isolation structure 117.
[0112] As an example, after obtaining the second isolation structure 117, a passivation layer 118 can be fabricated on the second surface 101b of the semiconductor substrate 101. The material of this passivation layer includes, but is not limited to, HK materials, such as hydroxyl oxide. Based on the passivation layer 118, it is beneficial to achieve material layer planarization and repair of process damage on the second surface 101b. Furthermore, color filters, grids, microlenses (MLs), and other structures can be further formed on the above structure. The color filter can be an RGGB Bayer array or an RGBIR arrangement to complete the fabrication of the image sensor.
[0113] Please see Figure 18 and 19 As shown, in one example, the semiconductor substrate 101 includes a plurality of pixel units 200 arranged in an array. Each pixel unit 200 includes at least one photoelectric conversion doped region (corresponding to PD1 to PD4) and a transfer control gate (corresponding to Tx1 to Tx4) corresponding to the photoelectric conversion doped region. The first trench (corresponding to 212_1 to 212_3) includes an extension trench region extending below the corresponding transfer control gate.
[0114] Specifically, this example provides a pixel circuit structural design. The first trench includes an extended trench region extending below the corresponding transmission control gate. Based on the design of this application, the extended trench region corresponds to a transmission modulation region on the periphery of the first trench. The formation of a first-doped transmission modulation region with a first region and a second region can improve the transmission barrier below the transmission gate while protecting the inner wall of the first trench. This forms a transfer path that facilitates the transfer of photoelectrons from the photoelectric conversion doped region to the floating diffusion node, which is beneficial for electron transfer when the transmission gate is turned on based on the turn-on voltage, thus improving transmission tailing. Please refer to [link to relevant documentation]. Figure 20 and Figure 21 The image shown is a simulation diagram of the potential distribution when electrons transfer from the photodiode to the floating diffusion region when the transfer transistor in the image sensor is turned on. Figure 20 and Figure 21 The difference is that, Figure 20 The transmission modulation region in the corresponding image sensor adopts the formation method of the first region and the second region in this application. Figure 21 In the corresponding image sensor, the transmission modulation area, which is composed of a single region, can be considered as... Figure 21 The structure is formed by a single ion implantation. That is, the second region above can be considered to be under the same high concentration conditions as the first region. The two regions are formed by different concentrations, that is, the second region is replaced by the first region under the same conditions. The transport modulation region only includes the large first region, which shows that the electron transfer effect is weakened.
[0115] Continue reading Figure 18 and Figure 19As shown, in one example, pixel unit 200 includes four photoelectric conversion doped regions (corresponding to PD1 to PD4) and four transmission control gates (corresponding to Tx1 to Tx4) corresponding to the photoelectric conversion doped regions (corresponding to PD1 to PD4).
[0116] The transmission control gates (corresponding to Tx1 to Tx4) are arranged facing each other to form a central opening region. The pixel unit 200 also includes an output transistor SF located in the central opening region, a first floating diffusion node FD1 and a second floating diffusion node FD2 located on both sides of the output transistor and connected to the corresponding transmission control gates, and a device gate (the reset transistor gate RST connected to FD1 is shown in the figure) connected to at least one floating diffusion node. The first trench includes a first type trench (212_3) located between the floating diffusion node and the output transistor (SF) and a second type trench (212_1 and 212_2) between the photoelectric conversion doped region (corresponding to PD1 to PD4) and the device gate (reset transistor gate RST).
[0117] In this example, there are both a first type of trench and a second type of trench below the transfer control gate. Furthermore, the two are located on opposite sides below the transfer control gate, which is beneficial for adjusting the potential barrier below the transfer control gate, facilitating the transfer of charge to the floating diffusion region, improving electron transport, and reducing tailing.
[0118] Example 2:
[0119] Please see Figures 15 to 21 As shown, this application also provides an image sensor, wherein the image sensor in this embodiment is prepared using the image sensor preparation method of Embodiment 1. The relevant structure and corresponding features can be found in the description of the preparation method, and will not be repeated here. Of course, in other embodiments, it can also be obtained based on other preparation methods, wherein the image sensor includes:
[0120] A semiconductor substrate, the semiconductor substrate including a device functional layer of a first doping type;
[0121] A semiconductor device, located in the functional layer of the device, the semiconductor device including a photoelectric conversion doped region having a second doping type different from the first doping type;
[0122] A first trench is disposed in the functional layer of the device, and its periphery includes a transmission modulation region; wherein:
[0123] The transmission modulation region includes at least a first region and a second region of a first doping type that are adjacent to each other, wherein the second region is close to the first surface and the doping concentration of the first region is greater than that of the second region.
[0124] As an example, the first region corresponds at least to the bottom of the first trench, and the second region corresponds at least to the sidewall of the first trench.
[0125] As an example, a layer of filling material is formed in the first trench to form a first isolation structure.
[0126] As an example, a second isolation structure corresponding to the first trench is formed in the semiconductor substrate, and the second isolation structure extends from a second surface opposite to the first surface into the semiconductor substrate.
[0127] As an example, an isolation region corresponding to the first trench is formed in the semiconductor substrate, and the isolation region extends from the first surface into the semiconductor substrate.
[0128] As an example, a surface oxide medium layer is also formed on the sidewalls and bottom of the first trench.
[0129] As an example, the ion doping concentration of the second region is between 20% and 80% of the ion doping concentration of the first region.
[0130] As an example, the second region has a gap with the first surface of the semiconductor substrate.
[0131] As an example, the bottom of the transmission modulation region is closer to the first surface of the semiconductor substrate than the bottom of the photoelectric conversion doping region.
[0132] As an example, the semiconductor substrate includes a plurality of pixel units arranged in an array, each pixel unit including at least one photoelectric conversion doped region and a transmission control gate corresponding to the photoelectric conversion doped region, wherein: the first trench includes an extension trench region extending below the corresponding transmission control gate.
[0133] As an example, the pixel unit includes four photoelectric conversion doped regions and four transfer control gates corresponding to the photoelectric conversion doped regions. The transfer control gates are arranged facing each other to form a central opening region. The pixel unit also includes an output transistor located in the central opening region, a first floating diffusion node and a second floating diffusion node located on both sides of the output transistor and connected to the corresponding transfer control gates, and a device gate connected to at least one floating diffusion node. The first trench includes a first type trench located between the floating diffusion node and the output transistor and a second type trench located between the photoelectric conversion doped region and the device gate.
[0134] Example 3:
[0135] This invention also provides an electronic device, including an image sensor as described in any of the above embodiments. The electronic device can be used in security monitoring, vehicle electronics, mobile phone cameras, machine vision, and other devices. The image sensor based on this invention can acquire high-quality image information, particularly for infrared-utilizing devices.
[0136] In summary, the image sensor and electronic device of this application form at least two distinct regions with the same doping type but different doping concentrations around the periphery of the first trench. This provides protection for the trench sidewalls and bottom while effectively regulating electron transport. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0137] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. All equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.
Claims
1. An image sensor, characterized by, The image sensor comprises: a semiconductor substrate comprising a device functional layer of a first doping type; a semiconductor device in the device functional layer, the semiconductor device comprising a photoelectric conversion doped region of a second doping type different from the first doping type; a first trench disposed in the device functional layer, a circumferential side comprising a transport modulation region; wherein: the transport modulation region comprises at least a first region and a second region of the first doping type adjacent to each other, the semiconductor substrate having opposite first and second faces, the first trench extending into the semiconductor substrate from the first face, the second region being closer to the first face and the first region having a doping concentration greater than the second region.
2. The image sensor of claim 1, wherein, the first region corresponds at least to a bottom of the first trench, and the second region corresponds at least to a sidewall of the first trench.
3. The image sensor of claim 1, wherein, a filling material layer is formed in the first trench to form a first isolation structure; and / or, a second isolation structure corresponding to the first trench is formed in the semiconductor substrate, the second isolation structure extending into the semiconductor substrate from the second face opposite to the first face; and / or, an isolation region corresponding to the first trench is formed in the semiconductor substrate, the isolation region extending into the semiconductor substrate from the first face.
4. The image sensor of claim 1, wherein, a surface oxide dielectric layer is further formed on the sidewall and the bottom of the first trench.
5. The image sensor of claim 1, wherein, an ion doping concentration of the second region is between 20%-80% of an ion doping concentration of the first region.
6. The image sensor of claim 1, wherein, a spacing is provided between the second region and the first face of the semiconductor substrate.
7. The image sensor of claim 1, wherein, a bottom of the transport modulation region is closer to the first face of the semiconductor substrate than a bottom of the photoelectric conversion doped region; and / or, a maximum lateral width of the second region in a direction parallel to the first face of the semiconductor substrate is less than a maximum lateral width of the first region in the direction parallel to the first face.
8. The image sensor according to any one of claims 1 to 7, wherein, the semiconductor substrate comprises a plurality of pixel units arranged in an array, each pixel unit comprising at least one photoelectric conversion doped region and a transport control gate corresponding to the photoelectric conversion doped region, wherein: the first trench comprises an extension trench region extending below the corresponding transport control gate.
9. The image sensor of claim 8, wherein, each pixel unit comprises four photoelectric conversion doped regions and four transport control gates corresponding to the photoelectric conversion doped regions, the transport control gates being oppositely disposed to form a central opening region, the pixel unit further comprising an output transistor in the central opening region, a first floating diffusion node and a second floating diffusion node connected to the corresponding transport control gates on both sides of the output transistor, and a device gate connected to at least one floating diffusion node, the first trench comprising a first type trench between the floating diffusion node and the output transistor and a second type trench between the photoelectric conversion doped region and the device gate.
10. An electronic device, comprising: the electronic device comprises the image sensor as claimed in any one of claims 1-9.