Chip packaging heat dissipation layer anti-stripping structure
By setting half-grooves on the wafer surface and using a half-cutting process to form a non-planar heat dissipation layer, the problem of heat dissipation layer peeling off during the cutting process is solved, thereby improving the yield of semiconductor packaging.
Patent Information
- Application Number
- CN202323039150.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-10
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2033-11-10
AI Technical Summary
In the semiconductor packaging process, the heat dissipation layer peels off due to the contact between the cutting blade and the plating layer during the cutting process, resulting in a decrease in product yield.
A semi-groove is set on the wafer surface, and a rectangular cross-section semi-groove is formed by a semi-cutting process with a cutting depth of 80-120μm. The heat dissipation layer is non-planar under the isolation of the semi-groove to avoid contact between the cutting blade and the continuous planar heat dissipation layer. The heat dissipation layer is formed by vacuum sputtering or coating processes.
This effectively prevents the heat dissipation layer from peeling off, thus improving the yield of semiconductor packaging.
Smart Images
Figure CN223798688U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor packaging, and in particular to a chip packaging heat dissipation layer anti-peeling structure. Background Technology
[0002] Semiconductor packaging refers to the process of processing tested wafers into individual chips according to product model and functional requirements. The packaging process is as follows: Wafers from the front-end wafer fabrication process are diced into small dies. The diced dies are then glued onto islands on corresponding substrates (lead frames). Ultra-fine metal (gold, tin, copper, aluminum) wires or conductive resin are used to connect the bonding pads of the dies to the corresponding leads on the substrate, forming the required circuit. The individual dies are then encapsulated and protected with a plastic shell. After encapsulation, a series of operations are performed. After packaging, finished product testing is conducted, typically involving incoming inspection, testing, and packaging, before finally being stored and shipped.
[0003] Currently, the fabrication of heat dissipation layers in semiconductor packaging typically employs two processes: vacuum sputtering for shielding layers and coating for heat dissipation layers. Sputtering, in an ultra-high vacuum environment, uses plasma discharge to directly bombard the target metal onto the material surface; while coating, using a coating machine, directly coats conductive metal onto the material surface. For example... Figure 1 and Figure 2 As shown, during the cutting process of product 1', the shearing force generated by the cutting blade 2' contacting the coating 3' can cause sputtering / coating peeling. Utility Model Content
[0004] The purpose of this invention is to provide a chip packaging heat dissipation layer anti-peeling structure to reduce peeling during wafer dicing and improve product yield.
[0005] To solve the above-mentioned technical problems, this utility model provides a chip packaging heat dissipation layer anti-peeling structure, including a wafer, a half-groove, and a heat dissipation layer;
[0006] The wafer is provided with multiple chip units;
[0007] The half-groove is disposed on the wafer, and the half-groove is used to cut and separate individual chip units on the wafer;
[0008] The heat dissipation layer is disposed on the wafer surface, and the heat dissipation layer is non-planar under the half-groove isolation.
[0009] Furthermore, the chip cell array is distributed.
[0010] Furthermore, the cross-section of the semi-groove is rectangular.
[0011] Furthermore, the half-groove is formed by a half-cutting process, and the cutting depth of the half-groove is 80-120μm.
[0012] Furthermore, the heat dissipation layer is either a vacuum sputtered shielding layer or a coated heat dissipation layer.
[0013] Compared with the prior art, the present invention has at least the following beneficial effects:
[0014] This invention, by setting a semi-groove on the wafer surface, can divide the heat dissipation layer of the entire wafer surface into sections. When cutting individual chip units, the heat dissipation layer will not be peeled off, thereby greatly improving the yield of semiconductor packaging. Attached Figure Description
[0015] Figure 1 A schematic diagram of the cutting structure of the heat dissipation layer for existing chip packaging technology;
[0016] Figure 2 A schematic diagram of the structure after the plating layer of the heat dissipation layer in a chip package of existing technology has been cut and peeled off.
[0017] Figure 3 This is a schematic diagram of the overall structure of the chip packaging heat dissipation layer anti-peeling structure of this utility model.
[0018] Figure 4 This is a schematic diagram of the cut structure of the anti-peeling structure of the heat dissipation layer of the chip package of this utility model. Detailed Implementation
[0019] The chip packaging heat dissipation layer anti-peeling structure of this utility model will be described in more detail below with reference to the schematic diagram, which illustrates the preferred embodiment of this utility model. It should be understood that those skilled in the art can modify the utility model described herein while still achieving the advantageous effects of this utility model. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit this utility model.
[0020] The present invention will be described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0021] like Figure 3 and Figure 4 As shown in the figure, this utility model embodiment proposes a chip packaging heat dissipation layer anti-peeling structure, including a wafer 1, a half-groove 3 and a heat dissipation layer 4.
[0022] Specifically, the wafer 1 is provided with a plurality of chip units 2, and the chip units 2 are distributed in an array.
[0023] The half-groove 3 is disposed on the wafer 1, and the half-groove 3 is used to cut and separate individual chip units 2 on the wafer 1.
[0024] The heat dissipation layer 4 is disposed on the surface of the wafer 1, and the heat dissipation layer 4 is non-planar under the isolation of the half-groove 3.
[0025] In the prior art, the heat dissipation layer 4 on the surface of wafer 1 is a continuous plane. When the chip unit 2 is cut, the shearing force generated by the cutting blade contacting the heat dissipation layer 4 will cause sputtering / coating peeling, resulting in a decrease in product yield.
[0026] In this embodiment, by setting a half-groove 3 on the surface of wafer 1, the half-groove 3 divides the continuous plane of the chip unit 2 into a non-plane. When the chip unit 2 is cut, the cutting blade contacts the heat dissipation layer 4 in the half-groove 3, which will not cause the heat dissipation layer 4 on the surface of wafer 1 to peel off, thereby improving the product yield.
[0027] In one specific embodiment, the cross-section of the half-groove 3 is rectangular, the half-groove 3 is formed by a half-cutting process, and the cutting depth of the half-groove 3 is 80-120μm.
[0028] Specifically, semi-cutting is a machining method that creates grooves by cutting into the middle of the workpiece. By continuously performing the grooving process, comb-like and needle-like shapes can be produced. In semiconductor manufacturing, semi-cutting is used in the DBG process, which first creates grooves through semi-cutting, and then simultaneously thins and separates the chip through grinding.
[0029] Furthermore, the heat dissipation layer 4 is either a vacuum sputtered shielding layer or a coated heat dissipation layer.
[0030] Specifically, vacuum sputtering mainly refers to a type of film deposition that requires a high vacuum level. It includes many types, such as vacuum ion evaporation and magnetron sputtering. Evaporation deposition generally involves heating the target material to evaporate surface components in the form of atomic clusters or ions. These evaporated components then deposit onto the substrate surface, forming a thin film through a film formation process (scattered-island structure-wandering structure-layer growth). Sputtering deposition can be simply understood as using electrons or high-energy lasers to bombard the target material, sputtering surface components in the form of atomic clusters or ions, which then deposit onto the substrate surface, undergoing a film formation process to ultimately form a thin film. Additionally, conductive metals can be directly coated onto the material surface using a coating machine.
[0031] In this process, the heat dissipation layer 4 is processed after the half-groove 3. After the heat dissipation layer 4 is completed, the heat dissipation layer 4 on the surface of wafer 1 is separated by the half-groove 3, resulting in the heat dissipation layer 4 being non-planar. During the subsequent chip unit 2 cutting process, the heat dissipation layer 4 located in the half-groove 3 will not affect the separation of the heat dissipation layer 4 on the surface of wafer 1, thereby greatly improving the product yield.
[0032] Compared with the prior art, the present invention has at least the following beneficial effects:
[0033] This invention, by setting a semi-groove on the wafer surface, can divide the heat dissipation layer of the entire wafer surface into sections. When cutting individual chip units, the heat dissipation layer will not be peeled off, thereby greatly improving the yield of semiconductor packaging.
[0034] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.
Claims
1. A chip packaging heat dissipation layer anti-peeling structure, characterized in that, This includes the wafer, half-groove, and heat dissipation layer; The wafer is provided with multiple chip units; The half-groove is disposed on the wafer, and the half-groove is used to cut and separate adjacent chip units on the wafer; The heat dissipation layer is disposed on the wafer surface, and the heat dissipation layer is non-planar under the half-groove isolation.
2. The chip packaging heat dissipation layer anti-peeling structure as described in claim 1, characterized in that, The chip unit array is distributed as follows.
3. The chip packaging heat dissipation layer anti-peeling structure as described in claim 1, characterized in that, The cross-section of the semi-groove is rectangular.
4. The chip packaging heat dissipation layer anti-peeling structure as described in claim 1, characterized in that, The half-groove is formed by a half-cutting process, and the cutting depth of the half-groove is 80-120μm.
5. The chip packaging heat dissipation layer anti-peeling structure as described in claim 1, characterized in that, The heat dissipation layer is either a vacuum sputtered shielding layer or a coated heat dissipation layer.