Semiconductor device

Abstract

A semiconductor device includes an interconnect structure over a substrate, a first metal pad, a second metal pad, and a first passivation layer around the first metal pad and the second metal pad. The interconnect structure includes an interlayer dielectric layer and a conductive portion embedded in the interlayer dielectric layer. A first metal pad is over a first one of the conductive portions. A second metal pad is over a second one of the conductive portions. Each of the first metal pad and the second metal pad has a stepped sidewall. The first passivation layer is around the first metal pad and the second metal pad.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Modern integrated circuits consist of millions of active devices, such as transistors and capacitors. These devices are initially isolated from each other but are later interconnected to form functional circuits. Typical interconnect structures include lateral interconnects, such as metal lines (wiring), and vertical interconnects, such as vias and contacts. Interconnects increasingly determine the performance and density limits of modern integrated circuits. Bonding pads are formed on top of the interconnect structure and exposed on the surface of individual wafers. Electrical connections are made via the bonding pads to connect the wafer to a package substrate or another die. Utility Model Content

[0003] In some embodiments, a semiconductor device includes a substrate, an interconnect structure, a plurality of metal pads, and a first passivation layer. The interconnect structure is located above the substrate, and the metal pads are located above the interconnect structure. Each of the metal pads has a stepped sidewall structure, the stepped sidewall structure including a lower sidewall and an upper sidewall extending rearward from the lower sidewall. The first passivation layer is located above the metal pads.

[0004] In some embodiments, a semiconductor device includes a substrate, an interconnect structure, a first metal pad and a second metal pad, a first passivation layer, a second passivation layer, and a third passivation layer. The interconnect structure is located above the substrate. The first and second metal pads are above the interconnect structure, wherein the first and second metal pads are separated from each other by pad-to-pad gaps. The first passivation layer surrounds the first and second metal pads and is located within the pad-to-pad gaps. The second passivation layer is above the first passivation layer. The third passivation layer is above the second passivation layer.

[0005] In some embodiments, a semiconductor device includes an interconnect structure, a first metal pad, a second metal pad, and a first passivation layer above a substrate. The interconnect structure includes an interlayer dielectric (ILD) layer and a plurality of conductive portions embedded in the interlayer dielectric layer. The first metal pad is above a first of the conductive portions, and the second metal pad is above a second of the conductive portions, wherein each of the first and second metal pads has stepped sidewalls. The first passivation layer surrounds the first and second metal pads. Attached Figure Description

[0006] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1AIt is a configuration of the pad array according to some embodiments;

[0008] Figure 1B This is a cross-sectional view of a semiconductor device including a first metal pad and a second metal pad in a pad array, according to some embodiments;

[0009] Figures 2A to 2B This is a flowchart illustrating a method for forming a liner structure according to some embodiments of the present disclosure;

[0010] Figures 3 to 11A and Figure 12 The diagram is based on Figures 2A to 2B A schematic diagram of the cross-sections of the various stages of fabricating a pad structure in a semiconductor device using the method described above.

[0011] Figure 11B , Figure 11C ,and Figure 11D According to some embodiments Figure 11A Enlarged view of the area in the middle;

[0012] Figures 13 to 17 The illustration shows cross-sectional views of a semiconductor device during various manufacturing stages;

[0013] Figures 18 to 23 The illustration shows cross-sectional views of a semiconductor device during various manufacturing stages.

[0014] [Symbol Explanation]

[0015] 100: Semiconductor devices

[0016] 100a~100b: Semiconductor devices

[0017] 102:Substrate

[0018] 103: Transistor

[0019] 1040~104 N Dielectric layer

[0020] 105: Conductive socket

[0021] 1061~106 N Etching termination layer

[0022] 108:STI

[0023] 110: Interconnection Structure

[0024] 1121~112 N Conductive part

[0025] 1141~114 N Conductive wire

[0026] 1161~116 N Conductive via

[0027] 120: First dielectric layer

[0028] 122: Second dielectric layer

[0029] 124': Pad array

[0030] 126: Barrier Layer

[0031] 127: Metal gasket material

[0032] 127a: First metal gasket

[0033] 127b: Second metal gasket

[0034] 127c~127h: Metal gasket

[0035] 127p: Protrusion

[0036] The lower part of 128a:127a

[0037] The lower part of 128b:127b

[0038] The upper part of 130a:127a

[0039] The upper part of 130b:127b

[0040] 131: Passivation Stacking

[0041] 132: First passivation layer

[0042] 134: Second passivation layer

[0043] 134B: The bottom part of 134

[0044] 134m:134 platform section

[0045] 134s:134 side view

[0046] 134S1~134S2: Side portion of 134

[0047] 134t: Thickness

[0048] 134t1~134t2: Thickness

[0049] 135: Passivation materials

[0050] 135t: Maximum vertical thickness

[0051] 136: Third passivation layer

[0052] 136b:136 bottom surface

[0053] 138: Groove

[0054] 139: Gasket-to-gasket gap

[0055] 140: Opening

[0056] 144: Dielectric layer

[0057] 1032: Gate Structure

[0058] 1034: Source / Drain Region

[0059] 1036: Passage Area

[0060] The bottom part of Ba:128a

[0061] Bb:128b bottom part

[0062] HS1~HS2: Lateral surface / Horizontal surface

[0063] HS3~HS6: Horizontal surfaces

[0064] L1: Length

[0065] M1: Method

[0066] P1: First patterned resist mask

[0067] P1a: First patterned resist mask

[0068] P2: Second patterned resist mask

[0069] P2a: Second patterned resist mask

[0070] P3: Masked with patterned resist

[0071] R1~R2: Area

[0072] s1: First spacing

[0073] s2: Second spacing

[0074] S10~S28: Operation

[0075] sp1: First spacing

[0076] sp2: Second spacing

[0077] SW1: Upper sidewall

[0078] SW2: Lower sidewall

[0079] SW3: Upper sidewall

[0080] SW4: Lower sidewall

[0081] SW5~SW6: First opposing sidewalls

[0082] SW7~SW8: Second opposite sidewalls

[0083] t1: First thickness

[0084] t2: Second thickness

[0085] t3: Third thickness

[0086] t4~t5: Thickness

[0087] Top surface of TP1:127a

[0088] Top surface of TP2:127b

[0089] The first top surface of TS1:132

[0090] The second top surface of TS2:132

[0091] w1~w4: Width

[0092] w1b: Bottom width

[0093] w1t: Top width

[0094] w2b:bottom width

[0095] w2t: Top width Detailed Implementation

[0096] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0097] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly.

[0098] As used herein, “approximately,” “about,” “close to,” or “substantially” may mean within 20%, 10%, or 5% of a given value or range. However, those skilled in the art will understand that the values ​​or ranges throughout the specification are merely examples and may decrease as the size of integrated circuits shrinks. The values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms “approximately,” “about,” “close to,” or “substantially” can be inferred.

[0099] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0100] In a wafer, interconnect structures include lateral interconnects, such as metal lines (wiring); and vertical interconnects, such as vias and contacts. Metal pads are formed over the interconnect structures and electrically coupled to them. Electrical connections are made via the metal pads to connect the wafer to a package substrate or another die. In some cases, probing can be performed to verify the functionality of active or passive devices on the wafer or individual electrical connections within the wafer. Probing is performed by bringing a probe into contact with the metal pads. A passivation layer may be formed over the metal pads to protect their surface and underlying circuitry from environmental influences.

[0101] In some embodiments, the passivation layer may include a first passivation layer, a second passivation layer, and a third passivation layer, wherein the second passivation layer may be incorporated in the gap between adjacent metal pads. However, when the gap is small (or has a high aspect ratio), thin-film cracks may occur in the second passivation layer because it may be subjected to high stress. Such thin-film cracks can negatively impact the reliability and performance of the device.

[0102] Some embodiments disclosed herein provide a method for forming a gasket structure. Each gasket structure may have a stepped sidewall structure to widen the gasket-to-gasket gap, thereby increasing the thin film step coverage of the second passivation layer and reducing film cracking therein. This also reduces regional high stress and global wafer warpage. Therefore, the reliability and performance of the device can be improved.

[0103] Figure 1A This refers to the configuration of a pad array 124' according to some embodiments. In some embodiments, the pad array 124' includes metal pads 127a, 127b, 127c, 127d, 127e, 127f, 127g, and 127h, each of which may extend along a first direction d1 and may be parallel to each other. In some embodiments, the metal pads 127a-127h may include a length L1 along the first direction d1, and the length L1 may be greater than about 50 μm. In some embodiments, the metal pads 127a-127h are configured along a second direction d2 intersecting the first direction d1 and are spaced apart from each other by a distance P1 along the second direction d2. For example, the second direction d2 may be substantially perpendicular to the first direction d1. In some embodiments, the distance P1 is less than about 3.5 μm. In the following sections, the metal pads 127a and 127b may be referred to as the first metal pad 127a and the second metal pad 127b.

[0104] Figure 1B This is a cross-sectional view of a semiconductor device 100 including a first metal pad 127a and a second metal pad 127b in a pad array 124, according to some embodiments. Reference Figure 1B In some embodiments, the semiconductor device 100 may include passive components (e.g., resistors, capacitors, inductors, and fuses), active components (e.g., P-channel field-effect transistors (PFETs), N-channel field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS), high-voltage transistors, and high-frequency transistors), other suitable components, and / or combinations thereof. It should be noted that those skilled in the art will understand that the above examples are provided for illustrative purposes only and are not intended to limit the scope of this disclosure in any way. Other circuit systems may also be included in the semiconductor device 100 based on various designs.

[0105] like Figure 1B As shown, the semiconductor device 100 may include a substrate 102, an interconnect structure 110 disposed on and electrically connected to the substrate 102, a first dielectric layer 120 covering the interconnect structure 110, a second dielectric layer 122 covering the first dielectric layer 120, and a pad array 124 penetrating the first dielectric layer 120 and the second dielectric layer 122. In some embodiments, the substrate 102 may be formed of silicon, a III-V compound material suitable for germanium (e.g., germanium arsenide (GeAs)), a combination thereof, or the like. In some embodiments, the substrate 102 may include a silicon-on-insulator (SOI) structure. Specifically, the SOI structure may have a layer of semiconductor material, such as silicon, formed on an insulating layer. The insulating layer may include a buried oxide (BOX) layer and / or a silicon oxide layer. It should be noted that substrate 102 may include another element semiconductor, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; or combinations thereof. Additionally, other types of substrates may also be used, such as multilayer substrates, gradient substrates, or combinations thereof.

[0106] In some embodiments, the active components of transistor 103 are formed on substrate 102. Transistor 103 includes a gate structure 1032, a source / drain region 1034, and a channel region 1036 to amplify or switch electrical signals and power. In some embodiments, shallow trench isolation (STI) 108 is adjacent to transistor 103 to prevent current leakage between transistor 103 and adjacent components. In some embodiments, dielectric layer 1040 is used to surround transistor 103 as an intermetallic layer and may include oxide materials, extremely low-k dielectrics (ELK), insulating materials, combinations thereof, or the like. In some embodiments, etch stop layer 1061 is formed over dielectric layer 1040 and may differ in composition from subsequently deposited dielectric layer 1041 and may have different etch selectivity to prevent over-etching during patterning of dielectric layer 1041. Etch stop layer 1061 may include silicon nitride, silicon oxynitride, and / or other suitable materials.

[0107] In some embodiments, the interconnect structure 110 of the semiconductor device 100 may include a plurality of dielectric layers 1040, 1041, 1042, ..., 104... N (1040~104 N Etching stop layers 1061, 1062, ..., 106N (1061~106 N ), conductive parts 1121, 1122, ..., 112 N (1121~112 N Conductive wires 1141, 1142, ..., 114 N (1141~114 N ), and conductive vias 1161, 1162, ..., 116 N (1161~116 N Conductive parts 1121-112 N Conductive wires 1141~114 N and / or conductive vias 1161 to 116 N It can be passed through dielectric layers 1040~104 N and / or etched termination layer 1061-106 N Routing is used to establish connections between transistor 103 and external electronic components. For example, such as Figure 1B As shown, dielectric layer 1040, etch stop layer 1061, dielectric layer 1041, etch stop layer 1062, dielectric layer 1042, ..., etch stop layer 106 N and dielectric layer 104 N The conductive socket 105 is arranged and stacked sequentially from bottom to top. It is routed via dielectric layer 1040 and / or etch-stop layer 1061 to establish connections between conductive portion 1121 and gate structure 1032 and / or between conductive line 1141 and source / drain region 1034. Conductive portion 1121 and conductive line 1141 can be coupled to each other. Conductive via 1162 can bridge conductive line 1141 and conductive line 1142. A similar structural configuration can also be applied to conductive line 1142 and conductive via 1162. N Conductive wire 114 N Conductive part 1122 and conductive part 112 N In some embodiments, the conductive socket 105 and the conductive wires 1141-114... N and conductive vias 1161 to 116 N Alternatively, it can be configured along a non-linear path to establish a connection between transistor 103 and the subsequently formed pad structure. In some embodiments, conductive socket 105, conductive wires 1141-114 N Conductive vias 1161 to 116 N and conductive parts 1121~112 N It may include metal-based materials with good electrical conductivity, such as copper (Cu).

[0108] In some embodiments, the interconnect structure 110 may be formed by a damascene process, a dual damascene process, a combination thereof, or the like. For example, a trench etching process may be performed to form a plurality of trenches. Subsequently, a metallic material such as copper may be provided in the trenches as an electrical transport medium. Thus, the interconnect structure 110 may be formed as part of an integrated circuit in the semiconductor device 100.

[0109] In some embodiments, a first dielectric layer 120 is positioned on the interconnect structure 110. The first dielectric layer 120 may include oxides, nitrides, silicon-free glass (USG), combinations thereof, or the like. In some embodiments, a second dielectric layer 122 is positioned on the first dielectric layer 120. The second dielectric layer 122 may include oxides, nitrides, silicon-free glass (USG), combinations thereof, or the like. In some embodiments, the first dielectric layer 120 may include silicon nitride (SiN), and the second dielectric layer 122 may include silicon-free glass (USG). It should be noted that the structural configurations of the first dielectric layer 120 and the second dielectric layer 122 are merely examples and are not intended to be limiting.

[0110] In some embodiments, a pad array 124 is formed extending through the first dielectric layer 120 and the second dielectric layer 122, such that the semiconductor device 100 can be bonded and connected to external electronic components using the pad array 124. In some embodiments, the pad array 124 can be used as a test pad prior to performing additional processing steps. The pad array 124 can be probing as part of wafer acceptance testing, circuit testing, known good die (KGD) testing, or the like. Probing can be performed to verify the functionality of active or passive devices on the substrate 102, or individual electrical connections within the substrate 102 or interconnect structure 110. Probing can be performed by bringing probes (not shown) into contact with the pad array 124. The probes can be part of a probe card that includes multiple probes, which can be connected, for example, to a test device. More specifically, the pad array 124 (emphasized by the rectangular dashed line) may be a stacked structure including a barrier layer 126, a first metal pad 127a, a second metal pad 127b, a first passivation layer 132, a second passivation layer 134, and a third passivation layer 136. In some embodiments, the first metal pad 127a and the second metal pad 127b may include similar structures. Each of the first metal pad 127a and the second metal pad 127b may include a stepped profile or a stepped sidewall structure. In some embodiments, the first metal pad 127a may have a lower portion 128a and an upper portion 130a that is thinner than the lower portion 128a. The width of the lower portion 128a of the first metal pad 127a is greater than the width of its upper portion 130a. The second metal pad 127b may have a lower portion 128b and an upper portion 130b that is thinner than the lower portion 128b. The width of the lower portion 128b of the second metal pad 127b is greater than the width of the upper portion 130b of the second metal pad 127b. Therefore, the pad-to-pad gap between the upper portion 130a of the first metal pad 127a and the upper portion 130b of the second metal pad 127b can be increased. For example, the pad-to-pad gap between the upper portion 130a of the first metal pad 127a and the upper portion 130b of the second metal pad 127b is greater than the pad-to-pad gap between the lower portion 128a of the first metal pad 127a and the lower portion 128b of the second metal pad 127b. The stepped profile of the first metal pad 127a and the second metal pad 127b facilitates widening the pad-to-pad gap of the pad array 124. The enlarged gasket between the upper portions 130a and 130b increases the thin film step coverage of the second passivation layer 134 in region R1 between the first metal gasket 127a and the second metal gasket 127b, thereby preventing thin film cracking in the second passivation layer 134. It also reduces regional high stress and global wafer warpage. Therefore, it improves the reliability and performance of the device.It should be noted that the structural configuration of the components described above in the interconnect structure 110 can be adjusted based on various designs. Furthermore, a more detailed description of the pad array 124 will be given below.

[0111] refer to Figures 2A to 2B This is a flowchart illustrating a method M1 for forming a pad array 124 according to some embodiments of the present disclosure. More specifically, Figures 2A to 2B The illustration shows an exemplary embodiment of a pad array 124 included in a semiconductor device 100. Method M1 may include relevant portions of the manufacturing process of the semiconductor device 100. It should be noted that the methods presented below are merely examples and are not intended to limit the scope of this disclosure beyond the express references in the claims. Additional operations may be provided before, during, and after the methods. For other embodiments of the manufacturing process, some of the described operations may be replaced, eliminated, or moved. Additionally, some elements in the figures have been simplified for clarity and ease of explanation.

[0112] Figures 3 to 11A and Figure 12 The diagram is based on Figures 2A to 2B A schematic diagram of cross-sections at various stages of fabricating the pad array 124 in the semiconductor device 100 using method M1. More specifically, the following will combine... Figures 3 to 11A and Figure 12 The cross-section shown is a reference. Figures 2A to 2B Operations S10 to S28 are used to jointly describe the detailed manufacturing and structure of the pad array 124. Figure 11B , Figure 11C ,and Figure 11D According to some embodiments Figure 11A A magnified view of the area in the image.

[0113] Method M1 may begin with operation S10, which includes forming an interconnect structure 110 on the substrate 102 of the semiconductor device 100. Further, as follows... Figures 3 to 5 The conductive part 112 shown N and conductive wire 114 N The manufacturing process enables the conductive portion 112 of the interconnect structure 110 to... N It can be formed on dielectric layer 104 N It is exposed as an intermediate structure.

[0114] refer to Figure 3 Provided the formation of etch stop layer 106. N The upper dielectric layer 104 N Conductive via 116 N Can penetrate dielectric layer 104 N and etch stop layer 106 NFormation. It should be noted that, for clarity and ease of explanation of this disclosure, a portion of the semiconductor device 100 is specifically illustrated. In some embodiments, dielectric layer 104... N It can be an inter-metal dielectric (IMD) layer or an inter-layer dielectric (ILD) layer. In some embodiments, the IMD layer can be made of phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicone glass (FSG), SiOxCy, spin-coated glass, spin-coated polymer, silicon carbide material, low-k dielectric material, its compound, its composite, its composition, or the like by any suitable method, such as spin-coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), combinations thereof, or the like.

[0115] refer to Figure 4 Groove 138 (or trench) is formed in dielectric layer 104. N The groove 138 can be formed by any suitable etching process, such as wet etching, dry etching, a combination thereof, or similar. In some embodiments, the dielectric layer 104 N The groove 138 can be formed by any suitable process, such as damascene, double damascene, a combination thereof, or similar, to form a trench with the desired shape based on various designs. In some embodiments, in dielectric layer 104 N Another groove is formed in the middle ( Figure 4 (Not shown) to form other conductive lines. That is, to form the subsequently formed conductive portion 112. N and conductive wire 114 N The groove 138 and the grooves used to form other conductive lines can be formed in the same etching process.

[0116] refer to Figure 5 The conductive portion 112 of the interconnect structure 110 N It is formed in the groove 138. In other words, the conductive portion 112 N and conductive wire 114 N Embeddable dielectric layer 104 N According to the above... Figure 1B Description of conductive part 112 N Can be passed through dielectric layer 104 N Routing to connect conductive line 114 N This makes the conductive portion 112 of the interconnect structure 110... N Conductive wire 114 N and conductive via 116 NIt can become part of the electrical connection between external electronic components and components such as transistor 103 in semiconductor device 100. Conductive portion 112 N and conductive wire 114 N It may include conductive materials such as copper, aluminum, tungsten, combinations thereof, or the like. In some embodiments, the conductive portion 112 of the interconnect structure 110 N and conductive wire 114 N It can be formed by any suitable process, such as inlay, double inlay, a combination thereof, or similar, to fill the groove 138 with a conductive material. In some embodiments, the conductive portion 112 N and conductive wire 114 N Conductive vias 116 can be formed N .

[0117] In some embodiments, the conductive portion 112 of the semiconductor device 100 N and conductive wire 114 N It may further include the conductive portion 112 N and conductive wire 114 N With dielectric layer 104 N One or more barrier layers or adhesive layers are used to prevent metal from leaving the conductive part 112. N and conductive wire 114 N Diffusion to dielectric layer 104 N Metal contamination caused by the medium. In addition, the barrier layer or adhesion layer may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, or the like, and may be formed by using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), combinations thereof, or the like.

[0118] In some embodiments, the conductive portion 112 N and conductive wire 114 N It can be done in Figure 4 The structure is formed by depositing a conductive material on top of the structure, which can fill the groove 138 and cover the dielectric layer 104. N The top surface of the conductive material. Subsequently, a planarization operation can be performed to partially remove the conductive material, such that the top surface of the conductive material is separated from the dielectric layer 104. N The top surface is essentially flush, thus forming an embedded dielectric layer 104. N The conductive part 112 N and conductive wire 114 NFurthermore, planarization operations may include the use of chemical mechanical polishing (CMP) processes. Therefore, as... Figure 5 As shown, conductive part 112 N and conductive wire 114 N The top surface can be connected to dielectric layer 104 N The top surfaces are essentially coplanar.

[0119] refer to Figure 6 Method M1 can proceed to operation S12, which includes forming a first dielectric layer 120 and a second dielectric layer 122 on the interconnect structure 110. More specifically, the first dielectric layer 120 and the second dielectric layer 122 are formed on the conductive portion 112. N Conductive wire 114 N and dielectric layer 104 N superior.

[0120] In some embodiments, the first dielectric layer 120 and the second dielectric layer 122 may comprise different materials. For example, the first dielectric layer 120 may comprise silicon nitride (SiN), and the second dielectric layer 122 may comprise silicon-free glass (USG), or vice versa. The first dielectric layer 120 and the second dielectric layer 122 may be formed layer by layer by CVD, PVD, ALD, or another deposition technique.

[0121] refer to Figure 7 Method M1 may proceed to operation S14, which includes forming at least one opening 140 through the first dielectric layer 120 and the second dielectric layer 122. For ease of explanation, Figure 7 Two openings 140 are shown. More specifically, the first dielectric layer 120 and the second dielectric layer 122 may be patterned and / or etched to form the openings 140 therein, such that the openings 140 expose the conductive portion 112. N and conductive wire 114 N The top surface. In some embodiments, at least one etching process, such as wet etching, photochemical etching, dry etching, plasma etching, or a combination thereof, may be selectively performed to give the opening 140 an oriented or anisotropic structure. It should be noted that the opening 140 may be referred to as a contact opening, a through-hole, or the like.

[0122] refer to Figure 8 Method M1 can proceed to operation S16, which includes passing through the opening 140 into the conductive portion 112 of the interconnect structure 110. N and conductive wire 114 N A barrier layer 126 is formed on top. More specifically, the barrier layer 126 is deposited on... Figure 7 Above the structure, specifically, through the opening 140, is deposited on the conductive portion 112.N and conductive wire 114 N On a portion of the surface. In some embodiments, the barrier layer 126 may include a tantalum (Ta)-based material, such as tantalum, tantalum nitride (TaN), a combination thereof, or the like. In some embodiments, the barrier layer 126 may be formed by CVD, PVD, ALD, or another deposition technique.

[0123] Still referencing Figure 8 Method M1 may proceed to operation S18, which includes forming a metal pad material 127 on the barrier layer 126. More specifically, the metal pad material 127 may include an aluminum (Al)-based material, a copper (Cu)-based material, a combination thereof, or the like, to enable electrical connections to the semiconductor device 100. In some embodiments, the metal pad material 127 may be formed by at least one of the deposition processes described above.

[0124] Still referencing Figure 8 Method M1 may proceed to operation S20, which includes forming a first patterned resist mask P1 over the metal pad material 127. A resist layer is formed over the metal pad material 127, and then patterned into the first patterned resist mask P1 using a suitable optical lithography process, such that portions of the metal pad material are exposed by the first patterned resist mask P1. In some embodiments, the first patterned resist mask P1 is a photoresist. In some embodiments, the first patterned resist mask P1 is an ashing removable dielectric (ARD), which is a photoresist-like material generally possessing the properties of a photoresist and can be etched and patterned like a photoresist. Exemplary optical lithography processes may include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof.

[0125] refer to Figure 9 Method M1 may proceed to operation S50, which includes performing a first etching process to etch the metal pad material 127 and the barrier layer 126. The first etching process is performed to pattern the metal pad material 127 exposed by the first patterned resist mask P1. A portion of the metal pad material 127 and the barrier layer 126 is removed. For example, the metal pad material 127 may be patterned as a first metal pad 127a and a second metal pad 127b spaced apart and separated from each other. For example, the first metal pad 127a and the second metal pad 127b are separated from each other by a pad-to-pad gap 139. The first patterned resist mask P1 is then removed using a suitable process (such as ashing and / or etching). After the etching process, the top surface of the second dielectric layer 122 is exposed.

[0126] refer to Figure 10 Method M1 can proceed to operation S24, which includes forming a second patterned resist mask P2 over the metal pad material 127. A resist layer is formed over the metal pad material 127, and then patterned into the second patterned resist mask P2 using a suitable optical lithography process, such that portions of the metal pad material 127 and the second dielectric layer 122 are exposed by the second patterned resist mask P2.

[0127] refer to Figure 11A and Figure 11B . Figure 11B yes Figure 11A An enlarged view of region R2. Method M1 can continue to operation S26, which includes performing a second etching process to etch the first metal pad 127a and the second metal pad 127b using a second patterned resist mask P2 as an etching mask. The second etching process is performed to pattern the first metal pad 127a and the second metal pad 127b exposed by the second patterned resist mask P2. The top portions of the first metal pad 127a and the second metal pad 127b can be etched. The second etching process can reshape the first metal pad 127a and the second metal pad 127b. In other words, the upper portions 130a of the first metal pad 127a and the upper portions 130b of the second metal pad 127b can be trimmed. After trimming, the first metal pad 127a and the second metal pad 127b can each have a stepped sidewall structure. The stepped sidewall structure of the first metal gasket 127a includes a lower sidewall SW2 and an upper sidewall SW1 extending rearward from the lower sidewall SW2. For example, the upper sidewall SW1 and the lower sidewall SW2 are connected by a lateral surface HS1. (See reference...) Figure 11C In some other embodiments, the second etching process can be performed by applying one or more etchants to the first metal pad 127a and the second metal pad 127b with suitable etching parameters to create concave lateral surfaces HS1 and HS2. (See reference...) Figure 11DIn some other embodiments, the second etching process can be performed by applying one or more etchants to the first metal pad 127a and the second metal pad 127b with suitable etching parameters to create convex lateral surfaces HS1 and HS2. The stepped sidewall structure of the second metal pad 127b includes a lower sidewall SW4 and an upper sidewall SW3 extending rearward from the lower sidewall SW4. For example, the upper sidewall SW3 and the lower sidewall SW4 are connected via the lateral surface HS2. In some embodiments, the upper sidewall SW1 and the lower sidewall SW2 are inclined relative to the lateral surface HS1. In some embodiments, the upper sidewall SW3 and the lower sidewall SW4 are inclined relative to the lateral surface HS2. The second patterned resist mask P2 is then removed using a suitable process (such as ashing and / or etching). The lower portion 128a may have a width w1 different from the width w2 of the upper portion 130a. For example, the upper portion 130a may be narrower than the lower portion 128a. In other words, the upper portion 130a may have a width w2 that is smaller than the width w1 of the lower portion 128a. In some embodiments, the second metal pad 127b may include a structure or shape substantially the same as the first metal pad 127a. The second metal pad 127b may have a lower portion 128b and an upper portion 130b above the lower portion 128b, and the lower portion 128b may have a width w3 that is different from the width w4 of the upper portion 130b. For example, the upper portion 130b may be narrower than the lower portion 128b. In other words, the upper portion 130b may have a width w4 that is smaller than the width w3 of the lower portion 128b. The spacing between the upper portion 130a of the first metal pad 127a and the upper portion 130b of the second metal pad 127b varies with increasing level height. The thickness of the upper portion 130a of the first metal pad 127a may decrease with increasing level height. The thickness of the upper portion 130b of the second metal pad 127b can decrease with increasing level height. The thickness of the lower portion 128a of the first metal pad 127a can decrease with increasing level height. The thickness of the lower portion 128b of the second metal pad 127b can decrease with increasing level height. Specifically, the lower portion 128a has a bottom portion Ba embedded in the first dielectric layer 120 and the second dielectric layer 122. In some embodiments, the bottom portion Ba may have a constant thickness t4 with increasing level height. The lower portion 128b has a bottom portion Bb embedded in the first dielectric layer 120 and the second dielectric layer 122. In some embodiments, the bottom portion Bb may have a constant thickness t5 with increasing level height. The upper portion 130a of the first metal pad 127a and the upper portion 130b of the second metal pad 127b can be separated by a first gap s1, which is the minimum gap between the upper portion 130a of the first metal pad 127a and the upper portion 130b of the second metal pad 127b.The spacing between the lower portion 128a of the first metal pad 127a and the lower portion 128b of the second metal pad 127b varies with increasing level height. The lower portions 128a and 128b of the first metal pad 127a and the second metal pad 127b may be spaced apart by a second spacing s2, which is the minimum spacing between them. The second spacing s2 may differ from the first spacing s1. In some embodiments, the first spacing s1 may be in the range of about 2500 nm to about 7500 nm, and the second spacing s2 may be in the range of about 0 nm to about 2500 nm. Since the upper portions 130a and 130b can be narrower than the lower portions 128a and 128b, the first spacing s1 can be greater than the second spacing s2, thereby increasing the padding to pad gap 139. This is beneficial for the subsequent passivation stacking of the thin film step coverage, which will be discussed in more detail below.

[0128] In some embodiments, the upper portion 130a of the first metal pad 127a may include a tapered shape. For example, the upper portion 130a may include a bottom width w2b and a top width w2t smaller than the bottom width w2b. In some embodiments, the lower portion 128a of the first metal pad 127a may include a tapered shape. For example, the lower portion 128a may include a bottom width w1b and a top width w1t smaller than the bottom width w1b. The upper portion 130b and the lower portion 128b of the second metal pad 127b may be similar in outline to the upper portion 130a and the lower portion 128a, respectively, and therefore their description is omitted here.

[0129] refer to Figure 12Method M1 may proceed to operation S28, which includes forming a passivation stack 131 over the first metal pad 127a and the second metal pad 127b. In some embodiments, forming the passivation stack 131 includes forming a first passivation layer 132 over the first metal pad 127a, the second metal pad 127b, and the second dielectric layer 122, forming a second passivation layer 134 over the first passivation layer 132, and forming a third passivation layer 136 over the second passivation layer 134. In some embodiments, the first passivation layer 132 may surround and contact the first metal pad 127a and the second metal pad 127b. For example, the first passivation layer 132 is formed to cover the top surface, upper sidewall SW1, and lower sidewall SW2 of the first metal pad 127a, and the top surface, upper sidewall SW3, and lower sidewall SW4 of the second metal pad 127b. Horizontal surfaces HS1 and HS2 may contact the first passivation layer 132. In some embodiments, the first passivation layer 132 includes a separated horizontal surface HS3 below the top surface TP1 of the first metal pad 127a and the top surface TP2 of the second metal pad 127b. In some embodiments, the first passivation layer 132 may be formed by any suitable method (such as CVD, PVD, ALD, or the like) from a dielectric material (e.g., silicon nitride, silicon oxide, high-density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS), silicon-free glass (USG), the like, or combinations thereof).

[0130] In some embodiments, the second passivation layer 134 may be formed from a dielectric material (e.g., silicon nitride, silicon oxide, high-density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS), silicon-free glass (USG), the like, or combinations thereof) by any suitable method (such as CVD, PVD, ALD, or the like). The second passivation layer 134 has a second horizontal surface HS4 between the first horizontal surfaces HS3 of the first passivation layer 132. In some embodiments, the third passivation layer 136 may be formed from a dielectric material (e.g., silicon nitride, silicon oxide, high-density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS), silicon-free glass (USG), the like, or combinations thereof) by any suitable method (such as CVD, PVD, ALD, or the like). In some embodiments, the first passivation layer 132 may include USG, the second passivation layer 134 may include HDP, and the third passivation layer 136 may include silicon nitride. In some embodiments, the third passivation layer 136 has a stepped sidewall structure. In some embodiments, the bottom surface 136b of the third passivation layer 136 is higher than the lateral surface HS1 of the stepped sidewall structure of the first metal pad 127a and the lateral surface HS2 of the stepped wall structure of the second metal pad 127b.

[0131] In some embodiments, the first passivation layer 132 may include a uniform thickness, and the third passivation layer 136 may include a uniform thickness. In some embodiments, the second passivation layer 134 may be formed by a high-density plasma (HDP) silicon oxide deposition process, and therefore may include a non-uniform thickness. For example, the second passivation layer 134 has a mesa portion 134m between the lower portion 128a of the first metal pad 127a and the lower portion 128b of the second metal pad 127b, the mesa portion having a first thickness t1, which is different from the second thickness t2 of the side portion 134s of the second passivation layer 134 along the sidewall of the upper portion 130a of the first metal pad 127a. The second passivation layer 134 may include a top portion 134t above the top surface TP1 of the first metal pad 127a or the top surface TP2 of the second metal pad 127b, which has a third thickness t3 different from the thickness t1 of the mesa portion 134m. In some embodiments, the first thickness t1 and the third thickness t3 may be greater than the second thickness t2. In some embodiments, the second passivation layer 134 has a maximum vertical thickness, i.e., thickness t1, above the liner-to-liner gap 139.

[0132] Because the first metal pad 127a and the second metal pad 127b are spaced apart by the enlarged pad to the pad gap 139, the thin film step coverage of the passivation stack 131 is improved. This also reduces regional high stress and global wafer warpage. It also reduces thin film cracks in the second passivation layer 134. In other words, the passivation stack 131 can be crack-free. Therefore, the reliability and performance of the device can be improved.

[0133] Figures 13 to 17 The illustration shows cross-sectional views of semiconductor device 100a during different manufacturing stages. Semiconductor device 100a is similar to... Figure 1B and Figures 3 to 12 Semiconductor device 100. Therefore, for simplicity and clarity, similar features are numbered the same. Reference Figure 13 A first patterned resist mask P1a is formed over the metal pad material 127. A resist layer is formed over the second passivation layer, and then patterned into the first patterned resist mask P1a using a suitable optical lithography process, such that a portion of the metal pad material 127 is exposed by the first patterned resist mask P1a. In some embodiments, the first patterned resist mask P1a is a photoresist, and its composition and formation method are similar to those previously discussed. Figure 8 The first patterned resist mask P1 discussed here is similar, so its description is omitted here.

[0134] refer to Figure 14A first etching process is performed to etch the metal pad material 127. Using a first patterned resist mask P1a as an etching mask, the first etching process is performed to pattern the metal pad material 127. A portion of the metal pad material 127 is removed. The patterned resist mask P1a is then removed using a suitable process (such as ashing and / or etching). After performing the first etching process, the second dielectric layer 122 may still be covered by the metal pad material 127. Each portion of the metal pad material 127 in the conductive portion 112... N and conductive wire 114 N It has a protrusion of 127p on top.

[0135] refer to Figure 15 A second patterned resist mask P2a may be formed over the metal pad material 127. For example, the second patterned resist mask P2a may be formed over the protrusion 127p. A resist layer is formed over the protrusion 127p of the metal pad material 127, and then it is patterned into the second patterned resist mask P2a using a suitable optical lithography process, so that a portion of the metal pad material 127 is exposed by the second patterned resist mask P2a.

[0136] refer to Figure 16 A second etching process is performed to etch the metal pad material 127a and the barrier layer 126 by forming the first metal pad 127a and the second metal pad 127b using a second patterned resist mask P2a as an etching mask. The second etching process is performed to pattern the metal pad material 127 exposed by the second patterned resist mask P2a. The second etching process can reshape the first metal pad 127a and the second metal pad 127b. The protrusions 127p of the metal pad material 127 and the bottom of the metal pad material 127 below the protrusions 127p can be etched. The second patterned resist mask P2a is then removed using a suitable process (such as ashing and / or etching). After performing the second etching process, the second dielectric layer 122 can be exposed. The first metal pad 127a and the second metal pad 127b may each have a stepped sidewall structure. The first metal gasket 127a may have a lower portion 128a and an upper portion 130a above the lower portion 128a, and the lower portion 128a may have a width different from the width of the upper portion 130a. The structural details of the first metal gasket 127a may be similar to those of the first metal gasket 127a regarding... Figure 11A The structure of the second metal pad 127b is omitted here. Similarly, the second metal pad 127b may have a lower portion 128b and an upper portion 130b above the lower portion 128b, and the lower portion 128b may have a width different from the width of the upper portion 130b. The structural details of the second metal pad 127b may be similar to those of the second metal pad 127b. Figure 11A The structure is omitted here.

[0137] refer to Figure 17 Passivation stack 131 may be formed over the first metal pad 127a and the second metal pad 127b. Passivation stack 131 is similar to previously mentioned... Figure 12 The passivation stack 131 discussed here is therefore omitted from the description.

[0138] Figures 18 to 23 The illustration shows cross-sectional views of semiconductor device 100b during various manufacturing stages. Semiconductor device 100b is similar to... Figure 1B and Figures 3 to 12 The semiconductor device 100 is shown. Therefore, for simplicity and clarity, similar features are numbered the same. A pad-to-pad gap 139 may be located between the first metal pad 127a and the second metal pad 127b. Reference Figure 18 A first passivation layer 132 and a second passivation layer 134 may be sequentially formed over a first metal pad 127a, a second metal pad 127b, and a second dielectric layer 122. In some embodiments, the second passivation layer 134 may include a side portion 134S1 on the sidewall of the first metal pad 127a and a side portion 134S2 on the sidewall of the second metal pad 127b, wherein a pad gap 139 is formed between the side portions 134S1 and 134S2. The second passivation layer 134 may include a bottom portion 134B below the side portions 134S1 and 134S2.

[0139] refer to Figure 19 A patterned resist mask P3 is formed over the metal pad material 127. A resist layer is formed over the second passivation layer, and then patterned into the patterned resist mask P3 using a suitable optical lithography process, such that portions of the metal pad material 127 are exposed by the patterned resist mask P3. In some embodiments, the patterned resist mask P3 is a photoresist, and its composition and formation method are similar to those previously discussed. Figure 8 The first patterned resist mask P1 discussed is similar, so its description is omitted here. The side portions 134S1, 134S2 and the bottom portion 134B, as well as the pad gap 139, may be exposed by the patterned resist mask P3. In some embodiments, the patterned resist mask P3 does not overlap with the pad-to-pad gap 139.

[0140] refer to Figure 20An etching process is performed to etch the second passivation layer 134. Using a patterned resist mask P3 as an etching mask, the etching process is performed to pattern the second passivation layer 134. For example, a portion of the second passivation layer 134 in the pad-to-pad gap 139 is trimmed. In some embodiments, the portion of the second passivation layer 134 in the pad-to-pad gap 139 is trimmed such that the second passivation layer 134 has first opposing sidewalls SW5 and SW6 above the top surface TP1 of the first metal pad 127a and the top surface TP2 of the second metal pad 127b, respectively. The second passivation layer 134 may have second opposing sidewalls SW7 and SW8 in the pad-to-pad gap 139, and the first spacing sp1 between the first opposing sidewalls SW5 and SW6 is greater than the second spacing sp2 between the second opposing sidewalls SW7 and SW8. The patterned resist mask P3 is then removed using a suitable process (such as ashing and / or etching).

[0141] An etching process can be performed to thin the side portions 134S1, 134S2 and the bottom portion 134B, which improves the film coverage of the subsequently formed passivation material. After the etching process, the bottom portion 134B of the second passivation layer 134 may have a reduced thickness, and the side portions 134S1, 134S2 may have a reduced thickness. In some embodiments, the side portions 134S1, 134S2 may have a thickness less than that of the bottom portion 134B. In some embodiments, a portion of the first passivation layer 132 is exposed after the etching process. For example, the first passivation layer 132 has a first top surface TS1 exposed by the second passivation layer 134 and a second top surface TS2 remaining covered by the second passivation layer 134.

[0142] refer to Figure 21In some embodiments, a deposition process is performed to form a passivation material 135 over the second passivation layer 134. For example, the passivation material 135 may be formed over a trimmed portion of the second passivation layer 134. In some embodiments, the passivation material 135 has a horizontal surface HS7 above the pad-to-pad gap 139 that is higher than the top surface TP1 of the first metal pad 127a. In some embodiments, the passivation material 135 is the same as the second passivation layer 134 in terms of composition and formation method. For example, the passivation material 135 may be formed from high-density plasma (HDP) oxides using high-density plasma deposition. After the deposition process, the second passivation layer 134 and the passivation material 135 together have a first portion (with a thickness 134t1) between the first metal pad 127a and the second metal pad 127b, and the second passivation layer 134 and the passivation material 135 together have a second portion (with a thickness 134t2 different from the thickness 134t1) above the top surface TP1 of the first metal pad 127a and the top surface TP1 of the second metal pad 127b. The thickness 134t1 may be greater than the thickness 134t2. The passivation material 135 may fill the remaining space of the pad-to-pad gap 139 between the first metal pad 127a and the second metal pad 127b. In some embodiments, the passivation material 135 has a maximum vertical thickness 135t above the pad-to-pad gap 139.

[0143] refer to Figure 22 In some embodiments, a third passivation layer 136 may be formed over the second passivation layer 134. The third passivation layer 136 may differ from previously discussed methods in terms of composition and formation. Figure 12 The third passivation layer discussed is similar, so its description is omitted here. In some embodiments, the third passivation layer 136 may include a horizontal surface HS6 above the pad-to-pad gap 139, which is higher than the top surface TP1 of the first metal pad 127a and the top surface TP2 of the second metal pad 127b. In some embodiments, the third passivation layer 136 has a maximum vertical thickness 136t above the pad-to-pad gap 139.

[0144] refer to Figure 23In some other embodiments, an optional dielectric layer 144 may be formed over the third passivation layer 136. The dielectric layer 144 may be made of phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicone glass (FSG), SiOxCy, spin-coated glass, spin-coated polymer, silicon carbide material, low-k dielectric material, its compounds, its composites, its compositions, or the like via any suitable method (e.g., spin-coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), combinations thereof, or the like).

[0145] Based on the above discussion, it is clear that the various embodiments disclosed herein offer advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, nor is any specific advantage required for all embodiments. One advantage is that the gasket structures may each have stepped sidewall structures to widen the gasket-to-gasket gap, thereby increasing the thin film step coverage of the second passivation layer and thus reducing film cracking therein. Another advantage is that it can also reduce regional high stress and global wafer warpage. Yet another advantage is that it can improve the reliability and performance of the device.

[0146] In some embodiments, a method of forming a semiconductor device includes the following steps: forming a metal pad material over an interconnect structure above a substrate; patterning the metal pad material into a plurality of metal pads; trimming the upper portions of the plurality of metal pads; after trimming, each of the plurality of metal pads has a stepped sidewall structure, the structure including a lower sidewall and an upper sidewall extending rearward from the lower sidewall; forming a first passivation layer over the plurality of metal pads; in some embodiments, the first passivation layer has a stepped sidewall structure; in some embodiments, the method further includes forming a second passivation layer over the first passivation layer, wherein the second passivation layer has a stepped sidewall structure; in some embodiments, the second passivation layer is formed using high-density plasma (HDP) silicon oxide deposition; in some embodiments, the first passivation layer has a separated first horizontal surface below the top surface of one of the plurality of metal pads; in some embodiments, the second passivation layer has a second horizontal surface between the first horizontal surfaces in the first passivation layer; in some embodiments, the method further includes forming a third passivation layer over the second passivation layer, wherein the third passivation layer has a stepped sidewall structure. In some embodiments, the bottom surface of the third passivation layer is higher than the horizontal surface of the stepped sidewall structure of each of the plurality of metal pads.

[0147] In some embodiments, a method of forming a semiconductor device includes the following steps: A first metal pad and a second metal pad are formed over an interconnect structure above a substrate. The first metal pad and the second metal pad are separated from each other by pad-to-pad gaps. A first passivation layer is formed around the first and second metal pads and in the pad-to-pad gaps. A second passivation layer is formed over the first passivation layer. A portion of the second passivation layer in the pad-to-pad gaps is trimmed. A third passivation layer is formed over the trimmed portion of the second passivation layer.

[0148] In some embodiments, a portion of the second passivation layer in the pad-to-pad gap is trimmed such that the second passivation layer has first opposing sidewalls above the top surface of the first metal pad and the top surface of the second metal pad, respectively. In some embodiments, a portion of the second passivation layer in the pad-to-pad gap is trimmed such that the second passivation layer has second opposing sidewalls in the pad-to-pad gap, and the first opposing sidewalls have a first spacing greater than the second spacing of the second opposing sidewalls. In some embodiments, a portion of the second passivation layer in the pad-to-pad gap is trimmed such that the first passivation layer is exposed. In some embodiments, a third passivation layer is in contact with the first passivation layer. In some embodiments, high-density plasma deposition is used to form the third passivation layer. In some embodiments, the third passivation layer has a maximum vertical thickness in the pad-to-pad gap. In some embodiments, the method further includes forming a fourth passivation layer over the third passivation layer, wherein the fourth passivation layer has a maximum vertical thickness over the pad-to-pad gap. In some embodiments, the fourth passivation layer has a horizontal surface above the top surface of the first metal pad over the pad-to-pad gap. In some embodiments, the third passivation layer has a horizontal surface above the top surface of the first metal liner above the liner-to-liner gap.

[0149] In some embodiments, the semiconductor device includes an interconnect structure above a substrate, a first metal pad, a second metal pad, and a first passivation layer surrounding the first and second metal pads. The interconnect structure includes an inter-layer dielectric (ILD) layer and conductive portions embedded in the ILD layer. The first metal pad is located above the first of the conductive portions. The second metal pad is located above the second of the conductive portions. Each of the first and second metal pads has stepped sidewalls. The first passivation layer surrounds the first and second metal pads. In some embodiments, the first passivation layer has stepped sidewalls.

[0150] In some embodiments, a semiconductor device includes a substrate, an interconnect structure, a plurality of metal pads, and a first passivation layer. The interconnect structure is located above the substrate, and the metal pads are located above the interconnect structure. Each of the metal pads has a stepped sidewall structure, including a lower sidewall and an upper sidewall extending rearward from the lower sidewall. The first passivation layer is located above the metal pads. In some embodiments, the first passivation layer has a stepped sidewall structure. In some embodiments, the semiconductor device further includes a second passivation layer located above the first passivation layer, wherein the second passivation layer also has a stepped sidewall structure. In some embodiments, the metal pads are parallel to each other.

[0151] In some embodiments, the semiconductor device includes a substrate, an interconnect structure, a first metal pad and a second metal pad, a first passivation layer, a second passivation layer, and a third passivation layer. The interconnect structure is located above the substrate. The first metal pad and the second metal pad are above the interconnect structure and are separated from each other by pad-to-pad gaps. The first passivation layer surrounds the first and second metal pads and is located within the pad-to-pad gaps. The second passivation layer is located above the first passivation layer, and the third passivation layer is located above the second passivation layer. In some embodiments, a plurality of first opposing sidewalls are provided above the top surfaces of the first and second metal pads. In some embodiments, the second passivation layer has a plurality of second opposing sidewalls within the pad-to-pad gaps, and the first opposing sidewalls have a first spacing greater than the second spacing of the second opposing sidewalls. In some embodiments, the first metal pad has a concave lateral surface.

[0152] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a substrate; an interconnect structure over the substrate; a plurality of metal pads over the interconnect structure, wherein each of the plurality of metal pads has a stepped sidewall structure comprising a lower sidewall and an upper sidewall set back from the lower sidewall; and a first passivation layer over the plurality of metal pads.

2. The semiconductor device according to claim 1, wherein wherein the first passivation layer has a stepped sidewall structure.

3. The semiconductor device according to claim 1, wherein Further comprising: a second passivation layer over the first passivation layer, wherein the second passivation layer has a stepped sidewall structure.

4. The semiconductor device according to claim 3, wherein wherein the plurality of metal pads are parallel to each other.

5. A semiconductor device, characterized by comprising: Comprising: a substrate; an interconnect structure over the substrate; a first metal pad and a second metal pad over the interconnect structure, wherein the first metal pad and the second metal pad are separated from each other by a pad-to-pad gap; a first passivation layer around the first metal pad and the second metal pad and in the pad-to-pad gap; a second passivation layer over the first passivation layer; and a third passivation layer over the second passivation layer.

6. The semiconductor device according to claim 5, wherein wherein a top surface of the first metal pad and a top surface of the second metal pad have a plurality of first opposing sidewalls thereover.

7. The semiconductor device according to claim 6, wherein wherein the second passivation layer has a plurality of second opposing sidewalls in the pad-to-pad gap, and the plurality of first opposing sidewalls have a first pitch that is greater than a second pitch of the plurality of second opposing sidewalls.

8. The semiconductor device according to claim 5, wherein wherein the first metal pad has a concave lateral surface.

9. A semiconductor device, characterized by comprising: It comprises: an interconnect structure over a substrate, wherein the interconnect structure comprises an interlayer dielectric (ILD) layer and a plurality of conductive portions embedded in the interlayer dielectric layer; a first metal pad over a first one of the plurality of conductive portions; a second metal pad over a second one of the plurality of conductive portions, wherein each of the first metal pad and the second metal pad has a stepped sidewall; and a first passivation layer around the first metal pad and the second metal pad.

10. The semiconductor device according to claim 9, wherein wherein the first passivation layer has a stepped sidewall. wherein the first metal pad has a concave lateral surface.

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