Semiconductor device

Abstract

A semiconductor device includes a plurality of semiconductor chips stacked on top of each other, each semiconductor chip including a substrate, a device layer, a conductive layer, a chip node, and a plurality of interconnect structures. The device layer is formed on the substrate and includes a plurality of chip assemblies. The conductive layer interconnects the plurality of chip assemblies. The chip nodes are connected to the conductive layer and are associated with corresponding signals. Interconnect structures are formed on a surface of the semiconductor chip and connected to the chip nodes, and are symmetrically arranged with respect to the x-axis or y-axis.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor devices. Background Technology

[0002] Packaging technologies (such as three-dimensional integrated circuits (3D-ICs) and chip-on-wafer-on-substrate (CoWoS) technologies) involve stacking semiconductor chips (also known as integrated circuits or dies) together to enhance performance while reducing footprint. Semiconductor chips can take many forms. In one example, a chip includes a chip substrate, chip components formed on the chip substrate (e.g., passive electronic components such as resistors, capacitors, and inductors, and active electronic components such as transistors), conductive layers interconnecting the chip components, and interconnect structures formed on the bottom and / or top surfaces of the conductive layers. Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0004] In some embodiments, a semiconductor device is provided, the semiconductor device comprising a plurality of semiconductor chips stacked on top of each other, wherein a first semiconductor chip of the plurality of semiconductor chips comprises: a substrate; a device layer formed on the substrate and comprising a plurality of chip components; a conductive layer interconnecting the plurality of chip components; a plurality of chip nodes connected to the conductive layer, wherein each of the plurality of chip nodes is associated with a corresponding one of a plurality of signals; and a plurality of first interconnect structures formed on a first surface of the first semiconductor chip and connected to the first chip nodes of the plurality of chip nodes, and symmetrically arranged with respect to at least one x-axis and y-axis.

[0005] According to one embodiment of the present invention, the plurality of first interconnect structures are bonded to a second semiconductor chip or an interposer or a substrate of the plurality of semiconductor chips to form an electrical connection between the first semiconductor chip and the second semiconductor chip.

[0006] According to one embodiment of the present invention, the plurality of first interconnect structures are symmetrical with respect to the x-axis or y-axis, ensuring that the first semiconductor chip is correctly connected to a second semiconductor chip of the plurality of semiconductor chips even when the first semiconductor chip is rotated 180° around the x-axis or y-axis.

[0007] According to one embodiment of the present invention, the plurality of first interconnect structures are symmetrical with respect to the x-axis and y-axis, ensuring that the first semiconductor chip is correctly connected to a second semiconductor chip of the plurality of semiconductor chips even when the first semiconductor chip is rotated 90°, 180° or 270° about an axis transverse to the x-axis and y-axis.

[0008] According to one embodiment of the present invention, it further includes: a plurality of second interconnect structures formed on a second surface of the first semiconductor chip and connected to the first chip node, and arranged symmetrically with respect to the x-axis or y-axis.

[0009] According to one embodiment of the present invention, it further includes: a substrate, wherein the first semiconductor chip is bonded to the substrate.

[0010] According to one embodiment of the present invention, it further includes: an interposer layer, wherein the first semiconductor chip is bonded to the interposer layer.

[0011] In some embodiments, a semiconductor device is provided, the semiconductor device comprising a plurality of semiconductor chips stacked on top of each other, wherein a first semiconductor chip of the plurality of semiconductor chips comprises: a substrate; a device layer formed on the substrate and comprising a plurality of chip components; a conductive layer interconnecting the plurality of chip components; a plurality of chip nodes connected to the conductive layer, wherein each of the plurality of chip nodes is configured to receive a corresponding one of a plurality of signals; and a plurality of first interconnect structures formed on a first surface of the first semiconductor chip and connected to the first chip nodes of the plurality of chip nodes, and arranged symmetrically with respect to the x-axis and y-axis.

[0012] According to one embodiment of the present invention, the chip node is configured to receive data signals transmitted by the first semiconductor chip, data signals transmitted by a second semiconductor chip of the plurality of semiconductor chips, VSS signals, or VDD signals.

[0013] According to one embodiment of the present invention, it further includes: a plurality of second interconnect structures formed on a second surface of the first semiconductor chip and connected to the first chip node, and arranged symmetrically with respect to the x-axis and y-axis. Attached Figure Description

[0014] The embodiments of this utility model can be better understood from the following detailed description and the accompanying drawings. It should be noted that, according to standard industry practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0015] Figure 1A cross-sectional schematic diagram of an exemplary device 100 is provided for various embodiments of the present invention.

[0016] Figure 2 The following is a bottom (or top) view of an exemplary interconnect structure of a semiconductor chip according to various embodiments of the present invention.

[0017] Figure 3 This is a bottom (or top) view of the interconnect structure of a semiconductor chip, according to various embodiments of the present invention.

[0018] Figure 4 This is a bottom (or top) view of the interconnect structure of a semiconductor chip, according to various embodiments of the present invention.

[0019] Figure 5 This is a bottom (or top) view of the interconnect structure of a semiconductor chip, according to various embodiments of the present invention.

[0020] Figure 6 This is a bottom (or top) view of the interconnect structure of a semiconductor chip, according to various embodiments of the present invention.

[0021] Figure 7 This is a bottom (or top) view of the interconnect structure of a semiconductor chip, according to various embodiments of the present invention.

[0022] Figure 8 This is a bottom (or top) view of the interconnect structure of a semiconductor chip 130, according to various embodiments of the present invention.

[0023] Figure 9 This is a bottom (or top) view of the interconnect structure of a semiconductor chip, according to various embodiments of the present invention.

[0024] Figure 10 This is a bottom (or top) view of the interconnect structure of a semiconductor chip, according to various embodiments of the present invention.

[0025] Figure 11 The flowchart illustrates a method for manufacturing an exemplary device according to various embodiments of the present invention.

[0026] The attached figures are labeled as follows:

[0027] 100: Device

[0028] 110: Packaging substrate

[0029] 110': Conductive bump

[0030] 120: Intermediary layer

[0031] 120a: Intermediate substrate

[0032] 120b: Rewiring Layer

[0033] 120c: Intermediate bump

[0034] 130, 140, 150, 160, 170, 180: Semiconductor chips

[0035] 130a: Chip substrate

[0036] 130b: Device layer

[0037] 130c: Conductive layer

[0038] 130d, 200, 300, 400, 500, 600, 700, 800, 900, 1000: Interconnection structure

[0039] 130e: Sealant

[0040] 1100: Method

[0041] 1110, 1120, 1130, 1140, 1150, 1160, 1170: Operations

[0042] Vdd, Vss: Supply voltage

[0043] Tx: Transmitter

[0044] Rx: Receiver

[0045] clk: clock pulse

[0046] clk_tx: Transmitter clock pulse

[0047] clk_rx: Receiver clock pulse Detailed Implementation

[0048] It is important to understand that the following content provides many different embodiments or examples to implement different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the explanation. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment of this disclosure, but may depend on the processing conditions and / or required nature of the components. Furthermore, the embodiments in the following description where the first component is formed above or on the second component include those where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components, such that the first and second components are not in direct contact. In addition, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0049] Furthermore, to facilitate the description of the relationship between one element or component and another (or multiple elements or components) in the accompanying drawings, spatially related terms such as "below," "under," "lower part," "above," "upper part," and similar terms may be used. In addition to the orientations shown in the drawings, spatially related terms also cover different orientations of the device during use or operation. The device may also be positioned otherwise (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly.

[0050] Packaging technologies (such as 3D integrated circuits (3D-ICs) and chip-on-a-bed (CoWoS) technologies) involve stacking semiconductor chips (also known as integrated circuits or dies) together to enhance performance while reducing footprint. Semiconductor chips can take many forms. In one example, a semiconductor chip includes a chip substrate, chip components formed on the chip substrate (e.g., passive electronic components such as resistors, capacitors, and inductors, and active electronic components such as transistors), conductive layers interconnecting the chip components, and interconnect structures formed on the bottom and / or top surfaces of the conductive layers.

[0051] Interconnect structures are used in semiconductor packaging to form electrical connections between stacked semiconductor chips or between semiconductor chips and interposers or substrates. They can be combinations of microbumps, solder balls, copper pillars, metal and dielectric interconnect structures, other forms of interconnects created through, for example, hybrid bonding, tape-automated bonding (TAB), wire bonding, flip-chip bonding, other suitable interconnect structures, or combinations thereof. For example, an electrical connection between a pair of semiconductor chips in a package can be established by aligning an interconnect structure of one semiconductor chip with a node on the other semiconductor chip. The interconnect structure is then bonded to the node using a reflow soldering process. Next, an insulating material is used to fill the gap between the interconnect structure and the semiconductor chip to provide a stronger mechanical connection between the semiconductor chips. The package then undergoes a cooling phase to solidify the solder joints, thereby forming a permanent and reliable electrical connection between the semiconductor chips.

[0052] In some examples, during the fabrication of a device having this packaging technology, the semiconductor chips of the device are oriented or aligned relative to each other to ensure proper bonding using interconnect structures. This step in the fabrication process is prone to error. If misalignment occurs between the semiconductor chips, the interconnect structure connected to a node of one of the semiconductor chips (e.g., receiving a supply voltage) may inadvertently connect to, for example, an electrical ground node of another semiconductor chip, resulting in an electrical short circuit in the device. The systems and methods described in some examples herein mitigate this drawback by symmetrically arranging the interconnect structures of the semiconductor chips relative to the x-axis, y-axis, or both. Regardless of the orientation of the semiconductor chips, this ensures proper bonding of the semiconductor chips to the substrate, interposer, or another semiconductor chip, which will be described in detail below.

[0053] Figure 1 A cross-sectional schematic diagram of an exemplary device 100 is provided for various embodiments of the present invention. Figure 1As shown, an exemplary device 100 (e.g., a semiconductor package (e.g., a three-dimensional integrated circuit or a chip-on-a-substrate)) includes a package substrate 110, an interposer 120, and a plurality of semiconductor chips 130, 140, 150, 160, 170, and 180. The package substrate 110 may have horizontal conductors (or interconnect structures) therein, vertical conductors (or vias) therein, and / or through-silicon vias (TSVs) passing through it, and conductive bumps 110' on its bottom surface. Examples of materials used for the package substrate 110 include silicon, germanium, group III-V semiconductor materials, other suitable semiconductor materials, and the aforementioned alloys. The horizontal conductors, vertical conductors, TSVs, and conductive bumps 110' may be made of copper, aluminum, nickel, barrier metals (e.g., titanium, tungsten, and tantalum), gold, tin, other suitable conductive materials, or the aforementioned alloys. In some embodiments, the package substrate 110 is omitted from the device 100.

[0054] Intermediate layer 120 is mounted on package substrate 110 and includes intermediate substrate 120a, redistribution layer (RDL) 120b formed in intermediate substrate 120a, and intermediate bumps 120c formed on the bottom surface of intermediate substrate 120a. Intermediate layer 120 may further include horizontal conductors (or interconnect structures), vertical conductors (or vias), and / or through-silicon vias (TSVs) embedded in intermediate substrate 120a. Examples of materials used for intermediate substrate 120a may be silicon, germanium, group III-V semiconductor materials, other suitable semiconductor materials, and alloys thereof. Redistribution layer 120b, horizontal conductors, vertical conductors, TSVs, and intermediate bumps 120c may be made of copper, aluminum, nickel, barrier metals (e.g., titanium, tungsten, and tantalum), gold, tin, other suitable conductive materials, or alloys thereof.

[0055] Semiconductor chip 130 includes a chip substrate 130a, a device layer 130b, a conductive layer 130c, and multiple interconnect structures 130d. Examples of materials used for the chip substrate 130a include silicon, germanium, group III-V semiconductor materials, other suitable semiconductor materials, and the aforementioned alloys. The device layer 130b is formed on the bottom surface of the chip substrate 130a and includes multiple chip components, such as passive electronic components (e.g., resistors, capacitors, and inductors) and active electronic components (e.g., transistors). The conductive layer 130c is formed above the chip substrate 130a and the device layer 130b, interconnecting the chip components of the device layer 130b, and includes horizontal wires (or interconnect structures) and vertical wires (or vias). The interconnect structures 130d are formed on the top and bottom surfaces of the conductive layer 130c. The conductive layer 130c and the interconnect structures 130d may be made of copper, aluminum, nickel, barrier metals (e.g., titanium, tungsten, and tantalum), gold, tin, other suitable conductive materials, or the aforementioned alloys.

[0056] Semiconductor chip 130 also includes a sealant 130e covering a chip substrate 130a, a device layer 130b, and a conductive layer 130c, which protects the semiconductor chip 130 from external environmental influences. Examples of materials used for sealant 130e include epoxy mold compounds (EMC), silicone resins, and polyurethane. Semiconductor chip 140 is located between a portion of interposer 120 and semiconductor chip 130. Semiconductor chip 150 is mounted on another portion of interposer 120. Semiconductor chip 160 is bonded to the top surface of semiconductor chip 140. Semiconductor chip 170 is bonded to semiconductor chip 150. Semiconductor chip 180 is stacked on the top surface of semiconductor chip 130.

[0057] Although device 100 is exemplified as a three-dimensional integrated circuit or a chip-on-a-chip package on a substrate, it should be understood that after reading this document, device 100 can be manufactured using other suitable semiconductor packaging technologies.

[0058] Figure 2 This is a bottom (or top) view of the interconnect structure 200 of an exemplary semiconductor chip 130 according to various embodiments of the present invention. Figure 2 As shown, the exemplary interconnect structure 200 includes a supply voltage (Vdd) interconnect structure, a supply voltage (Vss) interconnect structure, a transmitter (Tx) interconnect structure, and a receiver (Rx) interconnect structure. In this exemplary embodiment, the semiconductor chip 130 further includes a plurality of chip nodes connected to the conductive layer 130c. The chip nodes include a supply voltage (Vdd) node that receives the supply voltage (Vdd) signal, a supply voltage (Vss) node that receives the supply voltage (Vss) signal, a plurality of transmitter (Tx) nodes (each transmitter (Tx) node transmits a corresponding one of a plurality of signals, such as a data signal), and a plurality of receiver (Rx) nodes (each receiver (Rx) node receives a corresponding one of a plurality of signals, such as a data signal).

[0059] Please refer to Figure 2Supply voltage (Vdd) interconnect structures are connected to supply voltage (Vdd) nodes and extend along the x-axis and y-axis. In this exemplary embodiment, the supply voltage (Vdd) interconnect structures are symmetrical with respect to the x-axis and y-axis. For example, the number of supply voltage (Vdd) interconnect structures on one side of the x-axis is the same as the number of supply voltage (Vdd) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis. Similarly, the number of supply voltage (Vdd) interconnect structures on one side of the y-axis is the same as the number of supply voltage (Vdd) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other with respect to the y-axis. In some embodiments, the supply voltage (Vdd) interconnect structures are arranged on both sides of the x-axis and y-axis.

[0060] In an alternative embodiment, the supply voltage (Vdd) interconnect structure is asymmetrical with respect to the y-axis. For example, the number of supply voltage (Vdd) interconnect structures on one side of the y-axis is greater than or less than the number of supply voltage (Vdd) interconnect structures on the other side of the y-axis. As another example, the number of supply voltage (Vdd) interconnect structures on one side of the y-axis is the same as the number of supply voltage (Vdd) interconnect structures on the other side of the y-axis. In this further example, the supply voltage (Vdd) interconnect structures do not form a mirror image with respect to the y-axis.

[0061] Similarly, supply voltage (Vss) interconnect structures are connected to supply voltage (Vss) nodes and arranged on both sides of the x-axis and y-axis. In this exemplary embodiment, the supply voltage (Vss) interconnect structures are symmetrical with respect to the x-axis and y-axis. For example, the number of supply voltage (Vss) interconnect structures on one side of the x-axis is the same as the number of supply voltage (Vss) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis. Similarly, the number of supply voltage (Vss) interconnect structures on one side of the y-axis is the same as the number of supply voltage (Vss) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other with respect to the y-axis.

[0062] In an alternative embodiment, the supply voltage (Vss) interconnect structure is asymmetrical with respect to the y-axis. For example, the number of supply voltage (Vss) interconnect structures on one side of the y-axis is greater than or less than the number of supply voltage (Vss) interconnect structures on the other side of the y-axis. As another example, the number of supply voltage (Vss) interconnect structures on one side of the y-axis is the same as the number of supply voltage (Vss) interconnect structures on the other side of the y-axis. In this further example, the supply voltage (Vss) interconnect structures do not form a mirror image with respect to the y-axis.

[0063] Transmitter (Tx) interconnect structures (e.g., a specific number) are connected to specific transmitter (Tx) nodes and arranged on both sides of the x-axis and y-axis. In this exemplary embodiment, the transmitter (Tx) interconnect structures are symmetrical with respect to the x-axis. For example, the number of transmitter (Tx) interconnect structures on one side of the x-axis is the same as the number of transmitter (Tx) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis.

[0064] Furthermore, such as Figure 2 As shown, the transmitter (Tx) interconnect structure is asymmetrical with respect to the y-axis. For example, the number of transmitter (Tx) interconnect structures on one side of the y-axis is greater than or less than the number of transmitter (Tx) interconnect structures on the other side of the y-axis. As another example, the number of transmitter (Tx) interconnect structures on one side of the y-axis is the same as the number of transmitter (Tx) interconnect structures on the other side of the y-axis. In this other example, the transmitter (Tx) interconnect structures do not form a mirror image with respect to the y-axis.

[0065] Similarly, receiver (Rx) interconnect structures (e.g., a specific number) are connected to specific receiver (Rx) nodes and arranged on both sides of the x-axis and y-axis. In this exemplary embodiment, the receiver (Rx) interconnect structures are symmetrical with respect to the x-axis. For example, the number of receiver (Rx) interconnect structures on one side of the x-axis is the same as the number of receiver (Rx) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis.

[0066] Furthermore, such as Figure 2 As shown, the receiver (Rx) interconnect structure is asymmetrical with respect to the y-axis. For example, the number of receiver (Rx) interconnect structures on one side of the y-axis is greater than or less than the number of receiver (Rx) interconnect structures on the other side of the y-axis. As another example, the number of receiver (Rx) interconnect structures on one side of the y-axis is the same as the number of receiver (Rx) interconnect structures on the other side of the y-axis. In this other example, the receiver (Rx) interconnect structures do not form a mirror image with respect to the y-axis.

[0067] As described above, the semiconductor chip 130 includes interconnect structures 200 on its top and bottom surfaces. The interconnect structures 200 on the top surface of the semiconductor chip 130 are symmetrical about the x-axis, and the interconnect structures 200 on the bottom surface of the semiconductor chip 130 are also symmetrical about the x-axis. Even when the semiconductor chip 130 is rotated 180° about the x-axis, this configuration ensures that the semiconductor chip 130 is correctly bonded to another semiconductor chip (e.g., semiconductor chip 140) or an interposer (e.g., interposer 120).

[0068] Figure 3This is a bottom (or top) view of the interconnect structure 300 of an exemplary semiconductor chip 130 according to various embodiments of the present invention. Figure 3 As shown, the difference between the exemplary interconnect structure 300 and the interconnect structure 200 is that the transmitter (Tx) interconnect structures are symmetrical with respect to the y-axis. For example, the number of transmitter (Tx) interconnect structures on one side of the y-axis is the same as the number of transmitter (Tx) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other with respect to the y-axis.

[0069] Furthermore, such as Figure 3 As shown, the transmitter (Tx) interconnect structure is asymmetrical with respect to the x-axis. For example, the number of transmitter (Tx) interconnect structures on one side of the x-axis is greater than or less than the number of transmitter (Tx) interconnect structures on the other side of the x-axis. As another example, the number of transmitter (Tx) interconnect structures on one side of the x-axis is the same as the number of transmitter (Tx) interconnect structures on the other side of the x-axis. In this other example, the transmitter (Tx) interconnect structures do not form a mirror image with respect to the x-axis.

[0070] Similarly, the receiver (Rx) interconnect structures are symmetrical with respect to the y-axis. For example, the number of receiver (Rx) interconnect structures on one side of the y-axis is the same as the number of receiver (Rx) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other with respect to the y-axis.

[0071] Furthermore, such as Figure 3 As shown, the receiver (Rx) interconnect structure is asymmetrical with respect to the x-axis. For example, the number of receiver (Rx) interconnect structures on one side of the x-axis is greater than or less than the number of receiver (Rx) interconnect structures on the other side of the x-axis. As another example, the number of receiver (Rx) interconnect structures on one side of the x-axis is the same as the number of receiver (Rx) interconnect structures on the other side of the x-axis. In this other example, the receiver (Rx) interconnect structures do not form a mirror image with respect to the x-axis.

[0072] As described above, the semiconductor chip 130 includes interconnect structures 300 on its top and bottom surfaces. The interconnect structures 300 on the top surface of the semiconductor chip 130 are symmetrical about the y-axis, and the interconnect structures 300 on the bottom surface of the semiconductor chip 130 are also symmetrical about the y-axis. Even when the semiconductor chip 130 is rotated 180° about the y-axis, this configuration ensures that the semiconductor chip 130 is correctly bonded to another semiconductor chip (e.g., semiconductor chip 140) or an interposer (e.g., interposer 120).

[0073] Figure 4 This is a bottom (or top) view of the interconnect structure 400 of an exemplary semiconductor chip 130 according to various embodiments of the present invention. Figure 3 As shown, the exemplary interconnect structure 400 differs from interconnect structures 200 and 300 in that the transmitter (Tx) interconnect structures are symmetrical with respect to the x and y axes. For example, the number of transmitter (Tx) interconnect structures on one side of the x-axis is the same as the number of transmitter (Tx) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis. Similarly, the number of transmitter (Tx) interconnect structures on one side of the y-axis is the same as the number of transmitter (Tx) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other with respect to the y-axis.

[0074] The receiver (Rx) interconnect structure is symmetrical with respect to the x and y axes. For example, the number of receiver (Rx) interconnect structures on one side of the x-axis is the same as the number of receiver (Rx) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis. Similarly, the number of receiver (Rx) interconnect structures on one side of the y-axis is the same as the number of receiver (Rx) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other with respect to the y-axis.

[0075] As described above, the semiconductor chip 130 includes interconnect structures 400 on its top and bottom surfaces. The interconnect structures 400 on the top surface of the semiconductor chip 130 are symmetrical with respect to the x and y axes, and the interconnect structures 400 on the bottom surface of the semiconductor chip 130 are also symmetrical with respect to the x and y axes. Even when the semiconductor chip 130 is rotated 180° about the x-axis or y-axis, or rotated 90°, 180°, or 270° about an axis transverse to the x and y axes, this configuration ensures that the semiconductor chip 130 is correctly bonded to another semiconductor chip (e.g., semiconductor chip 140) or an interposer (e.g., interposer 120).

[0076] Figure 5 This is a bottom (or top) view of the interconnect structure 500 of an exemplary semiconductor chip 130 according to various embodiments of the present invention. Figure 5 As shown, the exemplary interconnect structure 500 differs from interconnect structures 200, 300, and 400 in that interconnect structure 500 also includes clock pulse (clk) interconnect structures. The chip node also includes clock pulse nodes for transmitting or receiving clock pulse signals. The clock pulse interconnect structures are connected to the clock pulse nodes and are positioned relative to the y-axis. In this exemplary embodiment, the clock pulse interconnect structures are symmetrical about the x-axis. For example, the number of clock pulse (clk) interconnect structures on one side of the x-axis is the same as the number of clock pulse (clk) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other relative to the x-axis.

[0077] In an alternative embodiment, the interconnect structure 500 further includes a second clock pulse (clk) interconnect structure connected to the clock pulse node and positioned relative to the x-axis. In this alternative embodiment, the second clock pulse (clk) interconnect structure is asymmetrical with respect to the y-axis. For example, the number of second clock pulse (clk) interconnect structures on one side of the y-axis is greater than or less than the number of second clock pulse (clk) interconnect structures on the other side of the y-axis. As another example, the number of second clock pulse (clk) interconnect structures on one side of the y-axis is the same as the number of second clock pulse (clk) interconnect structures on the other side of the y-axis. In this further example, the second clock pulse (clk) interconnect structures do not form a mirror image with respect to the y-axis.

[0078] Because multiple interconnect structures are connected to the clock pulse node, the clock pulse signal is more evenly distributed, reducing or eliminating the time difference (skew) between different points of the device 100 that receive the same clock pulse signal.

[0079] As described above, the semiconductor chip 130 includes interconnect structures 500 on its top and bottom surfaces. The interconnect structures 500 on the top surface of the semiconductor chip 130 are symmetrical about the x-axis, and the interconnect structures 500 on the bottom surface of the semiconductor chip 130 are also symmetrical about the x-axis. Even when the semiconductor chip 130 is rotated 180° about the x-axis, this configuration ensures that the semiconductor chip 130 is correctly bonded to another semiconductor chip (e.g., semiconductor chip 140) or an interposer (e.g., interposer 120).

[0080] Figure 6 For the various embodiments of the present invention, another illustrative bottom (or top) view of the interconnect structure 600 of a semiconductor chip 130 is provided. Figure 6 As shown, the exemplary interconnect structure 600 differs from interconnect structures 200, 300, and 400 in that interconnect structure 600 also includes clock pulse (clk) interconnect structures. The chip node also includes clock pulse nodes for transmitting or receiving clock pulse signals. The clock pulse interconnect structures are connected to the clock pulse nodes and are positioned relative to the x-axis. In this exemplary embodiment, the clock pulse interconnect structures are symmetrical about the y-axis. For example, the number of clock pulse (clk) interconnect structures on one side of the y-axis is the same as the number of clock pulse (clk) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other relative to the y-axis.

[0081] In an alternative embodiment, the interconnect structure 600 further includes a second clock pulse (clk) interconnect structure connected to the clock pulse node and positioned relative to the y-axis. In this alternative embodiment, the second clock pulse (clk) interconnect structure is asymmetrical with respect to the x-axis. For example, the number of second clock pulse (clk) interconnect structures on one side of the x-axis is greater than or less than the number of second clock pulse (clk) interconnect structures on the other side of the x-axis. As another example, the number of second clock pulse (clk) interconnect structures on one side of the x-axis is the same as the number of second clock pulse (clk) interconnect structures on the other side of the x-axis. In this further example, the second clock pulse (clk) interconnect structures do not form a mirror image with respect to the x-axis.

[0082] As described above, the semiconductor chip 130 includes interconnect structures 600 on its top and bottom surfaces. The interconnect structures 600 on the top surface of the semiconductor chip 130 are symmetrical about the y-axis, and the interconnect structures 600 on the bottom surface of the semiconductor chip 130 are also symmetrical about the y-axis. Even when the semiconductor chip 130 is rotated 180° about the y-axis, this configuration ensures that the semiconductor chip 130 is correctly bonded to another semiconductor chip (e.g., semiconductor chip 140) or an interposer (e.g., interposer 120).

[0083] Figure 7 For various embodiments of the present invention, another illustrative bottom (or top) view of the interconnect structure 700 of a semiconductor chip 130 is provided. Figure 6 As shown, the exemplary interconnect structure 700 differs from interconnect structures 200, 300, and 400 in that interconnect structure 700 also includes clock pulse (clk) interconnect structures. The chip node also includes clock pulse nodes for transmitting or receiving clock pulse signals. The clock pulse interconnect structures are connected to the clock pulse nodes and are positioned relative to the x-axis and y-axis. In this exemplary embodiment, the clock pulse interconnect structures are symmetrical with respect to the x-axis and y-axis. For example, the number of clock pulse (clk) interconnect structures on one side of the x-axis is the same as the number of clock pulse (clk) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis. Similarly, the number of clock pulse (clk) interconnect structures on one side of the y-axis is the same as the number of clock pulse (clk) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other with respect to the y-axis.

[0084] As described above, the semiconductor chip 130 includes interconnect structures 700 on its top and bottom surfaces. The interconnect structures 700 on the top surface of the semiconductor chip 130 are symmetrical with respect to the x-axis and y-axis, and the interconnect structures 700 on the bottom surface of the semiconductor chip 130 are also symmetrical with respect to the x-axis and y-axis. Even when the semiconductor chip 130 is rotated 180° about the x-axis or y-axis, or rotated 90°, 180°, or 270° about an axis transverse to the x-axis or y-axis, this configuration ensures that the semiconductor chip 130 is correctly bonded to another semiconductor chip (e.g., semiconductor chip 140) or an interposer (e.g., interposer 120).

[0085] Figure 8 For the various embodiments of the present invention, another illustrative bottom (or top) view of the interconnect structure 800 of a semiconductor chip 130 is provided. Figure 8 As shown, the exemplary interconnect structure 800 differs from interconnect structures 200, 300, and 400 in that interconnect structure 800 also includes a transmitter clock pulse (clk_tx) interconnect structure and a receiver clock pulse (clk_rx) interconnect structure. The chip node also includes a transmitter clock pulse (clk_tx) node for transmitting a first clock pulse signal and a receiver clock pulse (clk_rx) node for receiving a second clock pulse signal. The transmitter clock pulse (clk_tx) interconnect structures are connected to the transmitter clock pulse (clk_tx) nodes and are arranged on both sides of the x-axis. In this exemplary embodiment, the transmitter clock pulse (clk_tx) interconnect structures are symmetrical with respect to the x-axis. For example, the number of transmitter clock pulse (clk_tx) interconnect structures on one side of the x-axis is the same as the number of transmitter clock pulse (clk_tx) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis.

[0086] In an alternative embodiment, the interconnect structure 800 further includes second transmitter clock pulse (clk_tx) interconnect structures arranged on both sides of the y-axis. In this alternative embodiment, the second transmitter clock pulse (clk_tx) interconnect structures are asymmetrical with respect to the y-axis. For example, the number of second transmitter clock pulse (clk_tx) interconnect structures on one side of the y-axis is greater than or less than the number of second transmitter clock pulse (clk_tx) interconnect structures on the other side of the y-axis. As another example, the number of second transmitter clock pulse (clk_tx) interconnect structures on one side of the y-axis is the same as the number of second transmitter clock pulse (clk_tx) interconnect structures on the other side of the y-axis. In this further example, the second transmitter clock pulse (clk_tx) interconnect structures do not form a mirror image with respect to the y-axis.

[0087] Similarly, the receiver clock pulse (clk_rx) interconnect structures are connected to the receiver clock pulse (clk_rx) nodes and arranged on both sides of the x-axis. In this exemplary embodiment, the receiver clock pulse (clk_rx) interconnect structures are symmetrical with respect to the x-axis. For example, the number of receiver clock pulse (clk_rx) interconnect structures on one side of the x-axis is the same as the number of receiver clock pulse (clk_rx) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis.

[0088] In an alternative embodiment, the interconnect structure 800 further includes second receiver clock pulse (clk_rx) interconnect structures arranged on both sides of the y-axis. In this alternative embodiment, the second receiver clock pulse (clk_rx) interconnect structures are asymmetrical with respect to the y-axis. For example, the number of second receiver clock pulse (clk_rx) interconnect structures on one side of the y-axis is greater than or less than the number of second receiver clock pulse (clk_rx) interconnect structures on the other side of the y-axis. As another example, the number of second receiver clock pulse (clk_rx) interconnect structures on one side of the y-axis is the same as the number of second receiver clock pulse (clk_rx) interconnect structures on the other side of the y-axis. In this further example, the second receiver clock pulse (clk_rx) interconnect structures do not form a mirror image with respect to the y-axis.

[0089] As described above, the semiconductor chip 130 includes interconnect structures 800 on its top and bottom surfaces. The interconnect structures 800 on the top surface of the semiconductor chip 130 are symmetrical about the x-axis, and the interconnect structures 800 on the bottom surface of the semiconductor chip 130 are also symmetrical about the x-axis. Even when the semiconductor chip 130 is rotated 180° about the x-axis, this configuration ensures that the semiconductor chip 130 is correctly bonded to another semiconductor chip (e.g., semiconductor chip 140) or an interposer (e.g., interposer 120).

[0090] Figure 9 For the various embodiments of the present invention, another illustrative bottom (or top) view of the interconnect structure 900 of a semiconductor chip 130 is provided. Figure 9As shown, the exemplary interconnect structure 900 differs from interconnect structures 200, 300, and 400 in that interconnect structure 900 also includes transmitter clock pulse (clk_tx) interconnect structures and receiver clock pulse (clk_rx) interconnect structures. The chip node also includes a transmitter clock pulse (clk_tx) node for transmitting a first clock pulse signal and a receiver clock pulse (clk_rx) node for receiving a second clock pulse signal. The transmitter clock pulse (clk_tx) interconnect structures are connected to the transmitter clock pulse (clk_tx) nodes and are arranged on both sides of the y-axis. In this exemplary embodiment, the transmitter clock pulse (clk_tx) interconnect structures are symmetrical with respect to the y-axis. For example, the number of transmitter clock pulse (clk_tx) interconnect structures on one side of the y-axis is the same as the number of transmitter clock pulse (clk_tx) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other with respect to the y-axis.

[0091] In an alternative embodiment, the interconnect structure 900 further includes second transmitter clock pulse (clk_tx) interconnect structures arranged on both sides of the y-axis. In this alternative embodiment, the second transmitter clock pulse (clk_tx) interconnect structures are asymmetrical with respect to the x-axis. For example, the number of second transmitter clock pulse (clk_tx) interconnect structures on one side of the x-axis is greater than or less than the number of second transmitter clock pulse (clk_tx) interconnect structures on the other side of the x-axis. As another example, the number of second transmitter clock pulse (clk_tx) interconnect structures on one side of the x-axis is the same as the number of second transmitter clock pulse (clk_tx) interconnect structures on the other side of the x-axis. In this further example, the second transmitter clock pulse (clk_tx) interconnect structures do not form a mirror image with respect to the x-axis.

[0092] Similarly, the receiver clock pulse (clk_rx) interconnect structures are connected to the receiver clock pulse (clk_rx) nodes and arranged on both sides of the y-axis. In this exemplary embodiment, the receiver clock pulse (clk_rx) interconnect structures are symmetrical with respect to the y-axis. For example, the number of receiver clock pulse (clk_rx) interconnect structures on one side of the y-axis is the same as the number of receiver clock pulse (clk_rx) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other with respect to the y-axis.

[0093] In an alternative embodiment, the interconnect structure 900 further includes second receiver clock pulse (clk_rx) interconnect structures arranged on both sides of the x-axis. In this alternative embodiment, the second receiver clock pulse (clk_rx) interconnect structures are asymmetrical with respect to the x-axis. For example, the number of second receiver clock pulse (clk_rx) interconnect structures on one side of the x-axis is greater than or less than the number of second receiver clock pulse (clk_rx) interconnect structures on the other side of the x-axis. As another example, the number of second receiver clock pulse (clk_rx) interconnect structures on one side of the x-axis is the same as the number of second receiver clock pulse (clk_rx) interconnect structures on the other side of the x-axis. In this further example, the second receiver clock pulse (clk_rx) interconnect structures do not form a mirror image with respect to the x-axis.

[0094] As described above, the semiconductor chip 130 includes interconnect structures 900 on its top and bottom surfaces. The interconnect structures 900 on the top surface of the semiconductor chip 130 are symmetrical about the y-axis, and the interconnect structures 900 on the bottom surface of the semiconductor chip 130 are also symmetrical about the y-axis. Even when the semiconductor chip 130 is rotated 180° about the y-axis, this configuration ensures that the semiconductor chip 130 is correctly bonded to another semiconductor chip (e.g., semiconductor chip 140) or an interposer (e.g., interposer 120).

[0095] Figure 10 For various embodiments of the present invention, another exemplary bottom (or top) view of the interconnect structure 1000 of a semiconductor chip 130 is provided. Figure 9 As shown, the exemplary interconnect structure 1000 differs from interconnect structures 200, 300, and 400 in that interconnect structure 1000 also includes a transmitter clock pulse (clk_tx) interconnect structure and a receiver clock pulse (clk_rx) interconnect structure. The chip node also includes a transmitter clock pulse (clk_tx) node for transmitting a first clock pulse signal and a receiver clock pulse (clk_rx) node for receiving a second clock pulse signal. The transmitter clock pulse (clk_tx) interconnect structures are connected to the transmitter clock pulse (clk_tx) nodes and are arranged on both sides of the x-axis and y-axis. In this exemplary embodiment, the transmitter clock pulse (clk_tx) interconnect structures are symmetrical with respect to the x-axis and y-axis. For example, the number of transmitter clock pulse (clk_tx) interconnect structures on one side of the x-axis is the same as the number of transmitter clock pulse (clk_tx) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis. Similarly, the number of transmitter clock pulse (clk_tx) interconnect structures on one side of the y-axis is the same as the number of transmitter clock pulse (clk_tx) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other relative to the y-axis.

[0096] In an alternative embodiment, the interconnect structure 900 further includes transmitter clock pulse (clk_tx) interconnect structures arranged on both sides of the x-axis. In this alternative embodiment, the transmitter clock pulse (clk_tx) interconnect structures are asymmetrical with respect to the x-axis. For example, the number of transmitter clock pulse (clk_tx) interconnect structures on one side of the x-axis is greater than or less than the number of transmitter clock pulse (clk_tx) interconnect structures on the other side of the x-axis. As another example, the number of transmitter clock pulse (clk_tx) interconnect structures on one side of the x-axis is the same as the number of transmitter clock pulse (clk_tx) interconnect structures on the other side of the x-axis. In this further example, the transmitter clock pulse (clk_tx) interconnect structures do not form a mirror image with respect to the x-axis.

[0097] Furthermore, such as Figure 10 As shown, the receiver clock pulse (clk_rx) interconnect structures are connected to the receiver clock pulse (clk_rx) nodes and arranged on both sides of the x-axis and y-axis. In this exemplary embodiment, the receiver clock pulse (clk_rx) interconnect structures are symmetrical with respect to the x-axis and y-axis. For example, the number of receiver clock pulse (clk_rx) interconnect structures on one side of the x-axis is the same as the number of receiver clock pulse (clk_rx) interconnect structures on the other side of the x-axis, and their positions are mirror images of each other with respect to the x-axis. Similarly, the number of receiver clock pulse (clk_rx) interconnect structures on one side of the y-axis is the same as the number of receiver clock pulse (clk_rx) interconnect structures on the other side of the y-axis, and their positions are mirror images of each other with respect to the y-axis.

[0098] As described above, the semiconductor chip 130 includes interconnect structures 1000 on its top and bottom surfaces. The interconnect structures 1000 on the top surface of the semiconductor chip 130 are symmetrical with respect to the x-axis and y-axis, and the interconnect structures 1000 on the bottom surface of the semiconductor chip 130 are also symmetrical with respect to the x-axis and y-axis. Even when the semiconductor chip 130 is rotated 180° about the x-axis or y-axis, or rotated 90°, 180°, or 270° about an axis transverse to the x-axis or y-axis, this configuration ensures that the semiconductor chip 130 is correctly bonded to another semiconductor chip (e.g., semiconductor chip 140) or an interposer (e.g., interposer 120).

[0099] Figure 11 This is a flowchart illustrating a method 1100 for manufacturing an exemplary apparatus using packaging technologies (such as three-dimensional integrated circuits (3D-IC) and chip-on-a-substrate (CoWoS) technology) according to various embodiments of the present invention. Further reference will be made for ease of understanding. Figures 1 to 10Describe example method 1100. It should be understood that method 1100 can also be applied to... Figures 1 to 10 Structures other than the structure. Furthermore, it should be understood that additional operations may be provided before, during, and after method 1100, and in alternative embodiments of method 1100, some of the operations described below may be replaced or eliminated.

[0100] In operation 1110, the system receives an interposer layer 120. In operation 1120, the system mounts a semiconductor chip 140 on the interposer layer 120. In operation 1130, the system bonds the semiconductor chip 130 to the semiconductor chip 140, regardless of its orientation. In an alternative embodiment, the system bonds the semiconductor chip 130 to the interposer layer 120.

[0101] In this exemplary embodiment, operation 1130 includes: the system receiving a chip substrate 130a; the system forming a device layer 130b on the chip substrate 130a; the system interconnecting chip components of the device layer 130b using a conductive layer 130c; the system defining multiple chip nodes connected to the conductive layer 130c (e.g., supply voltage (Vdd) node, supply voltage (Vss) node, transmitter (Tx) node; receiver (Rx) node, transmitter clock pulse (clk_tx) node, receiver clock pulse (...) node...). The system forms a plurality of interconnect structures 130d (e.g., supply voltage (Vdd) interconnect structure, supply voltage (Vss) interconnect structure, transmitter (Tx) interconnect structure, receiver (Rx) interconnect structure, transmitter clock pulse (clk_tx) interconnect structure, and receiver clock pulse (clk_rx) interconnect structure) on the top and bottom surfaces of the conductive layer 130c; and the system covers the chip substrate 130a, device layer 130b and conductive layer 130c with sealant 130e.

[0102] In operation 1140, the system mounts semiconductor chip 150 on interposer 120. In operation 1150, the system stacks semiconductor chips 160, 170, and 180 on interposer 120 or semiconductor chips 130, 140, and 150. In operation 1160, the system receives package substrate 110. In operation 1170, the system mounts the stacked interposer 120 and semiconductor chips 130, 140, 150, 160, 170, and 180 on package substrate 110.

[0103] In one embodiment, the device includes a plurality of semiconductor chips stacked on top of each other. A first semiconductor chip includes a substrate, a device layer, a conductive layer, chip nodes, and a plurality of first interconnect structures. The device layer is formed on the substrate and includes a plurality of chip components. The conductive layer interconnects the plurality of chip components. Chip nodes are connected to the conductive layer and associated with corresponding signals. The first interconnect structures are formed on a first surface of the first semiconductor chip and connected to the first chip nodes, and are symmetrically arranged with respect to an x-axis or y-axis.

[0104] In some other embodiments, a plurality of first interconnect structures are bonded to an interposer or substrate of a plurality of semiconductor chips or a semiconductor device to form an electrical connection between the first semiconductor chips and the second semiconductor chips.

[0105] In some other embodiments, the plurality of first interconnect structures are symmetrical with respect to the x-axis or y-axis, ensuring that the first semiconductor chip is correctly bonded to the second semiconductor chip of the plurality of semiconductor chips even when the first semiconductor chip is rotated 180° about the x-axis or y-axis.

[0106] In some other embodiments, the plurality of first interconnect structures are symmetrical with respect to the x-axis and y-axis, ensuring that the first semiconductor chip is correctly bonded to the second semiconductor chip of the plurality of semiconductor chips even when the first semiconductor chip is rotated 90°, 180° or 270° about an axis transverse to the x-axis and y-axis.

[0107] In some other embodiments, the semiconductor device further includes a plurality of second interconnect structures formed on a second surface of the first semiconductor chip and connected to the first chip node, and arranged symmetrically with respect to the x-axis or y-axis.

[0108] In some other embodiments, the semiconductor device further includes a substrate, wherein the first semiconductor chip is bonded to the substrate.

[0109] In some other embodiments, the semiconductor device further includes an interposer layer, wherein the first semiconductor chip is bonded to the interposer layer.

[0110] In another embodiment, the device includes a plurality of semiconductor chips stacked on top of each other. A first semiconductor chip includes a substrate, a device layer, a conductive layer, and a plurality of first interconnect structures. The device layer is formed on the substrate and includes a plurality of chip components. The conductive layer interconnects the plurality of chip components. Chip nodes are connected to the conductive layer and configured to receive corresponding signals. The plurality of first interconnect structures are formed on a first surface of the first semiconductor chip and connected to the first chip nodes, and are arranged symmetrically with respect to the x-axis and y-axis.

[0111] In some other embodiments, the chip node is configured to receive data signals transmitted by a first semiconductor chip, data signals transmitted by a second semiconductor chip consisting of a plurality of semiconductor chips, a VSS signal, or a VDD signal.

[0112] In some other embodiments, the semiconductor device further includes a plurality of second interconnect structures formed on a second surface of the first semiconductor chip and connected to the first chip node, and arranged symmetrically with respect to the x-axis and y-axis.

[0113] In some other embodiments, the semiconductor device further includes an interposer layer, wherein the first semiconductor chip is bonded to the interposer layer.

[0114] In some other embodiments, the first semiconductor chip is bonded to a second semiconductor chip of a plurality of semiconductor chips.

[0115] In another embodiment, the method includes stacking a plurality of semiconductor chips on top of each other. Manufacturing the semiconductor chips includes: receiving a substrate; forming a device layer on the substrate; interconnecting a plurality of chip components of the device layer with a conductive layer; defining a first chip node connected to the conductive layer, the first chip node corresponding to a first predetermined signal; and connecting a plurality of first interconnect structures to the first chip node. The plurality of first interconnect structures are symmetrically arranged with respect to an x-axis, a y-axis, or both.

[0116] In some other embodiments, the plurality of first interconnect structures are symmetrical with respect to the x-axis or y-axis, ensuring that the first semiconductor chip is correctly bonded to the second semiconductor chip of the plurality of semiconductor chips even when the first semiconductor chip is rotated 180° about the x-axis or y-axis.

[0117] In some other embodiments, the plurality of first interconnect structures are symmetrical with respect to the x-axis and y-axis, ensuring that the first semiconductor chip is correctly bonded to the second semiconductor chip of the plurality of semiconductor chips even when the first semiconductor chip is rotated 90°, 180° or 270° about an axis transverse to the x-axis and y-axis.

[0118] In some other embodiments, the first predetermined signal is transmitted through a device layer and received by another semiconductor chip, a VDD signal, or a VSS signal.

[0119] In some other embodiments, the semiconductor device further includes defining a second chip node connected to the conductive layer and corresponding to a second predetermined signal; and connecting a plurality of second interconnect structures to the second chip node, wherein the plurality of second interconnect structures are symmetrically arranged with respect to the x-axis, y-axis or both.

[0120] In some other embodiments, the second predetermined signal is transmitted through a device layer and received by another semiconductor chip, a VDD signal, or a VSS signal.

[0121] In some other embodiments, the semiconductor device further includes forming a plurality of first interconnect structures on the bottom surface of the semiconductor chip; connecting a plurality of second interconnect structures to a first chip node; and forming a plurality of second interconnect structures on the top surface of the semiconductor chip.

[0122] In some other embodiments, the semiconductor device further includes a substrate and a device layer covered with a sealant.

[0123] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various perspectives. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Multiple semiconductor chips are stacked on top of each other, wherein a first semiconductor chip of the plurality of semiconductor chips comprises: One base; A device layer is formed on the substrate and includes multiple chip components; A conductive layer interconnects these multiple chip components; Multiple chip nodes are connected to the conductive layer, wherein each of the multiple chip nodes is associated with a corresponding one of multiple signals; as well as Multiple first interconnect structures are formed on a first surface of the first semiconductor chip and connected to a first chip node of the multiple chip nodes, and are arranged symmetrically with respect to at least one x-axis and y-axis.

2. The semiconductor device as claimed in claim 1, characterized in that, The plurality of first interconnect structures are bonded to a second semiconductor chip or an interposer or substrate of the plurality of semiconductor chips to form an electrical connection between the first semiconductor chip and the second semiconductor chip.

3. The semiconductor device as claimed in claim 1 or 2, characterized in that, The plurality of first interconnect structures are symmetrical with respect to the x-axis or y-axis, ensuring that the first semiconductor chip is correctly bonded to a second semiconductor chip of the plurality of semiconductor chips even when the first semiconductor chip is rotated 180° around the x-axis or y-axis.

4. The semiconductor device as claimed in claim 1 or 2, characterized in that, The plurality of first interconnect structures are symmetrical with respect to the x-axis and y-axis, ensuring that the first semiconductor chip is correctly connected to a second semiconductor chip of the plurality of semiconductor chips even when the first semiconductor chip is rotated 90°, 180° or 270° about an axis transverse to the x-axis and y-axis.

5. The semiconductor device as claimed in claim 1 or 2, characterized in that, Also includes: Multiple second interconnect structures are formed on a second surface of the first semiconductor chip and connected to the first chip node, and are arranged symmetrically with respect to the x-axis or y-axis.

6. The semiconductor device as claimed in claim 1 or 2, characterized in that, Also includes: A substrate, wherein the first semiconductor chip is bonded to the substrate.

7. The semiconductor device as claimed in claim 1 or 2, characterized in that, Also includes: An interposer layer, wherein the first semiconductor chip is bonded to the interposer layer.

8. A semiconductor device, characterized in that, include: Multiple semiconductor chips are stacked on top of each other, wherein a first semiconductor chip of the plurality of semiconductor chips comprises: One base; A device layer is formed on the substrate and includes multiple chip components; A conductive layer interconnects these multiple chip components; Multiple chip nodes are connected to the conductive layer, wherein each of the multiple chip nodes is configured to receive a corresponding one of multiple signals; as well as Multiple first interconnect structures are formed on a first surface of the first semiconductor chip and connected to a first chip node of the multiple chip nodes, and are arranged symmetrically with respect to the x-axis and y-axis.

9. The semiconductor device as claimed in claim 8, characterized in that, The chip node is configured to receive data signals transmitted by the first semiconductor chip, data signals transmitted by a second semiconductor chip from the plurality of semiconductor chips, VSS signals, or VDD signals.

10. The semiconductor device as claimed in claim 8 or 9, characterized in that, Also includes: Multiple second interconnect structures are formed on a second surface of the first semiconductor chip and connected to the first chip node, and are arranged symmetrically with respect to the x-axis and y-axis.

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