Chip packaging structure

Abstract

A chip packaging structure comprises a photon substrate. The photonic substrate includes a first bonding dielectric layer, a first bonding pad, a first dielectric structure, a first wiring layer, and a waveguide structure. The first wiring layer and the waveguide structure are located in the first dielectric structure, the first wiring layer is provided with a first surface and a second surface opposite to the first surface, the first bonding dielectric layer is located above the first dielectric structure, the second surface faces the first bonding dielectric layer, and the first bonding pad is embedded in the first bonding dielectric layer. The structure includes an electrical substrate bonded to a photonic substrate. The electrical substrate includes a second bonding dielectric layer and a second bonding pad embedded in the second bonding dielectric layer, and the second bonding pad is bonded to the first bonding pad. The structure includes a via structure penetrating the first dielectric structure and extending across the first surface and the second surface of the first wiring layer.

Description

Technical Field

[0001] This utility model relates to a packaging technology, and more particularly to a chip packaging structure with a via structure. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then using photolithography and etching processes to pattern the multiple material layers to form circuit components and elements on the semiconductor substrate.

[0003] Many integrated circuits (ICs) are typically fabricated on semiconductor wafers. Technological advancements in IC materials and design have led to several generations of ICs, each generation being smaller and more complex than the last. Die-hard chips can be packaged using wafer-level processes, and various technologies have been developed for wafer-level packaging. Because chip package structures need to contain multiple chips with various functions, forming a reliable chip package structure with multiple chips and low current path resistance between them is a major challenge. Utility Model Content

[0004] The purpose of this invention is to propose a chip packaging structure to solve at least one of the above-mentioned problems.

[0005] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a photonic substrate, the photonic substrate including a first bonding dielectric layer, a first bonding pad, a first dielectric structure, a first wiring layer, and a waveguide structure. The first wiring layer and the waveguide structure are located within the first dielectric structure. The first wiring layer has a first surface and a second surface opposite to the first surface. The first bonding dielectric layer is located above the first dielectric structure, the second surface faces the first bonding dielectric layer, and the first bonding pad is embedded in the first bonding dielectric layer. The chip packaging structure includes an electrical substrate bonded to the photonic substrate. The electrical substrate includes a second bonding dielectric layer and a second bonding pad embedded in the second bonding dielectric layer, and the second bonding pad is bonded to the first bonding pad. The chip packaging structure includes a via structure penetrating the first dielectric structure and extending across the first surface and the second surface of the first wiring layer.

[0006] According to one embodiment of the present invention, the via structure continuously penetrates the first dielectric structure and the first bonding dielectric layer.

[0007] According to one embodiment of the present invention, the guide hole structure is in direct contact with the second bonding pad.

[0008] According to one embodiment of the present invention, the photonic substrate further includes: a second wiring layer located in the first dielectric structure, wherein the first dielectric structure exposes a surface of the second wiring layer, and the via structure is in direct contact with the second wiring layer.

[0009] According to one embodiment of the present invention, the electrical substrate further includes: a second wiring layer located above the second bonding dielectric layer, wherein the via structure continuously penetrates the first dielectric structure, the first bonding dielectric layer and the second bonding dielectric layer, and is in direct contact with the second wiring layer.

[0010] According to one embodiment of the present invention, the first dielectric structure has a surface facing away from the electrical substrate, and one end of the via structure is closer to the surface than the waveguide structure.

[0011] According to one embodiment of the present invention, one end of the via structure extends into the first wiring layer.

[0012] According to one embodiment of the present invention, the photonic substrate further includes an etch stop layer, and the first wiring layer is located between the etch stop layer and the first bonding dielectric layer.

[0013] According to one embodiment of the present invention, the photonic substrate further includes a semiconductor structure located in the first dielectric structure and between the first wiring layer and the waveguide structure. The first wiring layer is electrically connected to the semiconductor structure, and the first dielectric structure separates the via structure from the semiconductor structure.

[0014] According to one embodiment of the present invention, a surface of the first dielectric structure is flush with a first end surface of the via structure. Attached Figure Description

[0015] The various embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of this utility model.

[0016] Figures 1A to 1J According to some embodiments, cross-sectional views are shown at various stages of the process for forming a chip package structure.

[0017] Figures 2A to 2D According to some embodiments, cross-sectional views are shown at various stages of the process for forming a chip package structure.

[0018] Figure 3 This is a cross-sectional view of a chip package structure according to some embodiments.

[0019] Figure 4 This is a cross-sectional view of a chip package structure according to some embodiments.

[0020] Figure 5 This is a cross-sectional view of a chip package structure according to some embodiments.

[0021] Figure 6 This is a cross-sectional view of a chip package structure according to some embodiments.

[0022] Figure 7 This is a cross-sectional view of a chip package structure according to some embodiments.

[0023] The attached figures are labeled as follows:

[0024] 10: Substrate

[0025] 100 / 200 / 300 / 400 / 500 / 600 / 700: Chip package structure

[0026] 110: Substrate

[0027] 111: Semiconductor layer

[0028] 112: Isolation layer

[0029] 113: Semiconductor layer

[0030] 113a: Semiconductor structure

[0031] 114: Dielectric layer

[0032] 115 / 115M / 115t: Wiring layer

[0033] 115t1: Surface

[0034] 116: Bonding Dielectric Layer

[0035] 116a: Groove

[0036] 117: Joint Pad

[0037] 120: Electrical substrate

[0038] 121: Substrate

[0039] 122: Device

[0040] 123: Dielectric Structure

[0041] 124 / 124M1 / 124t: Wiring layer

[0042] 125: Etching stop layer

[0043] 125a: Groove

[0044] 126: Bonding Dielectric Layer

[0045] 126a: Groove

[0046] 127: Joint Pad

[0047] 130: Photonic substrate

[0048] 131: Dielectric layer

[0049] 131a: Groove

[0050] 132: Waveguide Structure

[0051] 133: Dielectric layer

[0052] 133a: Groove

[0053] 134: Waveguide Structure

[0054] 135: Dielectric layer

[0055] 136a / 136b: Guide hole structure

[0056] 136a1 / 136a2: End

[0057] 137: Dielectric layer

[0058] 137a: Groove

[0059] 138: Joining pad

[0060] 140 / 140A: Conductive bumps

[0061] 210: Etching stop layer

[0062] 212: Groove; 310: Etching termination layer; C: Cutting line

[0063] D1: Distance; D130: Dielectric structure; L1: Length; S1 / S2 / S3: Surface; S4 / S5: End surface; T112 / T112': Thickness; TH1 / TH2: Through hole; V1 / V2 / V3 / V4: Guide hole Detailed Implementation

[0064] The following utility model provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of this utility model. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements so that they are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of the embodiments of this utility model. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0065] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or components in the accompanying drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0066] Those skilled in the art will understand the term "substantially," such as "substantially flat" or "substantially coplanar." In some embodiments, the adjective "substantially" may be removed. When this term is used, it may include embodiments of "entirely," "completely," "all," etc. When this term is used, it may also indicate 90% or higher, such as 95% or higher, particularly 99% or higher, including 100%. Furthermore, the terms "substantially parallel" or "substantially perpendicular" can be interpreted as not excluding minor deviations from a particular setting, and may include deviations of, for example, up to 10°. The term "substantially" does not exclude "all," for example, a composition "substantially free" of Y may be completely free of Y.

[0067] The term "approximately" can vary across different technologies and is within the range of deviations understood by those skilled in the art. The use of "approximately" in conjunction with a specific distance or size can be interpreted as not excluding minor deviations from that specific distance or size. For example, the term "approximately" may include deviations from a specific value of up to 10%, but this invention is not limited thereto. The term "approximately" with respect to the numerical value x may represent x ± 5 or 10% of a specific value, but this invention is not limited thereto.

[0068] The following describes some embodiments of the present invention. Additional steps may be provided before, during, and / or after the stages described in these embodiments. Some of the described steps may be replaced or omitted for different embodiments. Additional components may be added to the semiconductor device structure. Some components described below may be replaced or omitted for different embodiments. Although some embodiments are described with operations performed in a specific order, these operations may also be performed in other logical orders.

[0069] This invention may also include other components and processes. For example, it may include test structures to assist in verifying and testing three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. Test structures may include, for example, test pads formed in redistribution layers or on a substrate, which allow for testing of 3D packages or 3DICs, probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods including intermediate verification of known good chips to increase yield and reduce costs.

[0070] Figures 1A to 1J This is a cross-sectional view showing the process at various stages for forming a chip package structure, according to some embodiments. For example... Figure 1A As shown, according to some embodiments, a substrate 10 is provided. The substrate 10 includes a semiconductor-on-insulator (SOI) substrate (e.g., silicon-on-insulator or germanium-on-insulator). The substrate 10 includes, for example, a wafer or a portion thereof.

[0071] According to some embodiments, substrate 10 includes a semiconductor layer 111, an isolation layer 112, and a semiconductor layer 113. According to some embodiments, the isolation layer 112 is located between semiconductor layer 111 and semiconductor layer 113. According to some embodiments, semiconductor layer 111 is thicker than semiconductor layer 113.

[0072] In some embodiments, semiconductor layers 111 and 113 are made of elemental semiconductor materials (including silicon or germanium) with single-crystal, polycrystalline, or amorphous structures. In some other embodiments, semiconductor layers 111 and 113 are made of compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, alloy semiconductors (e.g., silicon-germanium (SiGe) or gallium arsenide phosphide (GaAsP)), or combinations thereof.

[0073] In some embodiments, various device elements are formed in and / or on the semiconductor layer 113. For simplicity, the device elements are not shown in the figures. Examples of various device elements include modulator devices or other suitable elements.

[0074] In some embodiments, the insulating layer 112 is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorine-dopedsilicate glass (FSG)) or a combination thereof.

[0075] Alternatively, according to some embodiments, the isolation layer 112 comprises a low dielectric constant (k) material or a porous dielectric material, having a k value lower than that of silicon oxide, or a k value lower than about 3.0 or about 2.5.

[0076] like Figure 1B As shown, according to some embodiments, a portion of the semiconductor layer 113 is removed. According to some embodiments, the remaining portion of the semiconductor layer 113 forms a semiconductor structure 113a.

[0077] According to some embodiments, the semiconductor structures 113a are spaced apart from each other. According to some embodiments, the semiconductor structures 113a include modulator devices or other suitable elements. According to some embodiments, the removal process includes photolithography and etching processes.

[0078] like Figure 1C As shown, according to some embodiments, a dielectric layer 114, a wiring layer 115, and a via V1 are formed above the substrate 10. According to some embodiments, the wiring layer 115 and the via V1 are located in the dielectric layer 114.

[0079] According to some embodiments, vias V1 are connected between wiring layers 115 and between wiring layers 115 and semiconductor structure 113a. According to some embodiments, wiring layers 115 are electrically connected to semiconductor structure 113a.

[0080] According to some embodiments, the dielectric layer 114 is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorine-dopedsilicate glass (FSG)) or a combination thereof.

[0081] Alternatively, according to some embodiments, dielectric layer 114 comprises a low dielectric constant (k) material or a porous dielectric material, having a k value lower than that of silicon oxide, or a k value lower than about 3.0 or about 2.5.

[0082] The dielectric layer 114 is formed using chemical vapor deposition (CVD) processes (e.g., low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or high-density plasma chemical vapor deposition (HDPCVD)), atomic layer deposition (ALD), spin coating, physical vapor deposition (PVD), or other suitable processes.

[0083] According to some embodiments, wiring layer 115 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof. According to some embodiments, via V1 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0084] like Figure 1C As shown, according to some embodiments, a bonding dielectric layer 116, a bonding pad 117, and a via V2 are formed above the dielectric layer 114. According to some embodiments, the bonding pad 117 and the via V2 are formed in the bonding dielectric layer 116. According to some embodiments, the via V2 connects the bonding pad 117 and the wiring layer 115.

[0085] According to some embodiments, the bonding dielectric layer 116 is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorine-dopedsilicate glass (FSG)) or a combination thereof. Alternatively, according to some embodiments, the bonding dielectric layer 116 comprises a low dielectric constant (k) material or a porous dielectric material, having a k value lower than that of silicon oxide, or a k value lower than about 3.0 or about 2.5.

[0086] The bonding dielectric layer 116 is formed using chemical vapor deposition (CVD) processes (e.g., low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or high-density plasma chemical vapor deposition (HDPCVD)), atomic layer deposition (ALD), spin coating, physical vapor deposition (PVD), or other suitable processes.

[0087] According to some embodiments, the bonding pad 117 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof. According to some embodiments, the via V2 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof. According to some embodiments, in this step, a substrate 110 is substantially formed.

[0088] like Figure 1DAs shown, according to some embodiments, an electrical substrate 120 is provided. According to some embodiments, the electrical substrate 120 is also referred to as an electrical integrated-circuit (EIC) substrate. According to some embodiments, the electrical substrate 120 includes a substrate 121, a device 122, a dielectric structure 123, a wiring layer 124, a via V3, an etch stop layer 125, a bonding dielectric layer 126, a bonding pad 127, and a via V4.

[0089] The substrate 121 is made of an elemental semiconductor material (including silicon or germanium) with a single-crystal, polycrystalline, or amorphous structure. In some other embodiments, the substrate 121 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, alloy semiconductor such as (silicon germanium (SiGe) or gallium arsenide phosphide (GaAsP)) or a combination thereof.

[0090] In some embodiments, various devices 122 are formed in and / or over the substrate 121. Examples of various devices 122 include active devices, passive devices, other suitable elements, or combinations thereof. Active elements may include transistors or diodes (not shown) formed on the surface of the substrate 121. Passive elements include resistors, capacitors, or other suitable passive devices.

[0091] For example, a transistor can be a metal oxide semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high-voltage transistor, a high-frequency transistor, a p-channel transistor, and / or an n-channel field-effect transistor (PFET / NFET), etc. Various processes, such as front-end-of-line (FEOL) semiconductor manufacturing processes, are performed to form various devices 122. FEOL semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or combinations thereof.

[0092] In some embodiments, an isolation member (not shown) is formed in the substrate 121. The isolation member is used to electrically isolate various devices 122 formed in and / or above the active region on the substrate 121 in the active region. In some embodiments, the isolation member includes a shallow trench isolation (STI) member, a local oxidation of silicon (LOCOS) member, other suitable isolation members, or a combination thereof.

[0093] According to some embodiments, a dielectric structure 123 is formed over a substrate 121 and a device 122. According to some embodiments, wiring layers 124 and vias V3 are formed in the dielectric structure 123. According to some embodiments, vias V3 connect between wiring layers 124 and between wiring layers 124 and device 122.

[0094] According to some embodiments, the dielectric structure 123 is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorine-dopedsilicate glass (FSG)) or a combination thereof. Alternatively, according to some embodiments, the dielectric structure 123 comprises a low dielectric constant (k) material or a porous dielectric material, having a k value lower than that of silicon oxide, or a k value lower than about 3.0 or about 2.5.

[0095] The dielectric structure 123 is formed using chemical vapor deposition (CVD) processes (e.g., low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or high-density plasma chemical vapor deposition (HDPCVD)), atomic layer deposition (ALD), spin coating, physical vapor deposition (PVD), or other suitable processes.

[0096] According to some embodiments, wiring layer 124 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof. According to some embodiments, via V3 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0097] According to some embodiments, an etch stop layer 125 is formed over the wiring layer 124 and the dielectric structure 123. According to some embodiments, the etch stop layer 125 is made of silicon nitride, silicon oxynitride, or the like. According to some embodiments, a bonding dielectric layer 126 is formed over the etch stop layer 125.

[0098] According to some embodiments, a bonding pad 127 is formed in a bonding dielectric layer 126. According to some embodiments, a via V4 connects the bonding pad 127 to the wiring layer 124. According to some embodiments, the via V4 penetrates the etch stop layer 125 and the bonding dielectric layer 126.

[0099] According to some embodiments, the bonding dielectric layer 126 is made of an oxide-containing material (e.g., silicon oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), or the like. According to some embodiments, the bonding pad 127 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof. According to some embodiments, the via V4 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0100] like Figure 1E As shown, according to some embodiments, substrate 110 is bonded to electrical substrate 120. According to some embodiments, bonding pad 117 is bonded to bonding pad 127. According to some embodiments, bonding dielectric layer 116 is bonded to bonding dielectric layer 126.

[0101] like Figure 1F As shown, according to some embodiments, semiconductor layer 111 is removed. For example... Figure 1F As shown, according to some embodiments, the isolation layer 112 is thinned. That is, according to some embodiments, Figure 1E The thickness T112 of the isolation layer 112 is greater than Figure 1F The thickness T112' of the isolation layer 112. According to some embodiments, the thinning process includes a planarization process, such as a chemical mechanical polishing process.

[0102] like Figure 1G As shown, according to some embodiments, a dielectric layer 131 and a waveguide structure 132 are formed above an isolation layer 112. According to some embodiments, the waveguide structure 132 is formed in a groove 131a of the dielectric layer 131.

[0103] According to some embodiments, the dielectric layer 131 is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorine-dopedsilicate glass (FSG)) or a combination thereof.

[0104] Alternatively, according to some embodiments, dielectric layer 131 comprises a low dielectric constant (k) material or a porous dielectric material, having a k value lower than that of silicon oxide, or a k value lower than about 3.0 or about 2.5.

[0105] According to some embodiments, waveguide structure 132 is made of silicon nitride or other suitable waveguide material. According to some embodiments, waveguide structure 132 is formed using a deposition process and a chemical mechanical polishing process.

[0106] like Figure 1G As shown, according to some embodiments, dielectric layer 133 and waveguide structure 134 are formed over dielectric layer 131 and waveguide structure 132. According to some embodiments, waveguide structure 134 is formed in groove 133a of dielectric layer 133.

[0107] According to some embodiments, the dielectric layer 133 is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorine-dopedsilicate glass (FSG)) or a combination thereof.

[0108] Alternatively, according to some embodiments, dielectric layer 133 comprises a low dielectric constant (k) material or a porous dielectric material, having a k value lower than that of silicon oxide, or a k value lower than about 3.0 or about 2.5.

[0109] According to some embodiments, the waveguide structure 134 is made of silicon nitride or other suitable waveguide material. According to some embodiments, the waveguide structure 134 is formed using a deposition process and a chemical mechanical polishing process.

[0110] like Figure 1G As shown, according to some embodiments, dielectric layer 135 is formed over dielectric layer 133 and waveguide structure 134. According to some embodiments, dielectric layers 112, 114, 131, 133 and 135 together with bonding dielectric layer 116 form dielectric structure D130.

[0111] According to some embodiments, the dielectric layer 135 is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorine-dopedsilicate glass (FSG)) or a combination thereof.

[0112] In this step, according to some embodiments, a photonic substrate 130 is substantially formed. According to some embodiments, the photonic substrate 130 is also referred to as a photonic integrated-circuit (PIC) substrate. In some embodiments, the photonic substrate 130 does not include transistors. In some embodiments, the electrical substrate 120 includes more transistors than the photonic substrate 130.

[0113] like Figure 1H As shown, according to some embodiments, a portion of dielectric structure D130 is removed to form vias TH1 and TH2 in dielectric structure D130. According to some embodiments, via TH2 exposes wiring layer 115M in wiring layer 115.

[0114] According to some embodiments, wiring layer 115M is the film layer in wiring layer 115 that is closest to semiconductor layer 113. According to some embodiments, the removal process includes photolithography and etching processes.

[0115] like Figure 1H As shown, according to some embodiments, portions of the bonding dielectric layers 116 and 126 are removed through via TH1 to form a groove 116a in the bonding dielectric layer 116 and a groove 126a in the bonding dielectric layer 126. According to some embodiments, the removal process includes photolithography and etching processes.

[0116] like Figure 1H As shown, according to some embodiments, a portion of the etch stop layer 125 is removed through a via TH1 to form a recess 125a in the etch stop layer 125. According to some embodiments, the recess 125a exposes the wiring layer 124t in the wiring layer 124.

[0117] According to some embodiments, wiring layer 124t is the film layer in wiring layer 124 that is closest to photonic substrate 130. According to some embodiments, the removal process includes photolithography and etching processes.

[0118] like Figure 1H As shown, according to some embodiments, a guide hole structure 136a is formed in the through hole TH1 and the grooves 116a, 126a and 125a, and a guide hole structure 136b is formed in the through hole TH2.

[0119] According to some embodiments, via structure 136a penetrates dielectric structure D130, bonding dielectric layers 116 and 126, and etch stop layer 125. According to some embodiments, via structure 136a is in direct contact with wiring layer 124t. According to some embodiments, dielectric structure D130 separates via structure 136a from semiconductor structure 113a.

[0120] According to some embodiments, each wiring layer 115 has opposing surfaces S1 and S2. According to some embodiments, surface S2 faces the bonding dielectric layer 116. According to some embodiments, via structure 136a extends across surfaces S1 and S2 of wiring layer 115.

[0121] According to some embodiments, the via structure 136a has ends 136a1 and 136a2. According to some embodiments, end 136a1 is closer to the bonding dielectric layer 116 than the wiring layer 115M. According to some embodiments, end 136a1 extends toward the electrical substrate 120. According to some embodiments, the wiring layer 115M is closer to the surface S3 of the dielectric structure D130 than the end 136a1 of the via structure 136a.

[0122] According to some embodiments, the dielectric structure D130 has a surface S3 facing away from the electrical substrate 120. According to some embodiments, the end portion 136a2 of the via structure 136a is closer to surface S3 than the waveguide structures 132 and 134. According to some embodiments, the end portion 136a2 of the via structure 136a is closer to surface S3 of the dielectric structure D130 than the wiring layer 115.

[0123] According to some embodiments, via structures 136a and 136b are made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof. According to some embodiments, via structures 136a and 136b are formed using a deposition process and a chemical mechanical polishing process.

[0124] like Figure 1I As shown, according to some embodiments, dielectric layer 137 and bonding pad 138 are formed over dielectric layer 135. According to some embodiments, bonding pad 138 is formed in a groove 137a of dielectric layer 137.

[0125] According to some embodiments, the dielectric layer 137 is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorine-dopedsilicate glass (FSG)) or a combination thereof.

[0126] Alternatively, according to some embodiments, dielectric layer 137 comprises a low dielectric constant (k) material or a porous dielectric material, having a k value lower than that of silicon oxide, or a k value lower than about 3.0 or about 2.5. According to some embodiments, bonding pad 138 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0127] like Figure 1I As shown, according to some embodiments, conductive bumps 140 are formed above bonding pads 138. According to some embodiments, conductive bumps 140 are made of a conductive material, such as solder material (e.g., tin or an alloy thereof). According to some embodiments, conductive bumps 140 are made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0128] like Figure 1I As shown, according to some embodiments, a dicing process is performed along dicing line C to cut through the photonic substrate 130 and the electrical substrate 120 in order to form a chip package structure 100.

[0129] like Figure 1J As shown, according to some embodiments, one of the chip package structures 100 is flipped vertically. According to some embodiments, since the conductive bump 140A of the conductive bump 140 is electrically connected to the wiring layer 124t only through the bonding pad 138 and the via structure 136a, and does not pass through the wiring layer 115, vias V1, V2 and V4, and bonding pads 117 and 127, the current path resistance between the conductive bump 140A and the wiring layer 124t is reduced. Thus, according to some embodiments, the performance of the chip package structure 100 is improved.

[0130] Figures 2A to 2D This is a cross-sectional view showing the process at various stages for forming a chip package structure, according to some embodiments. For example... Figure 2A As shown, according to some embodiments, the execution Figure 1G The steps.

[0131] According to some embodiments, Figure 2A Photonic substrate 130 is similar to Figure 1G The difference lies in the photonic substrate 130. Figure 2A The photonic substrate 130 also includes an etch stop layer 210 in the dielectric layer 114 and above the wiring layer 115t, and Figure 2A The electrical substrate 120 does not include Figure 1G The etch stop layer 125 of the electrical substrate 120.

[0132] According to some embodiments, wiring layer 115t is the film layer in wiring layer 115 that is closest to electrical substrate 120. According to some embodiments, dielectric structure D130 exposes surface 115t1 of wiring layer 115t.

[0133] According to some embodiments, the wiring layer 115t is located between the etch stop layer 210 and the bonding dielectric layer 116. According to some embodiments, the wiring layer 115t is in direct contact with the bonding dielectric layer 116. According to some embodiments, the etch stop layer 210 is made of silicon nitride, silicon oxynitride, or the like.

[0134] like Figure 2B As shown, according to some embodiments, a portion of dielectric structure D130 is removed to form vias TH1 and TH2 in dielectric structure D130. According to some embodiments, via TH2 exposes wiring layer 115M in wiring layer 115. According to some embodiments, the removal process includes photolithography and etching processes.

[0135] like Figure 2C As shown, according to some embodiments, a portion of the etch stop layer 210 is removed through a via TH1 to form a recess 212 in the etch stop layer 210 and expose a portion of the wiring layer 115t. According to some embodiments, the removal process includes a photolithography process and an etching process.

[0136] According to some embodiments, such as Figure 2C As shown, via structure 136a is formed in through hole TH1 and groove 212, and via structure 136b is formed in through hole TH2. According to some embodiments, the end 136a1 of via structure 136a is in direct contact with wiring layer 115t.

[0137] According to some embodiments, the via structure 136b is spaced apart by a distance D1 from the wiring layer 115t, and the length L1 of the via structure 136a is greater than the distance D1. According to some embodiments, the surface S3 of the dielectric structure D130, the end surface S4 of the via structure 136a, and the end surface S5 of the via structure 136b are substantially flush with each other. According to some embodiments, the via structure 136a is longer than the via structure 136b.

[0138] like Figure 2D As shown, according to some embodiments, the execution Figures 1I to 1J The steps involve forming a dielectric layer 137, bonding pads 138, and conductive bumps 140. In this step, according to some embodiments, a chip package structure 200 is substantially formed.

[0139] According to some embodiments, since the conductive bump 140A of the conductive bump 140 is electrically connected to the wiring layer 115t only through the bonding pad 138 and the via structure 136a, and does not pass through the wiring layer 115t below the wiring layer 115t and the via V1, the current path resistance between the conductive bump 140A and the wiring layer 115t is reduced. In this way, according to some embodiments, the performance of the chip package structure 200 is improved.

[0140] Figure 3 This is a cross-sectional view of a chip package structure 300, according to some embodiments. For example... Figure 3 As shown, according to some embodiments, the chip package structure 300 is similar to Figure 1J The difference between the chip package structure 100 and the chip package structure 300 is that the via structure 136a of the chip package structure 300 extends further into the dielectric structure 123.

[0141] According to some embodiments, the chip package structure 300 further includes an etch stop layer 310 located in the dielectric structure 123 and below the wiring layer 124M1 of the wiring layer 124. According to some embodiments, the wiring layer 124M1 is the film layer in the wiring layer 124 closest to the substrate 121.

[0142] According to some embodiments, via structure 136a penetrates dielectric structure D130, bonding dielectric layers 116 and 126, dielectric structure 123, and etch stop layer 310. According to some embodiments, via structure 136a is in direct contact with wiring layer 124M1. According to some embodiments, via structure 136a is in direct contact with dielectric structure 123.

[0143] According to some embodiments, since the conductive bump 140A of the conductive bump 140 is electrically connected to the wiring layer 124M1 only through the bonding pad 138 and the via structure 136a, and does not pass through the wiring layers 115 and 124, the vias V1, V2 and V4, and the bonding pads 117 and 127, the current path resistance between the conductive bump 140A and the wiring layer 124M1 is reduced. In this way, according to some embodiments, the performance of the chip package structure 300 is improved.

[0144] Figure 4 This is a cross-sectional view of a chip package structure 400, according to some embodiments. For example... Figure 4 As shown, according to some embodiments, the chip package structure 400 is similar to Figure 2D The difference between the chip packaging structure 200 and the chip packaging structure 400 is that the via structure 136a penetrates the dielectric structure D130 and the bonding dielectric layer 116.

[0145] According to some embodiments, via structure 136a is formed in via TH1 of dielectric structure D130 and in groove 116a of bonding dielectric layer 116. According to some embodiments, end portion 136a1 is in direct contact with bonding pad 127. According to some embodiments, end portion 136a1 of via structure 136a extends into bonding pad 127 of electrical substrate 120.

[0146] According to some embodiments, since the conductive bump 140A of the conductive bump 140 is electrically connected to the bonding pad 127 only through the bonding pad 138 and the via structure 136a, and does not pass through the wiring layer 115, vias V1 and V2, and the bonding pad 117, the current path resistance between the conductive bump 140A and the bonding pad 127 is reduced. In this way, according to some embodiments, the performance of the chip package structure 400 is improved.

[0147] Figure 5 This is a cross-sectional view of a chip package structure 500, according to some embodiments. For example... Figure 5 As shown, according to some embodiments, the chip package structure 500 is similar to Figure 1J The chip packaging structure 100 differs in that the electrical substrate 120 does not have Figure 1J The etch stop layer 125, and the via structure 136a of the chip package structure 500 extends into the wiring layer 124t.

[0148] Figure 6 This is a cross-sectional view of a chip package structure 600, according to some embodiments. Figure 6 As shown, according to some embodiments, the chip package structure 600 is similar to Figure 2D The chip packaging structure 200 differs from the photonic substrate 130 in that it does not have... Figure 2D The etch stop layer 210 is provided, and the end 136a1 of the via structure 136a of the chip package structure 600 extends into the wiring layer 115t. According to some embodiments, the via structure 136a is in direct contact with the wiring layer 115t.

[0149] Figure 7 This is a cross-sectional view of a chip package structure 700, according to some embodiments. Figure 7 As shown, according to some embodiments, the chip package structure 700 is similar to Figure 3 The chip packaging structure 300 differs in that the electrical substrate 120 does not have... Figure 3 The etch stop layer 310 is provided, and the end 136a1 of the via structure 136a of the chip package structure 700 extends into the wiring layer 124M1. According to some embodiments, the via structure 136a is in direct contact with the wiring layer 124M1.

[0150] The processes and materials used to form chip package structures 200, 300, 400, 500, 600, and 700 may be similar to or the same as those used to form the aforementioned chip package structure 100. Figures 1A to 7 Components with the same or similar component symbols in the code represent components with the same or similar structure and materials. Therefore, their details will not be elaborated further.

[0151] According to some embodiments, a chip package structure and a method for forming the same are provided. The method for forming the chip package structure involves forming a long via structure that penetrates a photonic integrated circuit (PIC) substrate and is electrically connected to an electronic integrated circuit (EIC) substrate. Since the conductive bumps located beneath the photonic integrated circuit substrate and the long via structure are electrically connected to the electronic integrated circuit substrate only through bonding pads and the long via structure, and do not penetrate wiring layers, vias, or bonding pads, the current path resistance between the conductive bumps and the electronic integrated circuit substrate is reduced. This improves the performance of the chip package structure.

[0152] According to some embodiments, a method for forming a chip package structure is provided. The method includes providing an electrical substrate and a photonic substrate located above and bonded to the electrical substrate. The electrical substrate includes a first bonding dielectric layer and a first bonding pad embedded in the first bonding dielectric layer. The photonic substrate includes a second bonding dielectric layer, a second bonding pad, a dielectric structure, a first wiring layer, and a waveguide structure. The second bonding pad is embedded in the second bonding dielectric layer and bonded to the first bonding pad. The dielectric structure is located above the second bonding dielectric layer. The first wiring layer and the waveguide structure are located within the dielectric structure. The first wiring layer is located between the waveguide structure and the second bonding dielectric layer, and the first wiring layer is in direct contact with the second bonding dielectric layer. The method includes partially removing the dielectric structure to form a first via and a second via in the dielectric structure. The first via penetrates the dielectric structure and exposes the first wiring layer. The method includes forming a first via structure and a second via structure in the first via and the second via, respectively. The first via structure is in direct contact with the first wiring layer, while the second via structure is spaced apart from the first wiring layer.

[0153] In some embodiments, the dielectric structure has a surface facing away from the electrical substrate, and the end of the first via structure is closer to the surface than the waveguide structure. In some embodiments, the photonic substrate further includes a second wiring layer located in the dielectric structure, and the second wiring layer is connected between the first wiring layer and the second via structure. In some embodiments, the end of the first via structure extends into the first wiring layer. In some embodiments, the photonic substrate further includes an etch stop layer, the first wiring layer being located between the etch stop layer and the second bonding dielectric layer, and the formation method further includes: after forming the first via in the dielectric structure, partially removing the etch stop layer to form a groove through the etch stop layer, and the groove exposing a portion of the first wiring layer, wherein the first via structure is also formed in the groove. In some embodiments, the photonic substrate further includes a semiconductor structure located in the dielectric structure and between the first wiring layer and the waveguide structure, the first wiring layer being electrically connected to the semiconductor structure, and the dielectric structure separating the first via structure from the semiconductor structure. In some embodiments, the first via structure is longer than the second via structure. In some embodiments, the first surface of the dielectric structure, the first end surface of the first via structure, and the second end surface of the second via structure are substantially flush with each other. In some embodiments, the second via structure is spaced apart from the first wiring structure by a distance, and the length of the first via structure is greater than the distance. In some embodiments, the second bonding dielectric layer is bonded to the first bonding dielectric layer.

[0154] According to some embodiments, a method for forming a chip package structure is provided. The method includes providing an electrical substrate and a photonic substrate located above and bonded to the electrical substrate. The electrical substrate includes a first bonding dielectric layer and a first bonding pad embedded in the first bonding dielectric layer. The photonic substrate includes a second bonding dielectric layer, a second bonding pad, a first dielectric structure, and a waveguide structure. The second bonding pad is embedded in the second bonding dielectric layer and bonded to the first bonding pad. The first dielectric structure is located above the second bonding dielectric layer, and the waveguide structure is located within the first dielectric structure. The method includes partially removing the first dielectric structure, the second bonding dielectric layer, and the first bonding dielectric layer to form a via through the first dielectric structure, the second bonding dielectric layer, and the first bonding dielectric layer. The method includes forming a via structure in the via.

[0155] In some embodiments, the electrical substrate further includes a second dielectric structure located below the first bonding dielectric layer, and a first wiring layer and a second wiring layer located within the second dielectric structure. The first wiring layer is located between the second wiring layer and the via structure, and the via structure is in direct contact with the first wiring layer. In some embodiments, the via structure extends into the first wiring layer. In some embodiments, the electrical substrate further includes a second dielectric structure located below the first bonding dielectric layer and a wiring layer located within the second dielectric structure. Partial removal of the first dielectric structure, the second bonding dielectric layer, and the first bonding dielectric layer further includes: partially removing the second dielectric structure located above the wiring layer. The via further penetrates the second dielectric structure above the wiring layer, and the via structure is in direct contact with the wiring layer. In some embodiments, the via structure is in direct contact with the second dielectric structure.

[0156] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a photonic substrate, the photonic substrate including a first bonding dielectric layer, a first bonding pad, a first dielectric structure, a first wiring layer, and a waveguide structure. The first wiring layer and the waveguide structure are located within the first dielectric structure. The first wiring layer has a first surface and a second surface opposite to the first surface. The first bonding dielectric layer is located above the first dielectric structure, the second surface faces the first bonding dielectric layer, and the first bonding pad is embedded in the first bonding dielectric layer. The chip packaging structure includes an electrical substrate bonded to the photonic substrate. The electrical substrate includes a second bonding dielectric layer and a second bonding pad embedded in the second bonding dielectric layer, and the second bonding pad is bonded to the first bonding pad. The chip packaging structure includes a via structure penetrating the first dielectric structure and extending across the first surface and the second surface of the first wiring layer.

[0157] In some embodiments, the via structure continuously penetrates the first dielectric structure and the first bonding dielectric layer. In some embodiments, the via structure directly contacts the second bonding pad. In some embodiments, the photonic substrate further includes a second wiring layer located in the first dielectric structure. The first dielectric structure exposes the surface of the second wiring layer, and the via structure directly contacts the second wiring layer. In some embodiments, the electrical substrate further includes a second wiring layer located above the second bonding dielectric layer. The via structure continuously penetrates the first dielectric structure, the first bonding dielectric layer, and the second bonding dielectric layer, and directly contacts the second wiring layer.

[0158] The components of several embodiments are summarized above to facilitate a better understanding of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A chip package structure, characterized by, Comprising: a photonic substrate including a first bonding dielectric layer, a first bonding pad, a first dielectric structure, a first wiring layer, and a waveguide structure, wherein the first wiring layer and the waveguide structure are located in the first dielectric structure, the first wiring layer has a first surface and a second surface opposite to the first surface, the first bonding dielectric layer is located above the first dielectric structure, the second surface faces the first bonding dielectric layer, and the first bonding pad is embedded in the first bonding dielectric layer; an electric substrate bonded to the photonic substrate, wherein the electric substrate includes a second bonding dielectric layer and a second bonding pad embedded in the second bonding dielectric layer, and the second bonding pad is bonded to the first bonding pad; and a via structure penetrating through the first dielectric structure and extending across the first surface and the second surface of the first wiring layer.

2. The chip package structure of claim 1, wherein, The via structure continuously penetrates through the first dielectric structure and the first bonding dielectric layer.

3. The chip package structure of claim 2, wherein, The via structure is in direct contact with the second bonding pad.

4. The chip package structure of claim 1, wherein, The photonic substrate further comprises: a second wiring layer located in the first dielectric structure, wherein the first dielectric structure exposes a surface of the second wiring layer, and the via structure is in direct contact with the second wiring layer.

5. The chip package structure of claim 1, wherein, The electric substrate further comprises: a second wiring layer located above the second bonding dielectric layer, wherein The via structure continuously penetrates through the first dielectric structure, the first bonding dielectric layer, and the second bonding dielectric layer, and is in direct contact with the second wiring layer.

6. The chip package structure of claim 1, wherein, The first dielectric structure has a surface facing away from the electric substrate, and an end portion of the via structure is closer to the surface than the waveguide structure.

7. The chip package structure of claim 1, wherein, An end portion of the via structure extends into the first wiring layer.

8. The chip package structure of claim 1, wherein, The photonic substrate further comprises an etch stop layer, and the first wiring layer is located between the etch stop layer and the first bonding dielectric layer.

9. The chip package structure of claim 1, wherein, The photonic substrate further comprises a semiconductor structure located in the first dielectric structure and between the first wiring layer and the waveguide structure, the first wiring layer is electrically connected to the semiconductor structure, and the first dielectric structure separates the via structure and the semiconductor structure.

10. The chip package structure of claim 1, wherein, A surface of the first dielectric structure and a first end surface of the via structure are flush with each other.

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