GPIO (General Purpose Input / Output) pin compatibility testing device

Abstract

The utility model provides a general purpose input / output (GPIO) pin compatibility testing device, which comprises a Cat.1 communication module and a plurality of resistors, the Cat.1 communication module is provided with a plurality of groups of input pins and a plurality of groups of output pins, and the plurality of resistors are connected between the input pins and the output pins in the plurality of groups of input pins and the plurality of output pins; according to different connections between the input pin and the output pin, changing the pin state of the input pin or the output pin through an instruction of the Cat.1 module; therefore, different GPIO test schemes can be selected according to different GPIOs, the design and development cost is reduced, the automatic production line changing time is shortened, the construction of a production test environment is facilitated, the compatibility of a test tool is improved, and the cost of a test fixture is saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication module testing, and particularly relates to a GPIO pin compatibility testing device. BACKGROUND

[0002] At present, the Cat.1 module io testing scheme basically uses module pins for self-checking. When developing and designing, two GPIO pins of the module are selected, and resistors are used to connect them two by two. That is, the ping-pong testing scheme is used. For example, a high level is output by using the a pin, and whether the high level is input by using the b pin is detected. After the detection is completed, a high level is output by using the b pin, and whether the high level is input by using the a pin is detected. After the hardware confirmation scheme is confirmed, the software writes the GPIO combination scheme into the firmware of the module. In the production testing, the module is self-checked through relevant instructions. If there is an exception, the module sends instructions to the abnormal io pin.

[0003] The existing scheme has poor compatibility. For modules with the same package size, different GPIOs of the module will have different io testing schemes, which greatly increases the testing cost, such as testing tooling, production line change labor cost, and the like.

[0004] For example, a communication module GPIO pin function testing device is disclosed in the Chinese patent network with the application number 202223358103.4. In the technical scheme involved in the patent, a test PC, a direct current power supply, and a test fixture are composed. The test PC is used to send test instructions and receive statistical test results. The direct current power supply is used to power the measured module. The test fixture is used to fix the measured module and connect the GPIO pins of the measured module. The test fixture includes a one-way pin serial port, multiple wires, multiple first resistors, and a second resistor. The pin serial port is connected with the test PC. The first resistor is an isolation current-limiting functional resistor, and the second resistor is a pull-down functional resistor. One end of each first resistor is connected with a measured module pin GPIO through a wire. The other end of the first resistor is connected with other first resistors through a wire and then connected to the ground through the second resistor. It is difficult to compatible with the testing method of multiple GPIOs. Practical new type content

[0005] The purpose of the present application is to reduce the cost of GPIO testing and make the testing scheme more flexible by using multiple GPIO combination schemes.

[0006] In order to achieve the above purpose, the present application patent adopts the following technical scheme.

[0007] The test device comprises a Cat.1 communication module and a plurality of resistors, the Cat.1 communication module is provided with a plurality of input pins and a plurality of output pins, and a plurality of resistors are connected between the plurality of input pins and the plurality of output pins; according to the connection of different input pins and output pins, the pin state of the input pin or the output pin is changed through the instruction of the Cat.1 module.

[0008] As preferred, the resistance connection relationship between the plurality of input pins and the plurality of output pins in the Cat.1 communication module is that the plurality of input pins are connected with a plurality of input resistors, the plurality of input resistors are connected in parallel, and are connected with an output resistor, and the output resistor is connected with an output pin.

[0009] As preferred, the resistance R63 is connected between the pin 9 and the pin 8 of the Cat.1 communication module; the resistance R64 is connected between the pin 77 and the pin 24 of the Cat.1 module; the resistance R65 is connected between the pin 96 and the pin 24 of the Cat.1 communication module; and the resistance R66 is connected between the pin 76 and the pin 24 of the Cat.1 module.

[0010] As preferred, the input pin 2 of the Cat.1 module is connected with the second end of the input resistor R10; the input pin 44 of the Cat.1 module is connected with the second end of the input resistor R11; the input pin 55 of the Cat.1 module is connected with the second end of the input resistor R12; the input pin 104 of the Cat.1 module is connected with the second end of the input resistor R13; the input pin 3 of the Cat.1 module is connected with the second end of the input resistor R14; the input pin 4 of the Cat.1 module is connected with the second end of the input resistor R15; the input pin 63 of the Cat.1 module is connected with the second end of the input resistor R16; the input pin 57 of the Cat.1 module is connected with the second end of the input resistor R17; the first ends of the input resistors R10 to R17 are all connected with the second end of the output resistor R70, and the first end of the output resistor R70 is connected with the output pin 21.

[0011] As preferred, the input pin 109 of the Cat. 1 module is connected with the second end of the input resistor R67; the input pin 98 of the Cat. 1 module is connected with the second end of the input resistor R18; the input pin 56 of the Cat. 1 module is connected with the second end of the input resistor R19; the input pin 105 of the Cat. 1 module is connected with the second end of the input resistor R20; the input pin 107 of the Cat. 1 module is connected with the second end of the input resistor R21; the input pin 66 of the Cat. 1 module is connected with the second end of the input resistor R22; the input pin 50 of the Cat. 1 module is connected with the second end of the input resistor R23; the input pin 62 of the Cat. 1 module is connected with the second end of the input resistor R24; the input pin 102 of the Cat. 1 module is connected with the second end of the input resistor R25; the first end of the input resistors R67, R18 to R25 are all connected with the second end of the output resistor R71, and the first end of the output resistor R71 is connected with the output pin 22.

[0012] As preferred, the input pin 67 of the Cat. 1 module is connected with the second end of the input resistor R68; the input pin 51 of the Cat. 1 module is connected with the second end of the input resistor R26; the input pin 49 of the Cat. 1 module is connected with the second end of the input resistor R28; the input pin 80 of the Cat. 1 module is connected with the second end of the input resistor R29; the input pin 38 of the Cat. 1 module is connected with the second end of the input resistor R30; the input pin 16 of the Cat. 1 module is connected with the second end of the input resistor R31; the input pin 108 of the Cat. 1 module is connected with the second end of the input resistor R31; the input pin 81 of the Cat. 1 module is connected with the second end of the input resistor R32; the input pin 103 of the Cat. 1 module is connected with the second end of the input resistor R33; the first end of the input resistors R68, R26 to R33 are all connected with the second end of the output resistor R72, and the first end of the output resistor R72 is connected with the output pin 23.

[0013] As preferred, the input pin 58 of the Cat.1 module is connected with the second end of the input resistor R34; the input pin 106 of the Cat.1 module is connected with the second end of the input resistor R35; the input pin 69 of the Cat.1 module is connected with the second end of the input resistor R36; the input pin 82 of the Cat.1 module is connected with the second end of the input resistor R37; the input pin 39 of the Cat.1 module is connected with the second end of the input resistor R38; the input pin 74 of the Cat.1 module is connected with the second end of the input resistor R39; the input pin 61 of the Cat.1 module is connected with the second end of the input resistor R40; the input pin 64 of the Cat.1 module is connected with the second end of the input resistor R41; the first end of the input resistors R34 to R41 is connected with the second end of the output resistor R73, and the first end of the output resistor R73 is connected with the output pin 30.

[0014] As preferred, the input pin 29 of the Cat.1 module is connected with the second end of the input resistor R49; the input pin 100 of the Cat.1 module is connected with the second end of the input resistor R50; the input pin 85 of the Cat.1 module is connected with the second end of the input resistor R51; the input pin 33 of the Cat.1 module is connected with the second end of the input resistor R52; the input pin 78 of the Cat.1 module is connected with the second end of the input resistor R53; the input pin 97 of the Cat.1 module is connected with the second end of the input resistor R54; the input pin 68 of the Cat.1 module is connected with the second end of the input resistor R55; the first end of the input resistors R49 to R55 is connected with the second end of the output resistor R75, and the first end of the output resistor R75 is connected with the output pin 32.

[0015] The technical scheme of the present application has the advantages of greatly reducing the design and development cost, reducing the automatic production line changing time, and facilitating the construction of the production test environment. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is a pin schematic diagram of the Cat.1 module.

[0017] Figure 2 It is a pin schematic diagram of the Cat.1 module.

[0018] Figure 3 It is a pin schematic diagram of the Cat.1 module.

[0019] Figures 4 to 10 It is a schematic diagram of the resistance connection between the input pin and the output pin.

[0020] Figure 11 It is a schematic diagram of the resistance connection between the pins.

[0021] Figure 12 It is a USB circuit schematic diagram. DETAILED DESCRIPTION

[0022] Embodiment 1, the embodiment discloses a circuit connection mode of the device, and refers to Figures 1 to 11 .

[0023] Referring to Figures 1 to 10 , the input pin 2 of the Cat.1 module is connected with the second end of the resistor R10; the input pin 44 of the Cat.1 module is connected with the second end of the input resistor R11; the input pin 55 of the Cat.1 module is connected with the second end of the input resistor R12; the input pin 104 of the Cat.1 module is connected with the second end of the input resistor R13; the input pin 3 of the Cat.1 module is connected with the second end of the input resistor R14; the input pin 4 of the Cat.1 module is connected with the second end of the input resistor R15; the input pin 63 of the Cat.1 module is connected with the second end of the input resistor R16; the input pin 57 of the Cat.1 module is connected with the second end of the input resistor R17; the connection relationship between the input resistor 10 and the input resistor 17 is parallel connection, and the first end of the resistor R10 to the resistor R17 is connected with the second end of the output resistor R70; the first end of the output resistor R70 is connected with the output pin 21 of the Cat.1 module.

[0024] The input pin 109 of the Cat.1 module is connected with the second end of the input resistor R67; the input pin 98 of the Cat.1 module is connected with the second end of the input resistor R18; the input pin 56 of the Cat.1 module is connected with the second end of the input resistor R19; the input pin 105 of the Cat.1 module is connected with the second end of the input resistor R20; the input pin 107 of the Cat.1 module is connected with the second end of the input resistor R21; the input pin 66 of the Cat.1 module is connected with the second end of the input resistor R22; the input pin 50 of the Cat.1 module is connected with the second end of the input resistor R23; the input pin 62 of the Cat.1 module is connected with the second end of the input resistor R24; the input pin 102 of the Cat.1 module is connected with the second end of the input resistor R25; the connection mode between the resistor R67, the resistor R18 to the resistor R25 is parallel connection, and the first end of the resistor R67, the resistor R18 to the resistor R25 is connected with the second end of the output resistor R71, and the first end of the output resistor R71 is connected with the output pin 22 of the Cat.1 module.

[0025] The input pin 67 of the Cat.1 module is connected with the second end of the input resistor R68; the input pin 51 of the Cat.1 module is connected with the second end of the input resistor R26; the input pin 49 of the Cat.1 module is connected with the second end of the resistor R27; the input pin 80 of the Cat.1 module is connected with the second end of the input resistor R28; the input pin 38 of the Cat.1 module is connected with the second end of the input resistor R29; the input pin 16 of the Cat.1 module is connected with the second end of the input resistor R30; the input pin 108 of the Cat.1 module is connected with the second end of the input resistor R31; the input pin 81 of the Cat.1 module is connected with the second end of the input resistor R32; the input pin 103 of the Cat.1 module is connected with the second end of the input resistor R33; the resistors R68, R26 to R33 are connected in parallel, and the first ends of the resistors R68, R26 to R33 are connected with the second end of the output resistor R72; and the first end of the output resistor R72 is connected with the output pin 23 of the Cat.1 module.

[0026] The input pin 58 of the Cat.1 module is connected with the second end of the input resistor R34; the input pin 106 of the Cat.1 module is connected with the second end of the input resistor R35; the input pin 69 of the Cat.1 module is connected with the second end of the input resistor R36; the input pin 82 of the Cat.1 module is connected with the second end of the input resistor R37; the input pin 39 of the Cat.1 module is connected with the second end of the input resistor R38; the input pin 74 of the Cat.1 module is connected with the second end of the input resistor R39; the input pin 61 of the Cat.1 module is connected with the second end of the input resistor R40; the input pin 64 of the Cat.1 module is connected with the second end of the input resistor R41; and the first ends of the resistors R34 to R41 are connected with the second end of the output resistor R73; and the first end of the output resistor R73 is connected with the output pin 30 of the Cat.1 module.

[0027] The input pin 99 of the Cat.1 module is connected to the second end of the input resistor R69; the input pin 83 of the Cat.1 module is connected to the second end of the input resistor R42; the input pin 31 of the Cat.1 module is connected to the second end of the input resistor R43; the input pin 28 of the Cat.1 module is connected to the second end of the input resistor R44; the input pin 53 of the Cat.1 module is connected to the second end of the input resistor R45; the input pin 75 of the Cat.1 module is connected to the second end of the input resistor R46; the input pin 84 of the Cat.1 module is connected to the second end of the input resistor R47; the input pin 86 of the Cat.1 module is connected to the second end of the input resistor R48; and the first ends of the resistors R69, R42 to R48 are all connected to the second end of the output resistor R74, and the first end of the output resistor R74 is connected to the output pin 19 of the Cat.1 module.

[0028] The input pin 29 of the Cat.1 module is connected to the second end of the input resistor R49; the input pin 100 of the Cat.1 module is connected to the second end of the input resistor R50; the input pin 85 of the Cat.1 module is connected to the second end of the input resistor R51; the input pin 33 of the Cat.1 module is connected to the second end of the input resistor R52; the input pin 78 of the Cat.1 module is connected to the second end of the input resistor R53; the input pin 97 of the Cat.1 module is connected to the second end of the input resistor R54; the input pin 68 of the Cat.1 module is connected to the second end of the input resistor R55; and the first ends of the resistors R49 to R55 are all connected to the second end of the output resistor R75; and the first end of the output resistor R75 is connected to the output pin 32 of the Cat.1 module.

[0029] The input pin 101 of the Cat.1 module is connected to the second end of the input resistor R56; the input pin 54 of the Cat.1 module is connected to the second end of the input resistor R57; the input pin 79 of the Cat.1 module is connected to the second end of the input resistor R58; the input pin 87 of the Cat.1 module is connected to the second end of the input resistor R59; the input pin 20 of the Cat.1 module is connected to the second end of the input resistor R60; the input pin 26 of the Cat.1 module is connected to the second end of the input resistor R61; the input pin 52 of the Cat.1 module is connected to the second end of the input resistor R62; the input pin 33 of the Cat.1 module is connected to the second end of the input resistor R3; and the first ends of the resistors R3, R56 to R62 are all connected to the second end of the output resistor R76, and the first end of the output resistor R76 is connected to the output pin 25 of the Cat.1 module.

[0030] Referring to Figure 11Pin 9 of the Cat.1 module is connected with the second end of the resistor R63, the first end of the resistor R63 is connected with pin 8 of the Cat.1 module; pin 77 of the Cat.1 module is connected with the second end of the resistor R64, the first end of the resistor R64 is connected with pin 24 of the Cat.1 module; pin 96 of the Cat.1 module is connected with the resistor R65, the first end of the resistor R65 is connected with pin 24 of the Cat.1 module; pin 76 of the Cat.1 module is connected with the second end of the resistor R66, the first end of the resistor R66 is connected with pin 24 of the Cat.1 module.

[0031] With reference to Figure 12 Pin 1 of the USB module is connected with the second end of the resistor R6, the second end of the resistor R6 is connected with the second end of the capacitor C3 and the capacitor C4, the first end of the capacitor C3 and the capacitor C4 are grounded; pin 1 of the USB module is connected with the first end of the TVS diode D1; the first end of the TVS diode D2 is connected with pin 2 of the USB module; the first end of the TVS diode D3 is connected with pin 3 of the USB module; the second end of the TVS diode D1, the TVS diode D2 and the TVS diode D3 are connected with pin 5 and pin 0 of the USB module.

[0032] Embodiment 2 discloses the working mode of the device.

[0033] Group all GPIOs of the same package size product, and divide them into several groups according to actual production requirements, wherein the resistance between the output pin and the input pin is 1k ohm; according to the grouping result of the GPIO, input pin 2, input pin 44, input pin 55, input pin 104, input pin 3, input pin 4, input pin 63 and input pin 57 are used as input pins; output pin 21 is used as an output pin; all GPIO functions in the module are released through software, and firmware is synthesized and downloaded into the module flash; the module is configured through input and output instructions.

[0034] First, the output pin 21 is set to output low level state by the instruction, and the input pin 2, the input pin 44, the input pin 55, the input pin 104, the input pin 3, the input pin 4, the input pin 63 and the input pin 57 are input detected, the module is automatically detected by the set instruction, and the detected input pin result is output by the set instruction, if the detection is low level, the module output result is 0, and the problem occurs, if the detection is high level, the module output result is 1, and the abnormality occurs; after the above operation, the output pin is set to output high level state, and the input pin 2, the input pin 44, the input pin 55, the input pin 104, the input pin 3, the input pin 4, the input pin 63 and the input pin 57 are input detected, and the detected result is output, if it is high level, the module output result is 1, and no problem occurs; if it is low level, the module output result is 0, and the abnormality occurs.

[0035] For products of the same package size, if the GPIO definitions are different, the device involved in the utility model can also detect GPIO, if the 2 pins of the module are not defined in testing a certain product, the pin state of the pin is cancelled by the instruction when testing, and the other pins are tested.

[0036] Alternatively, for products of the same package size, if all GPIO groups of the product need input pins: input pin 109, input pin 98, input pin 56, input pin 105, input pin 107, input pin 66, input pin 50, input pin 62 and input pin 102; the output pin is output pin 102; when testing, the pin state of the input pin 2, the input pin 44, the input pin 55, the input pin 104, the input pin 3, the input pin 4, the input pin 63, the input pin 57 and the output pin 21 is cancelled by the instruction, and the pin state of the input pin 109, the input pin 98, the input pin 56, the input pin 105, the input pin 107, the input pin 66, the input pin 50, the input pin 62, the input pin 102 and the output pin 22 is added by the instruction, and the GPIO of the product is detected.

[0037] Or, for the same package size product, if the product of all GPIO groups, the need for input pins are: input pin 67, input pin 51, input pin 49, input pin 80, input pin 38, input pin 16, input pin 108, input pin 81 and input pin 103; the need for output pins are: output pin 23; when testing, by canceling the input pin 2, input pin 44, input pin 55, input pin 104, input pin 3, input pin 4, input pin 63, input pin 57 and output pin 21; then by adding the input pin 67, input pin 51, input pin 49, input pin 80, input pin 38, input pin 16, input pin 108, input pin 81, input pin 103 and output pin 23, the pin state of the product is realized. The GPIO detection is carried out.

[0038] Or, for the same package size product, if the product of all GPIO groups, the need for input pins are: input pin 58, input pin 106, input pin 69, input pin 82, input pin 39, input pin 74, input pin 61 and input pin 64; the output pin is output pin 30; when testing, by canceling the input pin 2, input pin 44, input pin 55, input pin 104, input pin 3, input pin 4, input pin 63, input pin 57 and output pin 21; then by adding the input pin 58, input pin 106, input pin 69, input pin 82, input pin 39, input pin 74, input pin 61, input pin 64 and output pin 30, the pin state of the product is realized. The GPIO detection is carried out.

[0039] Similarly, for other products of the same package size, if the input interface and output group of these products are: input pin 99, input pin 83, input pin 31, input pin 28, input pin 53, input pin 75, input pin 84, input pin 86 and output pin 19, input pin 29, input pin 100, input pin 85, input pin 33, input pin 33, input pin 78, input pin 97, input pin 68 and output pin 32, or input pin 101, input pin 54, input pin 79, input pin 87, input pin 20, input pin 26, input pin 52, input pin 33 and output pin 25.

[0040] When the GPIO test is performed, the pin states of input pin 2, input pin 44, input pin 55, input pin 104, input pin 3, input pin 4, input pin 63, input pin 57 and output pin 21 are cancelled by the instruction, and the pin states of input pin 99, input pin 83, input pin 31, input pin 28, input pin 53, input pin 75, input pin 84, input pin 86 and output pin 19, input pin 29, input pin 100, input pin 85, input pin 33, input pin 33, input pin 78, input pin 97, input pin 68 and output pin 32, or input pin 101, input pin 54, input pin 79, input pin 87, input pin 20, input pin 26, input pin 52, input pin 33 and output pin 25 are added by the instruction, so as to realize the GPIO detection of the product.

[0041] It should be noted that the Cat.1 module configuration instruction is used to change the pin state of the output pin or the input pin. According to the different input pins and output pins corresponding to different GPIO groups and the connection mode of different input pins and different output pins, the Cat.1 module configuration instruction is used to change the state of the output pin or the input pin, so that the device involved can be compatible with more types of product GPIO tests, and the tooling does not need to be replaced, thereby saving the cost of the fixture and the cost of development and design.

[0042] The utility model discloses through concrete embodiment in -depth explanation its purpose, technical scheme and beneficial effect, but these embodiments only as example, with show the application mode of invention, and do not constitute the limit of the protection scope of the utility model. We explicitly point out, any reasonable modification, equivalent replacement or technical improvement under the spirit and principle of the utility model should be brought into the protection scope of the utility model. This means, as long as these changes do not deviate from the core idea and basic function of invention, they should be protected by the patent right. The protection scope of the utility model should be extensive, including all direct obvious variants and the non-obvious innovation that can be reasonably deduced by technical experts according to the utility model disclosure. This broad protection aims to promote further research and development based on the utility model, while ensuring that its innovativeness and practicality are comprehensively legally protected.

Claims

1. A GPIO pin compatible testing device, characterized in that, It includes: Cat.1 communication module and a plurality of resistors, the Cat.1 communication module is provided with a plurality of groups of input pins and a plurality of groups of output pins, among the input pins and the output pins, a plurality of resistors are connected between the input pins and the output pins; according to the connection of different input pins and output pins, the pin state of the input pin or the output pin is changed through the instruction.

2. The GPIO pin compatible testing device of claim 1, wherein, In the Cat.1 communication module, the resistance connection relationship between the input pin and the output pin is that a plurality of input pins are connected with a plurality of input resistors, a plurality of input resistors are connected in parallel and connected with an output resistor, and the output resistor is connected with an output pin.

3. The GPIO pin compatible testing device of claim 1, wherein, The resistance R63 is connected between the pin 9 and the pin 8 of the Cat.1 communication module; the resistance R64 is connected between the pin 77 and the pin 24; the resistance R65 is connected between the pin 96 and the pin 24 of the Cat.1 communication module; and the resistance R66 is connected between the pin 76 and the pin 24.

4. A GPIO pin compatible testing device according to any one of claims 1 to 3, wherein, The input pin 2 is connected with the second end of the input resistor R10; the input pin 44 is connected with the second end of the input resistor R11; the input pin 55 is connected with the second end of the input resistor R12; the input pin 104 is connected with the second end of the input resistor R13; the input pin 3 is connected with the second end of the input resistor R14; the input pin 4 is connected with the second end of the input resistor R15; the input pin 63 is connected with the second end of the input resistor R16; the input pin 57 is connected with the second end of the input resistor R17; the first ends of the input resistors R10 to R17 are all connected with the second end of the output resistor R70, and the first end of the output resistor R70 is connected with the output pin 21.

5. A GPIO pin compatible testing device according to any one of claims 1 to 3, wherein, The input pin 109 is connected with the second end of the input resistor R67; the input pin 98 is connected with the second end of the input resistor R18; the input pin 56 is connected with the second end of the input resistor R19; the input pin 105 is connected with the second end of the input resistor R20; the input pin 107 is connected with the second end of the input resistor R21; the input pin 66 is connected with the second end of the input resistor R22; the input pin 50 is connected with the second end of the input resistor R23; the input pin 62 is connected with the second end of the input resistor R24; the input pin 102 is connected with the second end of the input resistor R25; the first ends of the input resistors R67, R18 to R25 are all connected with the second end of the output resistor R71, and the first end of the output resistor R71 is connected with the output pin 22.

6. A GPIO pin compatible testing device according to any one of claims 1 to 3, wherein, The input pin 67 is connected with the second end of the input resistor R68; the input pin 51 is connected with the second end of the input resistor R26; the input pin 49 is connected with the second end of the input resistor R28; the input pin 80 is connected with the second end of the input resistor R29; the input pin 38 is connected with the second end of the input resistor R30; the input pin 16 is connected with the second end of the input resistor R31; the input pin 108 is connected with the second end of the input resistor R31; the input pin 81 is connected with the second end of the input resistor R32; the input pin 103 is connected with the second end of the input resistor R33; the first end of the input resistors R68, R26 to R33 is connected with the second end of the output resistor R72, and the first end of the output resistor R72 is connected with the output pin 23.

7. A GPIO pin compatible testing device according to any one of claims 1 to 3, wherein, The input pin 58 is connected with the second end of the input resistor R34; the input pin 106 is connected with the second end of the input resistor R35; the input pin 69 is connected with the second end of the input resistor R36; the input pin 82 is connected with the second end of the input resistor R37; the input pin 39 is connected with the second end of the input resistor R38; the input pin 74 is connected with the second end of the input resistor R39; the input pin 61 is connected with the second end of the input resistor R40; the input pin 64 is connected with the second end of the input resistor R41; the first end of the input resistors R34 to R41 is connected with the second end of the output resistor R73, and the first end of the output resistor R73 is connected with the output pin 30.

8. A GPIO pin compatible testing device according to any one of claims 1 to 3, wherein, The input pin 29 is connected with the second end of the input resistor R49; the input pin 100 is connected with the second end of the input resistor R50; the input pin 85 is connected with the second end of the input resistor R51; the input pin 33 is connected with the second end of the input resistor R52; the input pin 78 is connected with the second end of the input resistor R53; the input pin 97 is connected with the second end of the input resistor R54; the input pin 68 is connected with the second end of the input resistor R55; the first end of the input resistors R49 to R55 is connected with the second end of the output resistor R75, and the first end of the output resistor R75 is connected with the output pin 32.

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