Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device, which comprises a semiconductor substrate provided with an active area and a peripheral area positioned on the outer side of the active area; the field oxide layer is arranged on the semiconductor substrate and exposes the active region; the metal electrode layer is arranged in the active region, forms electric contact with the semiconductor substrate, extends to one side, deviating from the semiconductor substrate, of the field oxide layer from the active region to the peripheral region so as to be partially overlapped with the field oxide layer, and is provided with an upper surface and a lower surface; a hollowed-out part penetrating from the upper surface to the lower surface is formed in the area, overlapped with the field oxide layer, of the metal electrode layer, and a groove which does not penetrate through the field oxide layer and is communicated with the hollowed-out part is formed in the part, corresponding to the hollowed-out part, of the field oxide layer; and the passivation layer is arranged on the field oxide layer, extends from the peripheral region to the active region to cover the metal electrode layer and exposes at least part of the upper surface. By arranging the hollow part and the groove communicated with the hollow part, the performance and the reliability of the device can be improved.

Description

TECHNICAL FIELD

[0001] The embodiment of the utility model relates to the technical field of semiconductor and electronic device, especially relates to a semiconductor device. BACKGROUND

[0002] In a semiconductor device such as silicon carbide (SiC) power device, the thermal expansion problem of passivation layer medium and metal has important influence on device performance and reliability. Due to the thermal expansion coefficient of metal such as aluminum and passivation layer is inconsistent, there is thermal stress in the passivation layer formed at high temperature, and this thermal stress can cause passivation layer deformation, cracking and even peeling off and other performance deterioration phenomena, and further affect the performance and reliability of the device. Therefore, how to effectively reduce the performance deterioration phenomenon of the passivation layer is a technical problem to be solved at present. UTILITY MODEL CONTENT

[0003] Therefore, the embodiment of the utility model provides a semiconductor device to reduce the performance deterioration phenomenon of the passivation layer and improve the performance and reliability of the device.

[0004] Specifically, the embodiment of the utility model provides a power semiconductor device, for example, including: semiconductor substrate, field oxide layer, metal electrode layer and passivation layer. The semiconductor substrate has an active region and a peripheral region located outside the active region. The field oxide layer is arranged on the semiconductor substrate and exposes the active region. The metal electrode layer is arranged on the active region and forms an electrical contact with the semiconductor substrate, and extends from the active region to the side of the field oxide layer away from the semiconductor substrate to partially overlap with the field oxide layer, wherein the metal electrode layer has an upper surface away from the semiconductor substrate and a lower surface facing the semiconductor substrate, the region of the metal electrode layer overlapping with the field oxide layer is formed with a hollow part penetrating from the upper surface to the lower surface, and the part of the field oxide layer corresponding to the hollow part is provided with a groove not penetrating the field oxide layer and communicating with the hollow part. The passivation layer is arranged on the field oxide layer and extends from the peripheral region to the active region to cover the metal electrode layer and expose at least part of the upper surface.

[0005] The above-mentioned embodiments of the utility model can have the following beneficial effects: by forming the hollow part penetrating from the upper surface to the lower surface in the area of the metal electrode layer overlapping with the field oxide layer, the thermal expansion expansion space of the metal electrode layer can be enlarged, thereby the phenomenon of performance deterioration of the passivation layer caused by the difference of thermal expansion coefficient between the metal and the passivation layer medium can be effectively reduced, so as to improve the performance and reliability of the device. Furthermore, by arranging the groove not penetrating the field oxide layer and communicating with the hollow part in the part of the field oxide layer corresponding to the hollow part, the field oxide layer with the groove partially overlaps with the metal electrode layer to form the field plate structure, which can not only guarantee the effect of isolating the electric field but also provide the structure similar to the water storage groove, so as to prevent the device failure caused by the invasion of water vapor and improve the high temperature and high humidity reverse bias reliability of the device. In addition, the embodiments of the utility model are also helpful to enlarge the selection range of the thermal expansion coefficient adaptation of the metal and the passivation layer material. BRIEF DESCRIPTION OF DRAWINGS

[0006] The specific embodiments of the utility model will be described in detail below with reference to the drawings.

[0007] Figure 1A A partial structure sectional view of a semiconductor device provided by the embodiments of the utility model is shown.

[0008] Figure 1B A structure top view of the semiconductor device shown in Figure 1A

[0009] Figure 1C Another structure top view of the semiconductor device shown in Figure 1A

[0010] A partial structure sectional view of a semiconductor substrate in a manufacturing method of a semiconductor device provided by the embodiments of the utility model is shown. Figure 2

[0011] A partial structure sectional view after forming the field oxide layer on the semiconductor substrate shown in Figure 3 Figure 2 A partial structure sectional view after forming the metal material layer on the semiconductor substrate and the field oxide layer shown in

[0012] Figure 4 A partial structure sectional view after patterning the metal material layer to form the metal electrode layer but without forming the groove shown in Figure 3

[0013] A structure top view after removing the mask layer shown in Figure 5A Figure 4

[0014] Figure 5B Figure 4 ​​​​​​

[0015] Figure 6A Another partial structure section schematic view of a semiconductor device is provided for the embodiment of the utility model.

[0016] Figure 6B Another partial structure section schematic view of a semiconductor device is provided for the embodiment of the utility model.

[0017] Figure 7A Another partial structure section schematic view of a semiconductor device is provided for the embodiment of the utility model.

[0018] Figure 7B For Figure 7A The overhead view of the semiconductor device is shown.

[0019] Figure 8 For Figure 4 The partial structure section schematic view that the metal material layer is patterned to form the metal electrode layer and forms the recess is shown.

[0020] Figure 9A Another partial structure section schematic view of a semiconductor device is provided for the embodiment of the utility model.

[0021] Figure 9B Another partial structure section schematic view of a semiconductor device is provided for the embodiment of the utility model.

[0022]

Main figure mark explanation

[0023] 10, semiconductor device;11, semiconductor substrate;110, silicon carbide substrate;112, silicon carbide epitaxial layer;13, field oxide layer;130, recess;15, metal electrode layer;15T, upper surface;15B, lower surface;15H, hollow part;17, passivation layer;AA, active area;PA, peripheral area;R, radius;D, distance;150H, via hole;13a, first part;13b, intermediate part;13c, second part;M1, M2, mask layer;150, metal material layer;18, organic protective layer;19, second electrode layer. Specific implementation

[0024] In order to make the above purpose, features and advantages of the utility model more obvious and easy to understand, the specific implementation of the utility model is described in detail below.

[0025] In order to make the ordinary skilled in the art better understand the technical scheme of the present application, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the ordinary skilled in the art without creative labor should belong to the scope of protection of the present application.

[0026] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not have to be used to describe a particular order or sequence. It should be understood that the terms thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0027] It should also be noted that the division of the plurality of embodiments in the present application is only for the convenience of description, and should not constitute a special limitation. The features in the various embodiments can be combined and mutually referenced without contradiction.

[0028] Reference should be made to Figure 1AThe utility model embodiment provides a kind of semiconductor device 10, for example include: semiconductor substrate 11, field oxide layer 13, metal electrode layer 15 and passivation layer 17.The semiconductor substrate 11 has active area AA and the peripheral area PA located in the active area AA outside.The field oxide layer 13 is arranged on the semiconductor substrate 11 and exposes the active area AA.The metal electrode layer 15 is arranged in the active area AA and forms electrical contact with the semiconductor substrate 11, and from the active area AA towards the peripheral area PA extends to the side of the field oxide layer 13 away from the semiconductor substrate 11 to partially overlap with the field oxide layer 13, wherein the metal electrode layer 15 has upper surface 15T away from the semiconductor substrate 11 and lower surface 15B facing the semiconductor substrate 11, the region of the metal electrode layer 15 overlapping with the field oxide layer 13 is formed with hollow part 15H from the upper surface 15T through to the lower surface 15B, the part of the field oxide layer 13 corresponding to the hollow part 15H is provided with groove 130 not through the field oxide layer 13 and communicated with the hollow part 15H.The passivation layer 17 is arranged on the field oxide layer 13, and from the peripheral area PA towards the active area AA extends to cover the metal electrode layer 15 and expose part of the upper surface 15T, also can expose all upper surface 15T.

[0029] The utility model embodiment forms hollow part 15H from the upper surface 15T through to the lower surface 15B in the region of the metal electrode layer 15 overlapping with the field oxide layer 13, which can expand the thermal expansion expansion space of metal electrode layer 15, thereby can effectively reduce the phenomenon of passivation layer performance deterioration caused by the difference of metal and passivation layer medium thermal expansion coefficient, to facilitate the performance and reliability of device improvement.Furthermore, the part of the field oxide layer 13 corresponding to the hollow part 15H is provided with groove 130 not through the field oxide layer 13 and communicated with the hollow part 15H, and the field oxide layer 13 with groove 130 partially overlaps with the metal electrode layer 15 to form field plate structure, that is, it can guarantee the role of isolating electric field and provide similar water tank structure, which is beneficial to prevent device failure caused by water vapor invasion and improve high temperature and high humidity reverse bias reliability of device.In addition, the utility model embodiment is also helpful to expand the selection range of thermal expansion coefficient adaptation of metal and passivation layer material.

[0030] For example, in terms of layer structure, the semiconductor substrate 11 includes, for example, silicon carbide substrate 110 and silicon carbide epitaxial layer 112, and the silicon carbide epitaxial layer 112 is located on the side of the silicon carbide substrate 110 facing the metal electrode layer 15.The crystal form of the silicon carbide substrate 110 is, for example, 4H SiC or 6H SiC, and the doping concentration range of the silicon carbide substrate 110 is, for example, 1E19-5E20 / cm 3The thickness of the silicon carbide epitaxial layer 112 is in the range of 1 μm to 100 μm, and the doping concentration is in the range of 1E14 to 5E16 / cm 3 The doping concentration of the silicon carbide substrate 110 is greater than that of the silicon carbide epitaxial layer 112. The field oxide layer 13 is, for example, a thermal oxide layer, or a CVD-deposited oxide layer, or a multilayer stack structure of a thermal oxide layer and a CVD-deposited oxide layer, with a thickness in the range of 0.5 μm to 1 μm, such as 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm or 1 μm, and a material of, for example, silicon oxide. The overlap length of the metal electrode layer 15 and the field oxide layer 13 is, for example, greater than 5 μm and less than or equal to 50 μm, and the thickness of the metal electrode layer 15 is, for example, 3 μm to 6 μm, such as 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm or 6 μm. By way of example, the metal electrode layer 15 includes, but is not limited to, any one or a combination of multiple metals of aluminum (Al), silver (Ag), copper (Cu) and the like, and a metal solid solution formed by any one or multiple metals of Al, Ag, Cu and the like and an element of nitrogen (N), silicon (Si) and the like; the metal electrode layer 15 can be a single-layer metal structure or a multilayer metal structure. The passivation layer 17 can be deposited by stacking any one or multiple dielectric layers of silicon oxide, silicon nitride, silicon oxynitride and the like; by way of example, the thickness of the passivation layer 17 is in the range of 0.6 μm to 4 μm, such as 0.6 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm or 4 μm.

[0031] In some embodiments, referring to Figure 1B The hollow part 15H includes a plurality of through holes 150H arranged at intervals along the circumference of the metal electrode layer 15. It is worth mentioning that, in other embodiments, the hollow part 15H can also be an annular through hole extending along the circumference of the metal electrode layer 15, for example, a closed annular through hole to separate the metal electrode layer 15 into two parts spaced apart from each other, or an open annular through hole. Furthermore, the shape of the through hole 150H can be circular, square, annular, strip-shaped or arc-shaped, etc. In addition, it is worth mentioning that Figure 1B The plurality of through holes 150H shown are distributed on four sides of the metal electrode layer 15, but the embodiments of the present application are not limited thereto, and they can also be located on only opposite sides of the metal electrode layer 15, or on three sides, or even on only one side of the metal electrode layer 15.

[0032] In some embodiments, referring to Figure 1BThe passivation layer 17 exposes the plurality of through holes 150H and includes a first portion 13a and a second portion 13c located on opposite sides of the hollowed portion 15H, respectively, which are separated from each other.

[0033] In some embodiments, referring to Figure 1C The passivation layer 17 exposes the plurality of through holes 150H and includes a first portion 13a and a second portion 13c located on opposite sides of the hollowed portion 15H, respectively, and an intermediate portion 13b connecting the first portion 13a and the second portion 13c, and the intermediate portion 13b is located between two adjacent through holes 150H in the circumferential direction of the metal electrode layer 15.

[0034] In some embodiments, referring to Figure 1B and Figure 1C The through hole 150H is, for example, a circular hole with a radius R greater than or equal to 2 μm, such as 2 μm, 5 μm, 10 μm, or 20 μm, and the distance D between two adjacent through holes 150H in the circumferential direction of the metal electrode layer 15 is, for example, greater than or equal to 5 μm, such as 5 μm, 6 μm, 7 μm, 9 μm, 10 μm, 15 μm, 20 μm, 25 μm, or 30 μm. In other embodiments, a single through hole 150H can also be a square hole with a side length greater than or equal to 4 μm.

[0035] In some embodiments, referring to Figure 6A The semiconductor device, for example, includes an organic protective layer 18 disposed on the passivation layer 17 and extending from the peripheral area PA toward the active area AA to cover the metal electrode layer 15 and expose the upper surface 15T of at least part of the metal electrode layer 15, and the organic protective layer 18 exposes the plurality of through holes 150H of the hollowed portion 15H. As an example, the organic protective layer 18 is, for example, an organic material such as polyimide, and has a thickness of, for example, 5 μm-10 μm.

[0036] In some embodiments, referring to Figure 6B The semiconductor device, for example, includes an organic protective layer 18 disposed on the passivation layer 17 and extending from the peripheral area PA toward the active area AA to cover the metal electrode layer 15 and expose the upper surface 15T of at least part of the metal electrode layer 15, and the organic protective layer 18 fills the plurality of through holes 150H of the hollowed portion 15H and the groove 130 to better prevent device failure caused by water vapor intrusion. As an example, the organic protective layer 18 is, for example, an organic material such as polyimide, and has a thickness of, for example, 5 μm-10 μm.

[0037] For the purpose of more clearly understanding the semiconductor device 10 of the embodiments of the present application, the following will describe an example of a manufacturing method of the semiconductor device 10 shown in Figure 2 、 Figure 3 、 Figure 4 、 Figure 5A and Figure 5B by way of example, which can include the following steps. Figure 1A The manufacturing method of the semiconductor device 10 shown in

[0038] First, after cleaning and polishing the n-type silicon carbide substrate 110, an n-type silicon carbide epitaxial layer 112 is grown on the silicon carbide substrate 110 by MOCVD, with a thickness of, for example, 1 μm-100 μm and a doping concentration of, for example, 1E14-5E16 / cm 3 , and polishing and grinding are performed to obtain the semiconductor substrate 11 shown in Figure 2 .

[0039] Next, a layer of silicon oxide with a thickness of, for example, 0.5 μm-1 μm is deposited on the silicon carbide epitaxial layer 112, and a photoresist is spin-coated and patterned on the surface of the deposited silicon oxide to obtain a mask layer M1, and then the deposited silicon oxide is opened by etching, for example, wet etching, to form a contact hole to expose a portion of the silicon carbide epitaxial layer 112, and obtain the field oxide layer 13 shown in Figure 3 . The wet etching conditions are, for example, a temperature of 20°C-40°C and a time of 20 minutes-60 minutes.

[0040] After the field oxide layer 13 is formed, the mask layer M1 is removed, and a metal material layer 150 with a thickness of, for example, 3 μm-6 μm is deposited on the semiconductor substrate 11, the metal material layer 150 being filled in the contact hole and extending to cover the field oxide layer 13, as shown in Figure 4 .

[0041] Then, a photoresist is spin-coated on the metal material layer 150, and the spin-coated photoresist is patterned by photolithography to obtain a mask layer M2, and then the topography of the mask layer M2 is transferred to the metal material layer 150 by dry etching to obtain a metal electrode layer 15 with a hollow portion 15H, as shown in Figure 5A . After the mask layer M2 is removed, the structure shown in Figure 5B is obtained, in which the hollow portion 15H includes a plurality of through holes 150H arranged at intervals in the circumferential direction of the metal electrode layer 15, and a single through hole 150H is, for example, a circular hole with a radius R greater than or equal to 2 μm, or a square hole with a side length greater than or equal to 4 μm, etc. By performing an annealing process on the structure shown in Figure 5B , the metal electrode layer 15 can form an electrical contact, for example, a Schottky contact, with the silicon carbide epitaxial layer 112 of the semiconductor substrate 11.

[0042] After the metal electrode layer 15 is prepared, a silicon oxide layer and a silicon nitride layer are sequentially deposited, each having a thickness of 0.3 μm-2 μm, for example. Then, dry etching is performed on the deposited silicon oxide layer and silicon nitride layer to remove the silicon oxide layer and silicon nitride layer within the hollow portion 15H and etch a groove 130 in the field oxide layer 13, thereby obtaining Figure 1A the passivation layer 17 and the field oxide layer 13 provided with the groove 130.

[0043] Further, an organic protective layer 18 having a thickness of 5 μm-10 μm, for example, can also be formed by spin-coating polyimide and baking after exposure, as shown in Figure 6A or Figure 6B Additionally, a 2 μm thick Ti / Ni / Ag can also be evaporated on the side of the silicon carbide substrate 110 of the semiconductor substrate 11 that is away from the silicon carbide epitaxial layer 112 as Figure 6A or Figure 6B the second electrode layer 19, as shown.

[0044] In some embodiments, referring to Figure 7A and Figure 7B , the passivation layer 17 is filled into the plurality of through holes 150H of the hollow portion 15H and the groove 130 of the field oxide layer 13, for example, to better prevent device failure caused by water vapor intrusion. Accordingly, in the method of manufacturing the semiconductor device, the groove 130 in the field oxide layer 13 and the hollow portion 15H of the metal electrode layer 15 can be formed simultaneously in the same etching process, for example, as shown in Figure 8 .

[0045] In some embodiments, referring to Figure 9A , the semiconductor device includes an organic protective layer 18, for example, which is disposed on the passivation layer 17 and extends from the peripheral region PA toward the active area AA to cover the metal electrode layer 15 and expose at least part of the upper surface 15T of the metal electrode layer 15, and the organic protective layer 18 exposes the part of the passivation layer 17 filled into the plurality of through holes 150H of the hollow portion 15H. As an example, the organic protective layer 18 is an organic material such as polyimide, for example, and has a thickness of 5 μm-10 μm, for example.

[0046] In some embodiments, referring to Figure 9BThe semiconductor device, for example, includes an organic protective layer 18 disposed on the passivation layer 17 and extending from the peripheral area PA toward the active area AA to cover the metal electrode layer 15 and expose the upper surface 15T of at least part of the metal electrode layer 15, and the organic protective layer 18 covers the part of the passivation layer 17 filling the plurality of through holes 150H of the hollow part 15H, so as to better prevent the device failure caused by the water vapor intrusion. As an example, the organic protective layer 18 is, for example, an organic material such as polyimide, and the thickness thereof is, for example, 5 μm-10 μm.

[0047] It should be noted that the above semiconductor device can be a MOSFET (metal-oxide semiconductor FET) device, or a SBD (Schottky barrier diode) device. Herein, no limitation is made.

[0048] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the technical solution of the present application, and any simple modification, equivalent change and modification of the above embodiment according to the technical essence of the present application still belong to the scope of the technical solution of the present application.

Claims

1. A semiconductor device, characterized by, Comprising: a semiconductor substrate having an active region and a peripheral region located outside the active region; a field oxide layer disposed on the semiconductor substrate and exposing the active region; a metal electrode layer disposed on the active region and forming electrical contact with the semiconductor substrate, and extending from the active region toward the peripheral region to a side of the field oxide layer facing away from the semiconductor substrate to partially overlap with the field oxide layer, wherein the metal electrode layer has an upper surface facing away from the semiconductor substrate and a lower surface facing toward the semiconductor substrate, a region of the metal electrode layer overlapping with the field oxide layer is formed with a hollow portion penetrating from the upper surface to the lower surface, and a portion of the field oxide layer corresponding to the hollow portion is provided with a groove not penetrating the field oxide layer and communicating with the hollow portion; and a passivation layer disposed on the field oxide layer and extending from the peripheral region toward the active region to cover the metal electrode layer and expose at least part of the upper surface. The hollow portion comprises a plurality of through holes arranged at intervals along the circumference of the metal electrode layer.

2. The semiconductor device according to claim 1, wherein The passivation layer exposes the plurality of through holes and comprises a first portion and a second portion located on opposite sides of the hollow portion, respectively, and the first portion and the second portion are separated from each other.

3. The semiconductor device of claim 2, wherein, The passivation layer exposes the plurality of through holes, the passivation layer comprises a first portion and a second portion located on opposite sides of the hollow portion, respectively, and an intermediate portion connecting the first portion and the second portion, and the intermediate portion is located between adjacent two through holes in the circumference of the metal electrode layer.

4. The semiconductor device of claim 2, wherein Further comprising:

5. The semiconductor device according to claim 3 or 4, wherein an organic protective layer disposed on the passivation layer and extending from the peripheral region toward the active region to cover the metal electrode layer and expose at least part of the upper surface of the metal electrode layer, and the organic protective layer exposes the plurality of through holes. Further comprising:

6. The semiconductor device according to claim 3 or 4, wherein an organic protective layer disposed on the passivation layer and extending from the peripheral region toward the active region to cover the metal electrode layer and expose at least part of the upper surface of the metal electrode layer, and the organic protective layer fills the plurality of through holes and the groove. The passivation layer also fills the plurality of through holes and the groove.

7. The semiconductor device of claim 2, wherein Further comprising:

8. The semiconductor device of claim 7, wherein, an organic protective layer disposed on the passivation layer and extending from the peripheral region toward the active region to cover the metal electrode layer and expose at least part of the upper surface of the metal electrode layer, and the organic protective layer exposes the part of the passivation layer filling the plurality of through holes. Further comprising:

9. The semiconductor device of claim 7, wherein, an organic protective layer disposed on the passivation layer and extending from the peripheral region toward the active region to cover the metal electrode layer and expose at least part of the upper surface of the metal electrode layer, and the organic protective layer covers the part of the passivation layer filling the plurality of through holes. The through holes are circular holes with a radius greater than or equal to 2 microns or square holes with a side length greater than or equal to 4 microns, and the spacing of adjacent two through holes in the circumference of the metal electrode layer is greater than or equal to 5 microns.

10. The semiconductor device of claim 2, wherein ​

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