Display device

Abstract

The utility model relates to a pixel and a display device. A pixel according to an embodiment of the present disclosure includes: a light emitting element; a pulse width control circuit electrically connected to a data line to which a data voltage is applied, generating an emission control signal having a pulse width according to the data voltage, and outputting the emission control signal; and a pixel driving circuit receiving the emission control signal and providing a driving current to the light emitting element in a period according to a pulse width of the emission control signal. According to an embodiment of the present disclosure, a pixel that displays images of various gray levels by controlling a period of light emission of a light emitting element, a method for driving the pixel, and a display device including the pixel may be provided.

Description

[0001] This application is a divisional application of Utility Model Patent Application No. 202420135244.X, filed on January 19, 2024, entitled “Pixel and Display Device Including the Same”.

[0002] Cross Reference to Related Applications

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0008605, filed in the Korean Intellectual Property Office (KIPO) on January 20, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0004] Embodiments of the present disclosure relate to a pixel, a method of driving the pixel, and a display device including the pixel. BACKGROUND

[0005] With the development of information technology, the importance of a display device, which is a medium for connecting users and information, has been emphasized. In response to this, the use of non-light emitting type display devices such as liquid crystal display devices and light emitting type display devices such as organic light emitting display devices has been increased.

[0006] The light emitting type display device can include a plurality of pixels including one or more light emitting elements. The light emitting type display device can display images of various gray scales by changing the size of a driving current flowing through the light emitting elements.

[0007] However, in the case of using the display device for a long time, the gray scale of an image displayed by the pixel can change due to a change in the characteristics of a transistor that provides a driving current to the light emitting element. This can be manifested as a phenomenon of distortion of a color coordinate preset in the display device.

[0008] Therefore, there is a demand for a pixel and a display device that display images of various gray scales without changing the size of a driving current provided to the light emitting element. SUMMARY

[0009] The present disclosure provides a pixel that displays images of various gray scales by controlling the length of a period in which a light emitting element emits light, a method of driving the pixel, and a display device including the pixel.

[0010] The pixel according to an embodiment of the present disclosure can include a light emitting element, a pulse width control circuit electrically connected to a data line to which a data voltage is applied, generating an emission control signal having a pulse width according to the data voltage, and outputting the emission control signal, and a pixel driving circuit receiving the emission control signal and providing a driving current to the light emitting element for a period according to the pulse width of the emission control signal.

[0011] The pulse width control circuit can include a first capacitor including a first electrode to which a data voltage is applied and a second electrode to which a triangular wave is applied.

[0012] The pulse width control circuit can further include a first switching element that switches electrical connection between the first electrode of the first capacitor and a data line.

[0013] The pulse width control circuit can further include a second switching element including a gate electrode, a source electrode, and a drain electrode, the gate electrode being electrically connected to the first electrode of the first capacitor. The gate electrode of the second switching element can be electrically connected to the first electrode of the first capacitor and the first switching element at a first node. One of the source electrode and the drain electrode of the second switching element can be electrically connected to a first power line to which a first power voltage is applied. The other of the source electrode and the drain electrode of the second switching element can be electrically connected to a second power line to which a second power voltage is applied.

[0014] The pulse width control circuit can further include a third switching element that switches electrical connection between the first power line and the second switching element.

[0015] The second switching element and the third switching element can be electrically connected at a second node. The emission control signal can be output through the second node.

[0016] The pulse width control circuit can further include a second capacitor including an electrode electrically connected to the second node.

[0017] The emission control signal can have a high voltage level or a low voltage level. One of the high voltage level and the low voltage level can be a voltage of the first power line. The other of the high voltage level and the low voltage level can be a voltage of the second power line.

[0018] The light emitting element can be electrically connected to a third power line. The pixel driving circuit can include a first emission control switching element including a gate electrode to which the emission control signal is input, and switching electrical connection between the first power line and a fourth node, a fourth switching element including a gate electrode, a source electrode, and a drain electrode electrically connected to the third node, and a fifth switching element switching electrical connection between the fourth node and a fourth power line. One of the source electrode and the drain electrode of the fourth switching element can be electrically connected to the fourth node, and the other of the source electrode and the drain electrode of the fourth switching element can be electrically connected to a fifth node.

[0019] The pixel driving circuit can further include a second emission control switching element switching electrical connection between the fifth node and the light emitting element.

[0020] The pixel driving circuit can further include a storage capacitor including one electrode electrically connected to the third node and another electrode electrically connected to the first power supply line.

[0021] The pixel driving circuit can further include a first initialization switching element that switches electrical connection between the third node and a second power supply line to which a second power supply voltage is applied. The gate electrode of the first emission control switching element can be electrically connected to the second power supply line through the pulse width control circuit.

[0022] The driving current flowing through the light emitting element can flow from the first power supply line to which the first power supply voltage is applied to the light emitting element via the pixel driving circuit. The high level voltage of the emission control signal can be a voltage applied to the pixel driving circuit from the first power supply line via the pulse width control circuit.

[0023] A display apparatus according to an embodiment of the disclosure can include a display panel on which a plurality of pixels including a light emitting element and a plurality of data lines electrically connected to the plurality of pixels are disposed, and a data driving circuit that provides a data voltage to the plurality of data lines. Each of the plurality of pixels can emit light for a period according to the data voltage.

[0024] The display apparatus can further include a timing controller that outputs input image data to the data driving circuit. The input image data can include gradation level information for each of the plurality of pixels, and the data driving circuit can output the data voltage having a voltage level corresponding to the gradation level information. Each of the plurality of pixels can emit light for a period according to the gradation level information included in the input image data.

[0025] A plurality of first scan lines can be disposed on the display panel, and each of the plurality of first scan lines can be electrically connected to pixels of the plurality of pixels located in the same pixel row. The pixels of the plurality of pixels located in the same pixel row can have different times to start emitting light or different times to end emitting light according to the data voltage.

[0026] The display apparatus can further include a triangular wave output circuit that outputs a first voltage or a triangular wave linearly increasing from the first voltage. At least one sweep line to which the triangular wave is applied can be disposed on the display panel, and the at least one sweep line can be electrically connected to the plurality of pixels. A period in which the data voltage is input to the plurality of pixels electrically connected to the at least one sweep line can overlap with a period in which the triangular wave output circuit outputs the first voltage. A period in which the plurality of pixels electrically connected to the at least one sweep line emit light can overlap with a period in which the triangular wave output circuit outputs the triangular wave.

[0027] According to an embodiment of the disclosure, a method for driving a pixel including a light emitting element can include inputting a data voltage to the pixel, generating an emission control signal having a pulse width corresponding to the data voltage in the pixel, and emitting light from the light emitting element for a period corresponding to the pulse width of the emission control signal.

[0028] The method for driving a pixel can further include inputting a triangular wave to the pixel through a sweep line electrically connected to the pixel. Emitting light from the light emitting element can be performed during the inputting of the triangular wave to the pixel.

[0029] The method for driving a pixel can further include inputting a first voltage to the sweep line. Inputting the data voltage can be performed during the inputting of the first voltage. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0031] Figure 1 is a schematic system block diagram of a display apparatus according to an embodiment of the disclosure.

[0032] Figure 2A is a schematic diagram illustrating a driving circuit of a pixel in a display apparatus displaying an image in a sequential emission method.

[0033] Figure 2B is a schematic diagram illustrating a driving circuit of a pixel in a display apparatus displaying an image in a non-sequential emission method.

[0034] Figure 3 is a schematic system block diagram of a pixel according to an embodiment of the disclosure.

[0035] Figure 4 is a schematic diagram illustrating an equivalent of a pulse width control circuit according to an embodiment of the disclosure.

[0036] Figure 5 is a schematic diagram illustrating a second emission control signal generated by a pulse width control circuit according to an embodiment of the disclosure.

[0037] Figure 6 is a schematic diagram illustrating an embodiment in which a length of a non-emission period is adjusted according to a level of a data voltage.

[0038] Figure 7 is a schematic diagram illustrating a relationship between a pulse width of a second emission control signal and a length of an emission period according to an embodiment of the disclosure.

[0039] Figure 8is a schematic diagram showing an equivalent of a pixel driving circuit according to an embodiment of the present disclosure.

[0040] Figure 9 is a schematic diagram showing a signal input to a pixel driving circuit and a voltage of a sweep line according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable terms that are non-limiting examples of the apparatus or methods disclosed herein. However, it will be readily apparent to one of ordinary skill in the art that the various embodiments can be practiced without these specific details, or with one or more equivalent arrangements. Herein, various embodiments are not necessarily mutually exclusive, or mutually consistent, or mutually exclusive and consistent with each other. For example, a particular shape, configuration, and characteristic of an embodiment can be used or implemented in another embodiment.

[0042] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art can easily practice the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0043] In order to clearly describe the present disclosure, portions unrelated to the description are omitted, and throughout the specification, the same or similar components are denoted by the same reference numerals. Accordingly, the above-described reference numerals can also be used in other drawings.

[0044] Unless otherwise specified, the described embodiments are to be understood as providing illustrative features of the present disclosure. Accordingly, features, components, modules, layers, films, panels, regions, and / or aspects of the various embodiments (hereinafter referred to as "elements"), both individually and / or collectively, can be combined with one another in other ways, separated, interchanged, and / or rearranged, unless otherwise specified herein, without departing from the present disclosure.

[0045] Various embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures of embodiments according to this disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions, unless otherwise specifically stated herein. In this manner, regions illustrated in the figures can be schematic in nature and can not reflect actual shapes of regions of devices, and as such are not intended to limit the scope of the present disclosure in any way.

[0046] Further, the dimensions and the thicknesses of each component shown in the drawings are arbitrarily shown for ease of description, and thus the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thicknesses can be exaggerated for clarity.

[0047] Further, in the specification, the expression "is the same" can mean "is substantially the same". That is, it can be sufficiently the same to convince one of ordinary skill in the art that it is the same. In other expressions, "substantially" can be omitted.

[0048] Although the terms "first", "second", etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0049] Spatially relative terms, such as "under", "above", "upper", "on", "higher", "side" (e.g., as in "sidewall") and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. In addition, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the terms "comprises", "comprising", "includes", "including" and / or "contains", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as synonyms for "about", and are used to designate a value that is close to, but not necessarily exactly, the stated value.

[0051] When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected, or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. In this regard, the term “connected” can refer to physical or electrical and / or fluid connection, with or without intervening elements.

[0052] Further, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to three axes of a rectangular coordinate system, such as an x-axis, a y-axis, and a z-axis, and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purpose of the present disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any one of X, Y, and Z alone, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. In the specification and claims, the term “and / or” is intended to include any combination of the term “and” and the term “or.” For example, “A and / or B” can be interpreted as meaning “A, B, or A and B.” The terms “and” and “or” can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to “and / or.”

[0053] The display surface can be parallel to a surface defined by the first direction DR1 and the second direction DR2. A normal direction of the display surface (i.e., a thickness direction of the display apparatus) can represent the third direction DR3. In the present specification, expressions “when viewed from a plane” or “in a plan view” can represent a case when viewed in the third direction DR3. Hereinafter, a front surface (or a top surface) and a rear surface (or a bottom surface) of each of layers or units can be distinguished by the third direction DR3. However, the directions represented by the first direction DR1, the second direction DR2, and the third direction DR3 can be relative concepts and are converted with respect to each other, for example, to opposite directions.

[0054] Unless otherwise defined or implied herein, all terms used are to be given their ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. It will also be appreciated that terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly so defined in the specification.

[0055] Figure 1 is a schematic system block diagram of a display apparatus 100 according to an embodiment of the disclosure.

[0056] The display apparatus 100 according to an embodiment of the disclosure can include a display panel 110, a data driving circuit 120, a gate driving circuit 130, a triangular wave output circuit 140, a timing controller 150, a power management circuit 160, etc.

[0057] A plurality of pixels PXL can be disposed on the display panel 110. Each of the pixels PXL can include one or more light emitting elements. In a case where each of the pixels PXL includes one or more light emitting elements, the display apparatus 100 can be implemented as a light emitting type display apparatus.

[0058] In a case where the display apparatus 100 is implemented as a light emitting type display apparatus, the display apparatus 100 can be implemented as an inorganic light emitting display apparatus. The display apparatus 100 can be a curved display apparatus, a flexible display apparatus, a foldable display apparatus, a rollable display apparatus, a stretchable display apparatus, a transparent display apparatus, a mirror display apparatus, etc. The display apparatus 100 can be implemented as, for example, a display apparatus including inorganic light emitting elements having a nano-scale size to a micro-scale size. The display apparatus 100 can be implemented as an organic light emitting display apparatus including organic light emitting elements. The display apparatus 100 according to an embodiment of the disclosure is not limited thereto.

[0059] A plurality of data lines DL1 to DLm (where m can be a natural number greater than or equal to 2), gate lines GL1 to GLn (where n can be a natural number greater than or equal to 2), and sweep lines SWL1 to SWLn (where n can be a natural number greater than or equal to 2) electrically connected to the pixels PXL can be disposed on the display panel 110. A plurality of power supply lines can be disposed on the display panel 110 to deliver a power supply voltage to be applied to the pixels PXL. One of a first power supply voltage ELVDD, a second power supply voltage VINIT, a third power supply voltage ELVSS, a fourth power supply voltage DATA_PAM, and a fifth power supply voltage VAINIT can be applied to one of the power supply lines disposed on the display panel 110.

[0060] The data lines DL1 to DLm can be disposed on the display panel 110 to extend in a first direction DR1. For example, the first direction DR1 can be a direction connecting an upper side and a lower side of the display panel 110. The first direction DR1 can be, for example, a column direction.

[0061] The gate lines GL1 to GLn can be disposed on the display panel 110 to extend in a second direction DR2. The second direction DR2 and the first direction DR1 can be different. For example, the second direction DR2 can intersect the first direction DR1. The second direction DR2 can be, for example, a direction connecting the left side and the right side of the display panel 110. The second direction DR2 can be, for example, a row direction. However, the directions indicated by the first direction DR1 and the second direction DR2 are not limited to the above descriptions.

[0062] Referring to Figure 1 The sweep lines SWL1 to SWLn can be disposed on the display panel 110 to extend in a second direction DR2. However, as will be described below with reference to Figure 2B The sweep lines SWL1 to SWLn can extend in a direction (e.g., the first direction DR1) different from the second direction DR2 in a case where the display apparatus 100 according to an embodiment of the disclosure operates in a non-sequential driving method.

[0063] The power supply lines can be disposed on the display panel 110 to extend in the first direction DR1.

[0064] The data driving circuit 120 can output data voltages to the data lines DL1 to DLm. The data driving circuit 120 can generate data voltages for displaying an image and output the generated data voltages to the data lines DL1 to DLm. The data driving circuit 120 can receive input image data DATA and a data driving circuit control signal DCS from the timing controller 150 to generate data voltages, and output the generated data voltages to the data lines DL1 to DLm according to timing.

[0065] The data driving circuit control signal DCS can include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, etc.

[0066] The gate driving circuit 130 can output gate driving signals to the gate lines GL1 to GLn. The gate driving circuit 130 can output gate voltages of an on level or an off level to the gate lines GL1 to GLn. The gate driving signals can include an on level gate voltage and an off level gate voltage. The operation timing of the switching elements in the pixels PXL can be controlled by the gate driving signals. The gate driving circuit 130 can receive a gate driving circuit control signal GCS from the timing controller 150 and output the gate driving signals (or the gate voltages of the on level or the on level gate voltages) to the gate lines GL1 to GLn according to timing. The gate driving circuit 130 can sequentially output the gate driving signals to the gate lines GL1 to GLn, but the disclosure is not limited thereto.

[0067] The triangular wave output circuit 140 can drive the sweep lines SWL1 to SWLn. The triangular wave output circuit 140 can output a triangular wave to the sweep lines SWL1 to SWLn. The triangular wave can include a signal whose voltage level linearly varies with time. In the disclosure, the triangular wave can also be referred to as a sweep signal. The triangular wave output circuit 140 can generate a triangular wave, and the triangular wave output circuit 140 can output the generated triangular wave to the sweep lines SWL1 to SWLn. The triangular wave output circuit 140 can sequentially output the generated triangular wave to the sweep lines SWL1 to SWLn, but the disclosure is not limited thereto. The triangular wave output circuit 140 can receive a triangular wave output circuit control signal SCS from the timing controller 150 to generate a triangular wave, and output the generated triangular wave to the sweep lines SWL1 to SWLn.

[0068] The timing controller 150 can control the data driving circuit 120, the gate driving circuit 130, and the triangular wave output circuit 140. The timing controller 150 can receive image data from the outside (e.g., a host system, etc.), and convert the image data according to an interface (or a preset interface). The timing controller 150 can transmit the input image data DATA converted according to the interface to the data driving circuit 120. The interface can include, for example, a low voltage differential signal (LVDS), a serial peripheral interface (SPI), an inter-integrated circuit (I2C), or an embedded display port (eDP).

[0069] The timing controller 150 can generate the input image data DATA in consideration of the arrangement of the pixels PXL provided on the display panel 110. For example, the timing controller 150 can receive RGB-type image data, convert the RGB-type image data into RGBG-type input image data DATA, and transmit the converted input image data DATA (e.g., the converted RGBG-type input image data DATA) to the data driving circuit 120.

[0070] The power management circuit 160 can generate a plurality of power supply voltages to be supplied to the display panel 110, and output the generated power supply voltages. The power supply voltage can be a voltage commonly input to the pixels PXL.

[0071] The data driving circuit 120, the gate driving circuit 130, the triangular wave output circuit 140, and the timing controller 150 can be classified according to functions performed by each component within the display apparatus 100, and two or more of the components can be formed as a single integrated circuit. For example, the data driving circuit 120 and the timing controller 150 can be integrally formed as a single integrated circuit and disposed in the display apparatus 100. The gate driving circuit 130 and the triangular wave output circuit 140 can be integrally formed as a single integrated circuit and disposed in the display apparatus 100.

[0072] The timing controller 150 can be formed as an integrated circuit and disposed in the display apparatus 100. The timing controller 150 can be implemented as a processor, a logic circuit, etc., and disposed in the display apparatus 100. The timing controller 150 can include one or more registers.

[0073] Figure 2A FIG. 1B is a schematic diagram illustrating a driving circuit of a pixel PXLij in the display apparatus 100 that displays an image in a sequential emission method. Figure 2B FIG. 1C is a schematic diagram illustrating a driving circuit of a pixel PXLij in the display apparatus 100 that displays an image in a non-sequential emission method.

[0074] Referring to Figure 2A and Figure 2B , the pixel PXLij (hereinafter, referred to as the pixel PXLij) can be located in an i-th row (1 ≤ i ≤ n, where n can be a natural number greater than or equal to 2) and a j-th column (1 ≤ j ≤ m, where m can be a natural number greater than or equal to 2) in the display panel 110.

[0075] Referring to Figure 2A , the pixel PXLij of the display apparatus 100 that displays an image in a sequential driving method (or a sequential emission method) is illustrated. For example, the gate driving circuit 130 can sequentially output gate driving signals from a first gate line GL1 (for example, see Figure 1 ) to an n-th gate line GLn (for example, see Figure 1 ). For example, the triangular wave output circuit 140 can sequentially output triangular waves from a first sweep line SWL1 (for example, see Figure 1 ) to an n-th sweep line SWLn (for example, see Figure 1 ).

[0076] The i-th gate line GLi (for example, see Figure 1 ) can be electrically connected to the pixel PXLij. The i-th gate line GLi can include an i-th first scan line SCL1i, an i-th second scan line SCL2i, an i-th third scan line GWLi, an i-th fourth scan line GILi, an i-th fifth scan line GBLi, and an i-th first emission control line EMLi.

[0077] The i-th first scan line SCL1i can be a line to which a gate signal (or a gate voltage at an on level) is applied, so that a data voltage applied to the data line DLj is input to the pixel PXLij.

[0078] The i-th second scan line SCL2i, the i-th third scan line GWLi, the i-th fourth scan line GILi, the i-th fifth scan line GBLi, and the i-th first emission control line EMLi will be described below.

[0079] The ith sweep line SWLi can be electrically connected to the pixel PXLij.

[0080] The gate driving signal (e.g., a gate voltage at an on level or an on level gate voltage) and the triangular wave can be input at substantially the same timing to the pixels PXL in the same pixel row (e.g., the ith pixel row) (see, for example, Figure 1 ). The gate driving signal and the triangular wave can be input at different timings to the pixels PXL in different pixel rows (see, for example, Figure 1 ).

[0081] Referring to Figure 2B , a pixel PXLij of a display apparatus 100 displaying an image in a non-sequential driving method is illustrated. The non-sequential driving method can include a simultaneous emission method.

[0082] In the disclosure, the simultaneous emission method can refer to a method in which the pixels PXL in different pixel rows (see, for example, Figure 1 ) start emitting light at the same time, or a method in which the pixels PXL in different pixel rows (see, for example, Figure 1 ) end emitting light at the same time.

[0083] Referring to Figure 2B , an ith gate line GLi (see, for example, Figure 1 ) can be electrically connected to the pixel PXLij. The ith gate line GLi can include an ith first scan line SCL1i, an ith second scan line SCL2, an ith third scan line GWL, an ith fourth scan line GIL, an ith fifth scan line GBL, an ith first emission control line EML, and the like.

[0084] At least one of the ith second scan line SCL2, the ith third scan line GWL, the ith fourth scan line GIL, the ith fifth scan line GBL, and the ith first emission control line EML can be a common line commonly connected to two or more pixel rows. The ith second scan line SCL2 can be a common second scan line SCL2. The ith third scan line GWL can be a common third scan line GWL. The ith fourth scan line GIL can be a common fourth scan line GIL. The ith fifth scan line GBL can be a common fifth scan line GBL. The ith first emission control line EML can be a common first emission control line EML.

[0085] The ith sweep line SWLi can be electrically connected to the pixel PXLij. The ith sweep line SWLi can be commonly connected to two or more pixel rows. The ith sweep line SWLi can be a common sweep line SWL.

[0086] Referring to Figure 2AAccording to an embodiment of the disclosure, the display apparatus 100 can display an image in a sequential driving method. According to the sequential driving method, a period of a display image of each pixel row can be controlled. According to the sequential driving method, a period in which the pixel PXLij emits light within one frame period can be increased.

[0087] Referring to Figure 2B According to an embodiment of the disclosure, the display apparatus 100 can display an image in a non-sequential driving method. According to the non-sequential driving method, the pixels PXL located in different pixel rows (see, for example, Figure 1 ) can start emitting light at the same time, or can end emitting light at the same time. According to the non-sequential driving method, the gate driving circuit 130 can be simple.

[0088] Hereinafter, the i-th first scan line SCL1i can be referred to as a first scan line SCL1, the i-th second scan line SCL2i or SCL2 can be referred to as a second scan line SCL2, the i-th third scan line GWLi or GWL can be referred to as a third scan line GWL, the i-th fourth scan line GILi or GIL can be referred to as a fourth scan line GIL, the i-th fifth scan line GBLi or GBL can be referred to as a fifth scan line GBL, the i-th first emission control line EMLi or EML can be referred to as a first emission control line EML, the i-th sweep line SWLi or SWL can be referred to as a sweep line SWL, and the j-th data line DLj can be referred to as a data line DL.

[0089] According to an embodiment of the disclosure, the display apparatus 100 can display an image in at least one of a sequential driving method and a non-sequential driving method.

[0090] Figure 3 is a schematic system block diagram of the pixel PXL according to an embodiment of the disclosure.

[0091] Referring to Figure 3 The pixel PXL according to an embodiment of the disclosure can include a pulse width control circuit PWMC, a pixel driving circuit PDC, and a light emitting element LE.

[0092] The pulse width control circuit PWMC can generate and output a second emission control signal EM2. The pulse width control circuit PWMC can be electrically connected to the data line DL and control a pulse width (or a duty ratio) of the second emission control signal EM2 based on an input data voltage.

[0093] The pulse width control circuit PWMC can be electrically connected to the sweep line SWL, the data line DL, the first scan line SCL1, and the second scan line SCL2. The pulse width of the second emission control signal EM2 can be controlled in the pulse width control circuit PWMC by a signal provided to a line (e.g., the sweep line SWL, the data line DL, the first scan line SCL1, the second scan line SCL2, etc.).

[0094] The pulse width control circuit PWMC can be electrically connected to a power line to which a high-level voltage is applied and a power line to which a low-level voltage is applied. For example, the pulse width control circuit PWMC can be electrically connected to a first power line PL1 to which a first power voltage ELVDD is applied. The high-level voltage of the second emission control signal EM2 can be equal to or substantially equal to the first power voltage ELVDD. For example, the pulse width control circuit PWMC can be electrically connected to a second power line PL2 to which a second power voltage VINIT is applied. The low-level voltage of the second emission control signal EM2 can be equal to or substantially equal to the second power voltage VINIT.

[0095] The pixel driving circuit PDC can be electrically connected to the first power line PL1. The pixel driving circuit PDC can receive the first power voltage ELVDD and provide a driving current to the light emitting element LE. The pixel driving circuit PDC can receive the second emission control signal EM2 and control a period in which the driving current is provided to the light emitting element LE according to the pulse width of the input second emission control signal EM2.

[0096] The light emitting element LE can include one electrode electrically connected to the pixel driving circuit PDC and another electrode electrically connected to a third power line PL3. A third power voltage ELVSS can be applied to the third power line PL3. The third power voltage ELVSS can be, for example, a ground voltage. The light emitting element LE can emit light if a driving current flows and can not emit light if the driving current does not flow.

[0097] In the pixel PXL according to the embodiment of the disclosure, the gray scale level of the corresponding pixel PXL can be adjusted according to the period in which the light emitting element LE emits light within one frame period.

[0098] For example, in the case where the period in which the light emitting element LE emits light within one frame period is long, the corresponding pixel PXL can display a high gray scale level image. For example, in the case where the period in which the light emitting element LE emits light within one frame period is short, the corresponding pixel PXL can display a low gray scale level image.

[0099] In the pixel PXL according to the embodiment of the disclosure, the magnitude of the driving current flowing through the light emitting element LE can be constant regardless of the gray scale level displayed by the corresponding pixel PXL.

[0100] Figure 4 is a schematic view showing an equivalent of the pulse width control circuit PWMC according to an embodiment of the present disclosure.

[0101] The pulse width control circuit PWMC can include one or more switching elements and one or more capacitors.

[0102] The switching element can include a transistor. The transistor can be implemented as a p-type thin film transistor including a p-type semiconductor or an n-type thin film transistor including an n-type semiconductor. In the p-type thin film transistor, the on-level voltage can be a low-level voltage, and the off-level voltage can be a high-level voltage. In the n-type thin film transistor, the on-level voltage can be a high-level voltage, and the off-level voltage can be a low-level voltage. The transistor can include a polycrystalline silicon semiconductor. In another embodiment, the transistor can include a single-crystal silicon semiconductor, an oxide semiconductor, an amorphous silicon semiconductor, or the like.

[0103] Hereinafter, an embodiment in which the one or more switching elements included in the pulse width control circuit PWMC are implemented as a p-type thin film transistor or an n-type thin film transistor will be described. However, the present disclosure is not limited thereto.

[0104] Referring to Figure 4 , the pulse width control circuit PWMC according to an embodiment of the present disclosure can include a first transistor TR1, a second transistor TR2, a third transistor TR3, a first capacitor Csw, and a second capacitor Chold.

[0105] The first transistor TR1 can switch an electrical connection between the data line DL and a first node N1. A gate electrode of the first transistor TR1 can be electrically connected to a first scan line SCL1. An operation timing of the first transistor TR1 can be controlled by a first scan signal SCAN1. Although the first transistor TR1 is illustrated as a p-type thin film transistor in Figure 4 , the present disclosure is not limited thereto, and the first transistor TR1 can be implemented as an n-type thin film transistor.

[0106] The second transistor TR2 can switch an electrical connection between a second power line PL2 and a second node N2. A gate electrode of the second transistor TR2 can be electrically connected to the first node N1. An operation timing of the second transistor TR2 can be controlled according to a voltage of the first node N1. In a case where the second transistor TR2 is turned on, a second power voltage VINIT can be applied to the second node N2. Although the second transistor TR2 is illustrated as an n-type thin film transistor in Figure 4 , the present disclosure is not limited thereto, and the second transistor TR2 can be implemented as a p-type thin film transistor.

[0107] The third transistor TR3 can switch the electrical connection between the first power line PL1 and the second node N2. The gate electrode of the third transistor TR3 can be electrically connected to the second scan line SCL2. The operation timing of the third transistor TR3 can be controlled by the second scan signal SCAN2. In the case where the third transistor TR3 is turned on, the first power voltage ELVDD can be applied to the second node N2. Although the third transistor TR3 is illustrated as a p-type thin film transistor in Figure 4 the present disclosure is not limited thereto, and the third transistor TR3 can be implemented as an n-type thin film transistor.

[0108] The first capacitor Csw can include a first electrode E1 and a second electrode E2. The first electrode E1 of the first capacitor Csw can be electrically connected to the first node N1. The data voltage DATA_PWM can be input to the first electrode E1 of the first capacitor Csw. The second electrode E2 of the first capacitor Csw can be electrically connected to the sweep line SWL. The triangular wave SWEEP can be input to the second electrode E2 of the first capacitor Csw.

[0109] In the case where the triangular wave SWEEP is input to the second electrode E2, the first capacitor Csw can change the voltage of the first electrode E1. In the case where the triangular wave SWEEP is applied to the second electrode E2 in a state (or a floating state) where a constant voltage is not applied to the first electrode E1 of the first capacitor Csw, the voltage level of the first electrode E1 can change. The phenomenon that the voltage level of the first electrode E1 changes can be due to the coupling effect of the capacitor. The first capacitor Csw can also be referred to as a sweep capacitor.

[0110] The second capacitor Chold can include one electrode electrically connected to the second node N2 and the other electrode to which the first power voltage ELVDD is applied. The other electrode can be electrically connected to, for example, the first power line PL1. The second capacitor Chold can remove noise generated in the second node N2.

[0111] The pulse width control circuit PWMC can output the second emission control signal EM2 through the second node N2. The high-level voltage of the second emission control signal EM2 can be the first power voltage ELVDD. The low-level voltage of the second emission control signal EM2 can be the second power voltage VINIT.

[0112] Figure 5 FIG. 7 is a diagram illustrating the second emission control signal EM2 generated by the pulse width control circuit PWMC according to an embodiment of the present disclosure.

[0113] Referring to Figure 5 , a frame can include a first period PR1, a second period PR2, and a third period PR3.

[0114] The first period PR1 can be a period in which the second scan signal SCAN2 of the on level is input to the pixel PXL (see, for example, Figure 1 ). In the first period PR1, the first scan signal SCAN1 of the off level can be input to the pixel PXL. The first power voltage ELVDD can be applied to the second node N2.

[0115] The second period PR2 can be a period in which the first scan signal SCAN1 of the on level is input to the pixel PXL (see, for example, Figure 1 ). In the second period PR2, the second scan signal SCAN2 of the off level can be input to the pixel PXL. The data voltage Vdata[k] (corresponding to DATA_PWM) of the corresponding frame (for example, the kth frame, where k can be a natural number greater than or equal to 2) can be input to the first node N1. For example, in the second period PR2, the data voltage Vdata[k-1] written in the previous frame period (for example, the (k-1)th frame) can be erased, and the data voltage Vdata[k] of the corresponding frame can be written. Figure 4

[0116] The third period PR3 can be a period in which the triangular wave SWEEP is input. In an embodiment of the present disclosure, during the third period PR3, the voltage of the sweep line SWL can change (for example, increase) the voltage ΔV (for example, a predetermined or selectable voltage ΔV) from the first voltage V1 (for example, a predetermined or selectable voltage V1).

[0117] Referring to Figure 5 , only a section in which the voltage of the sweep line SWL is linearly increased in the third period PR3 is shown, but the present disclosure is not limited thereto. In another embodiment, the third period PR3 can include a section in which the voltage of the sweep line SWL is linearly decreased.

[0118] In the case where the voltage of the sweep line SWL is linearly increased or decreased, the voltage of the first node N1 can change identically (or similarly) to the voltage of the sweep line SWL. The voltage change at the first node N1 can be due to the coupling effect described above.

[0119] Referring to Figure 5 , the third period PR3 can include a section in which the voltage level of the second node N2 is at a high level and a section in which the voltage level of the second node N2 is at a low level. One of the section in which the voltage level of the second node N2 is at a high level and the section in which the voltage level of the second node N2 is at a low level can be an emission period LP, and the other can be a non-emission period NLP.

[0120] In the pixel driving circuit PDC (see, for example, Figure 3 ​In a case where the transistor that receives the second emission control signal EM2 of the pixel drive circuit PDC (for example, see

[0121] In a case where the transistor that receives the second emission control signal EM2 of the pixel drive circuit PDC (for example, see Figure 3 In a case where the transistor that receives the second emission control signal EM2 of the pixel drive circuit PDC (for example, see

[0122] In the following, an explanation will be made on the basis of a case where the section in which the voltage level of the second node N2 is at a high level is the non-emission period NLP and the section in which the voltage level of the second node N2 is at a low level is the emission period LP. However, the present disclosure is not limited to this.

[0123] The timing at which the voltage level of the first node N1 in the third period PR3 becomes higher than the threshold voltage Vth of the second transistor TR2 can vary depending on the level of the data voltage Vdata[k]. Therefore, the timing at which the second power supply voltage VINIT is applied to the second node N2 can vary.

[0124] As described above, the pulse width control circuit PWMC (for example, see Figure 4 ) can generate the second emission control signal EM2. The pulse width control circuit PWMC can adjust the pulse width of the second emission control signal EM2.

[0125] Figure 6 is a schematic diagram showing an embodiment in which the length of the non-emission period NLP1 or NLP2 is adjusted depending on the level of the data voltage Vdata1 or Vdata2. The data voltage Vdata1 and Vdata2 of two levels will be described.

[0126] In Case 1, in the second period PR2, a high-level data voltage Vdata1 can be input to the first node N1. The voltage of the first node N1 can increase in the third period PR3, and at one time point, the voltage of the first node N1 can become greater than the threshold voltage Vth of the second transistor TR2. The period from the start of the third period PR3 to the point at which the voltage of the first node N1 reaches the threshold voltage Vth of the second transistor TR2 can be referred to as the first non-emission period NLP1.

[0127] In case 2, in the second period PR2, the low-level data voltage Vdata2 can be input to the first node N1. The voltage of the first node N1 can increase in the third period PR3, and at one point, the voltage of the first node N1 can become greater than the threshold voltage Vth of the second transistor TR2. The period from the start of the third period PR3 to the point at which the voltage of the first node N1 reaches the threshold voltage Vth of the second transistor TR2 can be referred to as a second non-emission period NLP2.

[0128] Referring to Figure 6 , the first non-emission period NLP1 can be shorter than the second non-emission period NLP2. For example, in case 1, because the emission period is longer, an image of a higher gray scale can be displayed. In case 2, because the emission period is shorter, an image of a lower gray scale can be displayed.

[0129] According to embodiments of the present disclosure, images of different gray scales can be displayed according to the level of the data voltage.

[0130] Figure 7 is a diagram illustrating a relationship between the pulse width of the second emission control signal EM2 and the length of the emission period LP1 or LP2 according to an embodiment of the present disclosure.

[0131] In case 1, the length of the non-emission period NLP1 can be relatively short, and the length of the emission period LP1 can be relatively long. Thus, in case 1, an image of a higher gray scale can be displayed.

[0132] In case 2, the length of the non-emission period NLP2 can be relatively long, and the length of the emission period LP2 can be relatively short. Thus, in case 2, an image of a lower gray scale can be displayed.

[0133] Referring to Figure 7 , the first period PR1 and the second period PR2 can be periods in which the first emission control signal EM1 has an off-level voltage (e.g., a high-level gate voltage VGH), and the third period PR3 can be a period in which the first emission control signal EM1 has an on-level voltage (e.g., a low-level gate voltage VGL). The first emission control signal EM1 can be a signal input to a pixel driving circuit PDC (e.g., see Figure 3 ), which will be described in detail with reference to Figure 8 and Figure 9 .

[0134] The point in time at which the third period PR3 starts and the point in time TM1 at which the first emission control signal EM1 of the on level is input can be the same. However, a margin period (e.g., a predetermined or selectable margin period) can be provided between the two points in time (e.g., the point in time at which the third period PR3 starts and the point in time TM1). The point in time at which the third period PR3 ends and the point in time TM2 at which the first emission control signal EM1 of the off level is input can be the same. However, a margin period (e.g., a predetermined or selectable margin period) can be provided between the two points in time (e.g., the point in time at which the third period PR3 ends and the point in time TM2).

[0135] Figure 8 is a schematic diagram illustrating an equivalent of the pixel drive circuit PDC according to an embodiment of the present disclosure.

[0136] The pixel drive circuit PDC according to an embodiment of the present disclosure can be electrically connected to the light emitting element LE. The pixel drive circuit PDC can include a transistor electrically connected to the second node N2. The pixel drive circuit PDC can include one or more capacitors.

[0137] Figure 8 It is shown that the pixel drive circuit PDC includes the fourth transistor TR4 to the tenth transistor TR10 and the storage capacitor Cstg. However, the present disclosure is not limited thereto.

[0138] The light emitting element LE can include a first electrode electrically connected to the sixth node N6 and a second electrode electrically connected to the third power supply line PL3 to which the third power supply voltage ELVSS is applied. The first electrode of the light emitting element LE can be one of an anode electrode and a cathode electrode, and the second electrode can be the other of the anode electrode and the cathode electrode.

[0139] In an embodiment of the present disclosure, the length of the period in which the drive current flows through the light emitting element LE can be adjusted. The magnitude of the drive current flowing through the light emitting element LE can be constant regardless of the gray scale of the image displayed by the corresponding pixel PXL (e.g., see Figure 1 ).

[0140] The light emitting element LE can be an organic light emitting element including an organic light emitting layer. In another embodiment, the light emitting element LE can be an inorganic light emitting element including an inorganic material. In another embodiment, the light emitting element LE can be a light emitting element composed of a combination of an inorganic material and an organic material. In another embodiment, the light emitting element LE can have a form in which a plurality of inorganic light emitting elements are connected in parallel and / or in series between the third power supply line PL3 and the sixth node N6.

[0141] The fourth transistor TR4 can switch the electrical connection between the fourth node N4 and the fifth node N5. The gate electrode of the fourth transistor TR4 can be electrically connected to the third node N3. One of the source electrode and the drain electrode of the fourth transistor TR4 can be electrically connected to the fourth node N4. The other of the source electrode and the drain electrode of the fourth transistor TR4 can be electrically connected to the fifth node N5. The fourth transistor TR4 can function as a driver transistor that supplies a drive current to the light emitting element LE.

[0142] The fifth transistor TR5 can switch the electrical connection between the fourth power supply line PL4 and the fourth node N4. The gate electrode of the fifth transistor TR5 can be electrically connected to the third scan line GWL. The operation timing of the fifth transistor TR5 can be controlled by the third scan signal GW.

[0143] The fourth power supply voltage DATA_PAM can be applied to the fourth power supply line PL4. The fourth power supply voltage DATA_PAM and the data voltage DATA_PWM or Vdata (see, for example, FIG. 6) described above can differ in that the fourth power supply voltage DATA_PAM can be commonly input to a plurality of pixels PXL. Figure 4

[0144] The sixth transistor TR6 can switch the electrical connection between the third node N3 and the fifth node N5. The gate electrode of the sixth transistor TR6 can be electrically connected to the third scan line GWL. The operation timing of the sixth transistor TR6 can be controlled by the third scan signal GW. During the period in which the sixth transistor TR6 is turned on, the fourth transistor TR4 can be connected in a diode form.

[0145] The seventh transistor TR7 can switch the electrical connection between the second power supply line PL2 and the third node N3. The gate electrode of the seventh transistor TR7 can be electrically connected to the fourth scan line GIL. The operation timing of the seventh transistor TR7 can be controlled by the fourth scan signal GI. During the period in which the seventh transistor TR7 is turned on, the voltage of the third node N3 can be initialized with the second power supply voltage VINIT.

[0146] The eighth transistor TR8 can switch the electrical connection between the first power supply line PL1 and the fourth node N4. The gate electrode of the eighth transistor TR8 can be electrically connected to the second node N2. In the present disclosure, the eighth transistor TR8 can be referred to as a first emission control transistor.

[0147] Reference Figure 8 Although the eighth transistor TR8 is illustrated as a p-type transistor, the present disclosure is not limited thereto, and the eighth transistor TR8 can be implemented as an n-type transistor.

[0148] ​The ninth transistor TR9 can switch an electrical connection between the fifth node N5 and the sixth node N6. A gate electrode of the ninth transistor TR9 can be electrically connected to the first emission control line EML. The operation timing of the ninth transistor TR9 can be controlled by the first emission control signal EM1. During at least a part of a period in which the ninth transistor TR9 is turned on, the fourth transistor TR4 can be electrically connected to the light emitting element LE.

[0149] The tenth transistor TR10 can switch an electrical connection between the sixth node N6 and the fifth power line PL5. A gate electrode of the tenth transistor TR10 can be electrically connected to the fifth scan line GBL. The operation timing of the tenth transistor TR10 can be controlled by the fifth scan signal GB. During a period in which the tenth transistor TR10 is turned on, the voltage of the sixth node N6 can be initialized with the fifth power voltage VAINIT.

[0150] The storage capacitor Cstg can include one electrode electrically connected to the third node N3 and the other electrode electrically connected to the first power line PL1. The storage capacitor Cstg can apply a voltage corresponding to the fourth power voltage DATA_PAM to the third node N3 within one frame.

[0151] Figure 8 It is illustrated that only the fourth transistor TR4 is an n-type transistor and the fifth transistor TR5 to the tenth transistor TR10 are p-type transistors. However, the disclosure is not limited thereto. In another embodiment, the fourth transistor TR4 can be implemented as a p-type transistor, and one or more of the fifth transistor TR5 to the tenth transistor TR10 can be implemented as an n-type transistor.

[0152] Reference Figure 8 The emission control signal EM can include the first emission control signal EM1 and the second emission control signal EM2. In an embodiment of the disclosure, the drive current can be provided to the light emitting element LE during at least a part of a period in which both the first emission control signal EM1 and the second emission control signal EM2 are at an on level.

[0153] Figure 8 It is illustrated that the second emission control signal EM2 is input to the gate electrode of the eighth transistor TR8, and the first emission control signal EM1 is input to the gate electrode of the ninth transistor TR9.

[0154] However, the disclosure is not limited thereto, and the second emission control signal EM2 can be input to the gate electrode of the ninth transistor TR9, and the first emission control signal EM1 can be input to the gate electrode of the eighth transistor TR8.

[0155] Therefore, when the pulse width of the second emission control signal EM2 is controlled, the period in which the drive current is provided to the light emitting element LE can be controlled.

[0156] Figure 9 is a diagram showing voltages of a signal input to a pixel driving circuit PDC (see, for example, Figure 8 ) and a sweep line SWL according to an embodiment of the present disclosure.

[0157] Referring to Figure 9 , the frame period can further include a fourth period PR4, a fifth period PR5, and a sixth period PR6 between the first period PR1 and the third period PR3.

[0158] In the first period PR1, a second emission control signal EM2 of a high level voltage can be input. The high level voltage of the second emission control signal EM2 can be an off level voltage.

[0159] In the fourth period PR4, a fourth scan signal GI of an on level can be input. The second power voltage VINIT can be applied to the third node N3.

[0160] In the fifth period PR5, a third scan signal GW of an on level can be input. As described above with reference to Figure 8 , the fifth transistor TR5 and the sixth transistor TR6 can be turned on. A second voltage V2 corresponding to the fourth power voltage DATA_PAM (see, for example, Figure 8 ) can be input to the third node N3. The second voltage V2 can be an on level voltage.

[0161] In the sixth period PR6, a fifth scan signal GB of an on level can be input. As described above with reference to Figure 8 , the tenth transistor TR10 can be turned on, and the voltage of the sixth node N6 can be initialized with the fifth power voltage VAINIT.

[0162] The second period PR2 (see, for example, Figure 5 , Figure 6 and Figure 7 ) can overlap one of the fourth period PR4, the fifth period PR5, and the sixth period PR6. However, the present disclosure is not limited thereto, and the second period PR2 can not overlap the fourth period PR4, the fifth period PR5, and the sixth period PR6. The second period PR2 can exist between the first period PR1 and the fourth period PR4, between the fourth period PR4 and the fifth period PR5, between the fifth period PR5 and the sixth period PR6, or between the sixth period PR6 and the third period PR3.

[0163] In the third period PR3, a first emission control signal EM1 of an on level can be input. As described above with reference to Figure 8 , the ninth transistor TR9 can be turned on.

[0164] refer to Figure 9 The time point at which the voltage of the sweep line SWL begins to increase linearly and the time point at which the first transmit control signal EM1 at the turn-on level are input can be the same. However, a margin period (e.g., a predetermined or selectable margin period) can be provided between the two time points (e.g., the time point at which the voltage of the sweep line SWL begins to increase linearly and the time point at which the first transmit control signal EM1 at the turn-on level is input). Reference Figure 9 The timing of the voltage drop of the sweep line SWL and the timing of the input of the first transmit control signal EM1 at the cutoff level can be the same, but a margin period (e.g., a predetermined or selectable margin period) can be provided between the two timing points (e.g., the timing of the voltage drop of the sweep line SWL and the timing of the input of the first transmit control signal EM1 at the cutoff level).

[0165] During the third cycle PR3, a second transmit control signal EM2 with a conduction level can be input. (See above reference.) Figure 8 As described, when the second transmit control signal EM2, which is at the on-level input, is input, the eighth transistor TR8 can be turned on. When the second transmit control signal EM2, which is at the on-level input, is input, drive current can be provided to the light-emitting element LE (e.g., see...). Figure 8 ).

[0166] In summary, the content is as follows.

[0167] According to embodiments of this disclosure, the period of light emission by the light-emitting element LE can be controlled by controlling the pulse width of the second emission control signal EM2. Therefore, the corresponding pixel PXL can display images of various gray levels, from low to high gray levels.

[0168] According to embodiments of this disclosure, images of various grayscale levels can be displayed without controlling the magnitude of the drive current. Therefore, controlling the magnitude of the drive current within a fine range may be unnecessary. According to embodiments of this disclosure, a pixel PXL, a method for driving the pixel PXL, and a display device 100 including the pixel PXL can be provided, which can mitigate the phenomenon of color coordinate distortion caused by changes in the characteristics (e.g., threshold voltage, mobility, etc.) of transistors located in the path of the drive current flow (e.g., the drive transistor of the pixel drive circuit PDC).

[0169] According to embodiments of the present disclosure, a pixel PXL for displaying images of various grayscale levels by controlling the period of light emission of the light-emitting element LE, a method for driving the pixel PXL, and a display device 100 including the pixel PXL can be provided.

[0170] The above description is an example of technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the above-described embodiments of the present disclosure can be implemented alone or in combination with each other.

[0171] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure should be interpreted by the appended claims, and it should be understood that all technical spirits within the equivalent scope are included within the scope of the present disclosure.

Claims

1. A display device, characterized in that, The display device includes: A display panel having a plurality of pixels, including light-emitting elements, and a plurality of data lines electrically connected to the plurality of pixels; and The data driving circuit provides data voltage to the plurality of data lines. Each of the plurality of pixels emits light within a period according to the data voltage.

2. The display device according to claim 1, characterized in that, The display device further includes: The timing controller outputs input image data to the data driving circuit, wherein... The input image data includes grayscale information for each of the plurality of pixels. The data driving circuit outputs a data voltage having a voltage level corresponding to the grayscale information, and Each of the plurality of pixels emits light within a period based on the grayscale information included in the input image data.

3. The display device according to claim 2, characterized in that, The light-emitting elements of the pixels displaying high grayscale images in the plurality of pixels emit light over a long period of time, and The light-emitting elements of the pixels displaying low grayscale images in the plurality of pixels emit light within a short period of time.

4. The display device according to claim 1, characterized in that, Multiple first scan lines are arranged on the display panel, and Each of the plurality of first scan lines is electrically connected to a pixel located in the same pixel row among the plurality of pixels.

5. The display device according to claim 4, characterized in that, Based on the data voltage, the pixels located in the same pixel row among the plurality of pixels have different start-up times and the same end-of-emission times.

6. The display device according to claim 4, characterized in that, According to the data voltage, the pixels located in the same pixel row among the plurality of pixels have the same start time for emitting light and different end times for emitting light.

7. The display device according to claim 1, characterized in that, The display device further includes: A triangular wave output circuit outputs a first voltage or a triangular wave that changes linearly from the first voltage.

8. The display device according to claim 7, characterized in that, The triangular wave output circuit outputs a triangular wave that increases linearly from the first voltage.

9. The display device according to claim 7, characterized in that, The triangular wave output circuit outputs a triangular wave that decreases linearly from the first voltage.

10. The display device according to claim 7, characterized in that, At least one sweep line to which the triangular wave is applied is disposed on the display panel. The at least one sweep line is electrically connected to the plurality of pixels. The period of the data voltage input to the plurality of pixels electrically connected to the at least one sweep line overlaps with the period of the first voltage output by the triangular wave output circuit. The period of light emission from the plurality of pixels electrically connected to the at least one sweep line overlaps with the period of the triangular wave output by the triangular wave output circuit.

Images