Semiconductor assembly
By designing specific doped layer structures and controlling doping in silicon carbide semiconductor components, the short-channel effect and hot carrier problem in the miniaturization process were solved, achieving a stable critical voltage and reducing on-resistance, thereby improving the reliability and electrical characteristics of the components.
Patent Information
- Application Number
- CN202520137456.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-11-26
- Filing Date
- 2025-01-21
- Publication Date
- 2026-01-20
- Estimated Expiration
- 2035-01-21
AI Technical Summary
Existing planar silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) suffer from short-channel effects and hot carrier problems during miniaturization, leading to unstable critical voltage and increased on-resistance, which affects component reliability and electrical deviation.
In silicon carbide semiconductor devices, by forming a first lightly doped layer and a second lightly doped layer around the source, and precisely controlling the doping opening of the junction field-effect region between adjacent well regions, the contact between the junction field-effect region and the well region is avoided. Combined with process control, a second lightly doped layer with a width greater than the first doped layer is formed to suppress short-channel effects and reduce hot carrier problems.
It effectively suppresses short-channel effects and hot carrier problems, maintains the stability of the critical voltage, reduces on-resistance, ensures that the electrical characteristics of the component are not affected during the miniaturization process, and improves reliability.
Smart Images
Figure CN223816360U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a semiconductor assembly, in particular to a planar silicon carbide semiconductor assembly. BACKGROUND
[0002] Silicon carbide (SiC) has superior temperature resistance and voltage resistance, and is therefore widely used in electronic assemblies that must withstand high temperatures and high voltages.
[0003] In order to reduce the on-resistance (RDSon) of a planar silicon carbide metal-oxide-semiconductor field-effect transistor (SiC planar MOSFET) when it is started to reduce power loss when it is working, the cell pitch is generally reduced. However, in the process of miniaturization, in addition to the bottleneck of production process (such as alignment, metal filling capacity of source contact pad, etc.), the electrical properties of the semiconductor assembly will also deviate, which will affect the subsequent application.
[0004] For example, the cell is miniaturized to reduce power loss when working by reducing the channel length or reducing the width of the MOS junction field effect region (MOS J FET region). However, the shortening of the channel length will cause the threshold voltage (Vth) to be unstable due to short-channel effects and hot-carrier effects caused by high channel electric field, resulting in reliability problems of the assembly. Miniaturization of the MOS J FET region will increase the resistance (R FET ) of the junction field effect region (J JFET region), which will in turn increase the on-resistance (RDSon). Therefore, in order to avoid the problem of high R FET due to miniaturization of the MOS J JFET region, a higher concentration of implant ions (JF implant) is usually implanted in the J FET region to suppress the increase of R JFET . However, the J FET region and the adjacent well region will have some overlap, and the high concentration of JF implant will reduce the concentration of dopant ions in the well region, resulting in a decrease in the threshold voltage (Vth). If the threshold voltage (Vth) is too low, the assembly will be easily disturbed by noise. SUMMARY
[0005] The utility model discloses a semiconductor component can inhibit short channel effect and reduce hot carrier problem.
[0006] The semiconductor component includes a silicon carbide epitaxial substrate, two well regions, a junction field effect region, two sources, two lightly doped regions, two heavily doped regions, a gate, and a drain electrode.
[0007] The silicon carbide epitaxial substrate has a top surface and a bottom surface that are opposite to each other.
[0008] The well regions are formed downward from the top surface of the silicon carbide epitaxial substrate at intervals and have a second type of doping.
[0009] The junction field effect region is formed downward from the top surface of the silicon carbide epitaxial substrate, is located between adjacent well regions and does not contact the well regions, and has a first type of doping.
[0010] The sources respectively extend downward from the top surface of the silicon carbide epitaxial substrate and are located in the well regions.
[0011] The lightly doped regions are arranged corresponding to the sources. The lightly doped regions have a first lightly doped layer that is downward from the top surface of the silicon carbide epitaxial substrate and is located at a side of the corresponding source, and a second lightly doped layer that is located below the first lightly doped layer and extends from a lower half of the side of the corresponding source to a bottom of the source. The first lightly doped layer has the first type of doping, and the second lightly doped layer has the second type of doping and has a width corresponding to the side of the source that is greater than that of the first lightly doped layer.
[0012] The heavily doped regions are respectively located at the bottom of the sources and do not exceed the well regions, and have the second type of doping.
[0013] The gate is located on the top surface of the silicon carbide epitaxial substrate and between adjacent sources, and left and right sides of the gate extend to partially overlap the sources.
[0014] The drain electrode is located on the bottom surface of the silicon carbide epitaxial substrate.
[0015] Preferably, the semiconductor component has a doping concentration of the second lightly doped layer that is less than a doping concentration of the well regions, and a concentration of the heavily doped regions that is higher than the doping concentration of the well regions.
[0016] Preferably, the semiconductor component has the second lightly doped layer that extends to the bottom of the source and is located at a side of the corresponding heavily doped region.
[0017] Preferably, the semiconductor component further comprises an insulation unit, a conductive unit and an insulation protection unit, the insulation unit has a first insulation layer covering a top surface of the silicon carbide epitaxial substrate, and a second insulation layer, the gate electrode is located on a surface of the first insulation layer, and the second insulation layer covers the gate electrode and the first insulation layer, the conductive unit has an ohmic contact layer in contact with the source electrode and a conductive layer electrically connected with the ohmic contact layer, and the insulation protection unit is composed of an insulation material and covers the conductive layer and the second insulation layer.
[0018] Preferably, the semiconductor component further comprises an electrical connection unit having a plurality of conductive structures penetrating through the insulation protection unit and the second insulation layer and electrically connected with the conductive layer and the gate electrode respectively, and an electrical connection circuit for electrically connecting the conductive structures externally.
[0019] The semiconductor component has the advantages that the first lightly doped layer is formed around the source electrode, and the second lightly doped layer having a second type of doping and a width greater than that of the first lightly doped layer is located below the first lightly doped layer, so that the short channel effect and the hot carrier problem are suppressed. In addition, the junction field effect region between the two adjacent well regions is not in contact with the adjacent well regions by process control, so that the threshold voltage is maintained, and the problem of affecting the electrical characteristics of the component due to the increase of the doping concentration of the junction field effect region when the component is miniaturized is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 is a side view schematic diagram illustrating an embodiment of the semiconductor component. DETAILED DESCRIPTION
[0021] The semiconductor component will be described in detail below in combination with the drawings and embodiments.
[0022] Referring to Figure 1 , the embodiment of the semiconductor component comprises a silicon carbide epitaxial substrate 2, two well regions W, a junction field effect region J FET , two source electrodes S, two lightly doped regions 3, two heavily doped regions HW, a gate electrode G, an insulation unit 4, a conductive unit 5, an insulation protection unit 6, an electrical connection unit 7, and a drain electrode D.
[0023] The silicon carbide epitaxial substrate 2 is of a first type of doping, having a silicon carbide substrate 21 and a silicon carbide epitaxial film 22 on the silicon carbide substrate 21, including a top surface 23 and a bottom surface 24 opposite to each other. It is to be noted that the first type of doping refers to a first conductive type of doping, and the second type of doping refers to a second conductive type of doping opposite to the first conductive type of doping. For example, the first type of doping is N-type doping, and the second type of doping is P-type doping; or the first type of doping is P-type doping, and the second type of doping is N-type doping. The semiconductor component of the present application is a silicon carbide planar metal-oxide-semiconductor field-effect transistor (SiC planar MOS), and the doping ions of the N-type doping can be nitrogen (N) or phosphorus (P), and the doping ions of the P-type doping can be aluminum (Al). In the present embodiment, the first type of doping is N-type doping.
[0024] The well regions W are formed downward from the top surface 23 of the silicon carbide epitaxial substrate 2, located in the silicon carbide epitaxial film 22, and have the second type of doping (P-type doping).
[0025] The junction field effect region J FET is formed downward from the top surface 23 of the silicon carbide epitaxial substrate 2, located between the well regions W and not in contact with the well regions W, and has the first type of doping (N-type doping).
[0026] The source electrodes S are respectively extended downward from the top surface 23 of the silicon carbide epitaxial substrate 2 and located in the well regions W.
[0027] The lightly doped regions 3 are arranged corresponding to the source electrodes S and located in the well regions W, and each of the lightly doped regions 3 has a first lightly doped layer 31 downward from the top surface 23 of the silicon carbide epitaxial substrate 2 and located at a side edge of the corresponding source electrode S, and a second lightly doped layer 32 located below the first lightly doped layer 31 and extended from a lower half of the side edge of the corresponding source electrode S to a bottom of the source electrode S. That is, the depth of the source electrode S is between the first lightly doped layer 31 and the second lightly doped layer 32.
[0028] The first lightly doped layer 31 has the first type of doping (N-type doping), and the second lightly doped layer 32 has the second type of doping (P-type doping) and has a width corresponding to the side edge of the source electrode S greater than that of the first lightly doped layer 31. The edge of the first lightly doped layer 31 has a lateral distance from the corresponding well region W as a channel. The second lightly doped layer 32 is located below the first lightly doped layer 31 and has a lateral width greater than that of the first lightly doped layer 31 and is closer to the edge of the well region W. The doping concentration of the second lightly doped layer 32 is less than that of the well region W.
[0029] The heavily doped regions HW are located at the bottom of the source S and do not exceed the well region W, and the second lightly doped layer 32 extends to the bottom of the source S and is located at the side of the corresponding heavily doped region HW. The heavily doped regions HW have the same type of doping as the well region W, and the doping concentration of the heavily doped regions HW is greater than that of the well region W.
[0030] The gate G is located on the top surface 23 of the silicon carbide epitaxial substrate 2 and between adjacent source S, and the left and right sides of the gate G extend to overlap the orthographic projection part of the source S.
[0031] The insulating unit 4 has a first insulating layer 41 and a second insulating layer 42, the first insulating layer 41 is composed of oxide material, covering the top surface 23 of the silicon carbide epitaxial substrate 2, the gate G is located on the surface of the first insulating layer 41, and the second insulating layer 42 is composed of dielectric insulating material, covering the gate G and the first insulating layer 41.
[0032] The conductive unit 5 has a plurality of ohmic contact layers 51 in contact with the source S and a conductive layer 52 electrically connected with the ohmic contact layer 51.
[0033] The insulating protection unit 6 is composed of insulating material and covers the conductive layer 52 and the second insulating layer 42.
[0034] The electrical connection unit 7 has a conductive structure 71 and an electrical connection line 72, which passes through the insulating protection unit 6 and the second insulating layer 42, and is electrically connected with the source S and the gate G respectively. The electrical connection line 72 is electrically connected with the conductive structure 71 and located on the insulating protection unit 6, so as to externally electrically connect the source S and the gate G through three-dimensional wiring (only the conductive structure 71 and the electrical connection line 72 for connecting the source S are shown in the figure).
[0035] As mentioned above, the ohmic contact layer 51 can be a metal silicide layer, such as nickel silicide (Ni silicide), and the conductive layer 52 can be a metal or an alloy, such as titanium (Ti), titanium nitride (TiN) or aluminum copper alloy (AlCu). The insulating protection unit 6 can be a single layer or a multi-layer structure composed of insulating materials such as oxide or nitride, and the electrical connection line 72 can be a single layer or a multi-layer structure composed of the aforementioned metal or alloy.
[0036] The drain electrode D is located on the bottom surface 24 of the silicon carbide epitaxial substrate 2, which can include a metal silicide layer D11 formed on the bottom surface 24 and a metal conductive layer D12 formed on the surface of the metal silicide layer D11. The materials of the metal silicide layer D11 and the metal conductive layer D12 can be as mentioned above.
[0037] Since the miniaturization process shortens the channel length of semiconductor components, this invention utilizes process control to form the first lightly doped layer 31 on one side of the source S adjacent to the channel, and forms a second lightly doped layer 32 below the first lightly doped layer 31 extending toward the edge of the well region W, with a width greater than the first doped layer 31 and having type II doping. The first lightly doped layer 31 and the second lightly doped layer 32 can be used to suppress the short-channel effect and reduce the hot carrier problem.
[0038] Furthermore, during the miniaturization process of semiconductor devices, the distance between adjacent well regions W also decreases. Since photolithography is known to be difficult to precisely control openings with high aspect ratios, the traditional method used to form junction field-effect regions J during device miniaturization becomes less effective. FET The shielding opening is relatively large and overlaps with the lower well region W, resulting in a larger interface field-effect region J formed through the larger opening during doping. FET It will contact the adjacent well region W. However, as the component becomes smaller, the junction field-effect region J needs to be increased to reduce on-resistance. FET At a doping concentration of 10%, the J-type junction field-effect region will be affected. FET Contact with the adjacent well region W results in a highly doped junction field-effect region J. FET This will also affect the electrical properties of the well region W, causing a decrease in the critical voltage (Vth), which in turn leads to component failure.
[0039] Therefore, this invention precisely forms small-diameter doped openings between adjacent well regions W through parameter control of the photolithography etching process. Thus, the junction field-effect region J formed after ion implantation through these doped openings... FET It can also be precisely controlled between the well regions W and not to contact adjacent well regions W, thus increasing the junction field-effect region J. FET Doping concentration reduces on-resistance while maintaining the critical voltage (Vth) of the semiconductor device, allowing it to function properly.
[0040] In summary, the semiconductor device of this invention utilizes a first lightly doped layer 31 extending towards the channel direction on the side corresponding to the source S, and a second lightly doped layer 32 with a width greater than the first doped layer 31 and having type II doping formed below the first lightly doped layer 31. This allows for the suppression of hot carriers by the first doped layer 31 and the second lightly doped layer 32, thus avoiding the short-channel effect problem caused by device miniaturization. Furthermore, the junction field-effect region J located between two adjacent well regions W... FETThe junction field effect region J is not in contact with the adjacent well region W to maintain the critical voltage (Vth) and reduce the effect of the increased doping concentration of the junction field effect region J on the electrical characteristics of the component when the component is miniaturized FET The component can maintain normal operating characteristics when the component is miniaturized, thus achieving the purpose of the present application.
Claims
1. A semiconductor component, characterized in that, Include: Silicon carbide epitaxial substrate having a top surface and a bottom surface that are opposite to each other; Two well regions are formed alternately from the top surface of the silicon carbide epitaxial substrate downwards and have type II doping; The junction field-effect region is formed downward from the top surface of the silicon carbide epitaxial substrate, located between adjacent well regions and not in contact with the well regions, and has type I doping; Two source electrodes extend downward from the top surface of the silicon carbide epitaxial substrate and are located in the well region; Two lightly doped regions are provided corresponding to the source electrode. Each lightly doped region has a first lightly doped layer extending downward from the top surface of the silicon carbide epitaxial substrate and located on the side of the corresponding source electrode, and a second lightly doped layer located below the first lightly doped layer and extending from the lower half of the side of the corresponding source electrode to the bottom of the source electrode. The first lightly doped layer has type I doping, and the second lightly doped layer has type II doping and its width on the side of the corresponding source electrode is greater than that of the first lightly doped layer. Two heavily doped regions, respectively located at the bottom of the source and not exceeding the well region, have type II doping; A gate electrode is located on the top surface of the silicon carbide epitaxial substrate and between adjacent source electrodes, with its left and right sides extending to partially overlap with the source electrodes; and The drain electrode is located on the bottom surface of the silicon carbide epitaxial substrate.
2. The semiconductor component according to claim 1, characterized in that: The doping concentration of the second lightly doped layer is less than that of the well region, and the concentration of the heavily doped region is higher than that of the well region.
3. The semiconductor component according to claim 1, characterized in that: The second lightly doped layer extends to the bottom of the source and is located on the side of the corresponding heavily doped region.
4. The semiconductor component according to claim 1, characterized in that: The semiconductor component further includes an insulating unit, a conductive unit, and an insulating protection unit. The insulating unit has a first insulating layer and a second insulating layer covering the top surface of the silicon carbide epitaxial substrate. The gate is located on the surface of the first insulating layer. The second insulating layer covers the gate and the first insulating layer. The conductive unit has an ohmic contact layer that is connected to the source and a conductive layer that is electrically connected to the ohmic contact layer. The insulating protection unit is made of an insulating material and covers the conductive layer and the second insulating layer.
5. The semiconductor component according to claim 4, characterized in that: The semiconductor component further includes an electrical connection unit having a plurality of conductive structures passing through the insulating protection unit and the second insulating layer and respectively electrically connected to the conductive layer and the gate, and an electrical connection line for electrically connecting the conductive structures to the outside.