Array substrate and display panel

Abstract

The embodiment of the utility model provides an array substrate and a display panel, relates to the technical field of display, and is used for improving the preparation yield of the array substrate. The array substrate comprises a substrate body, a plurality of first signal lines arranged on the substrate body, a plurality of second signal lines arranged on the first signal lines and an electrode layer arranged on the second signal lines. The first signal lines extend along a first direction, the second signal lines extend along a second direction, and the second direction intersects with the first direction. The plurality of first signal lines and the plurality of second signal lines are intersected to form a plurality of sub-pixel areas. The electrode layer comprises a plurality of electrodes and at least one first auxiliary signal line, wherein the electrodes are located in the sub-pixel areas respectively. Wherein the orthographic projection of the first auxiliary signal line on the substrate is overlapped with the orthographic projection of the target signal line on the substrate, and the first auxiliary signal line is connected with the target signal line through at least one first connecting through hole; the target signal line is a first signal line or a second signal line.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, and no radiation, and has been developed rapidly in recent years.

[0003] During the production of TFT-LCDs, signal lines on the array substrate are prone to breakage due to foreign matter or other issues during the manufacturing process. When a signal line is broken, it can lead to display abnormalities. Utility Model Content

[0004] The purpose of this disclosure is to provide an array substrate and a display panel for improving the fabrication yield of the array substrate.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0006] On one hand, an array substrate is provided. The array substrate includes: a substrate, a plurality of first signal lines disposed on the substrate, a plurality of second signal lines disposed on a side of the plurality of first signal lines away from the substrate, and an electrode layer disposed on a side of the plurality of second signal lines away from the substrate.

[0007] Multiple first signal lines extend along a first direction and are spaced apart along a second direction; the second direction intersects the first direction. Multiple second signal lines extend along the second direction and are spaced apart along the first direction. The multiple first signal lines and multiple second signal lines intersect to form multiple sub-pixel regions. The electrode layer includes multiple electrodes located within the multiple sub-pixel regions, and at least one first auxiliary signal line.

[0008] Wherein, the orthographic projection of the first auxiliary signal line on the substrate overlaps with the orthographic projection of the target signal line on the substrate, and the first auxiliary signal line and the target signal line are connected through at least one first connecting via; the target signal line is either the first signal line or the second signal line.

[0009] In the aforementioned array substrate, the first auxiliary signal line and the target signal line are connected through one or more (two or more) first connection vias.

[0010] When the first auxiliary signal line and the target signal line are connected through a first connecting via, if there is a break in the target signal line, the portion of the target signal line on the side of the break is already connected to the first auxiliary signal line through the first connecting via. In this case, a second connecting via can be formed by drilling a hole on the portion of the target signal line on the other side of the break, extending from the upper surface of the first auxiliary signal line (the surface of the first auxiliary signal line away from the substrate) to the upper surface of the target signal line (the surface of the target signal line away from the substrate) or the interior of the target signal line. Conductive material is then filled into the second connecting via to reconnect the target signal line with the break through the first auxiliary signal line.

[0011] In this way, when repairing a broken signal line, only one hole needs to be drilled on one side of the broken point. Compared to the solution of drilling holes on both sides of the broken point and filling them with conductive material after the broken signal line is discovered, fewer holes are needed. This can avoid the problem of signal line repair failure caused by drilling failure (drilling too deep or too shallow, or drilling position deviating from the preset position) to a certain extent, and improve the success rate of repairing broken signal lines.

[0012] When the first auxiliary signal line and the target signal line are connected through multiple (two or more) first connecting through-holes, if there is a break in the target signal line, the portions of the target signal line on both sides of the break point are connected to the first auxiliary signal line through at least one first connecting through-hole, thereby restoring the target signal line with the break point to continuity through the first auxiliary signal line. When the first auxiliary signal line is formed, a pre-repair of the target signal line is already achieved. Even if a break occurs in the target signal line, the target signal line with the break point has already been restored to continuity through the first auxiliary signal line, eliminating the need for further break repair of the target signal line.

[0013] In some embodiments, the array substrate further includes an insulating layer disposed between the target signal line and the electrode layer, a first connection via penetrating the insulating layer to the target signal line, a first auxiliary signal line covering the first connection via, and at least a portion of the first auxiliary signal line being connected to the target signal line.

[0014] In some embodiments, the target signal line is the second signal line; the orthographic projection of the first auxiliary signal line on the substrate and the position where the orthographic projections of the first signal line and the second signal line on the substrate intersect have overlap.

[0015] In some embodiments, the first end and the second end of the first auxiliary signal line are located on both sides of at least one first signal line along a second direction.

[0016] In some embodiments, each second signal line is connected to multiple first auxiliary signal lines; the multiple first auxiliary signal lines connected to the same second signal line are spaced apart from each other.

[0017] In some embodiments, a portion of the first end of the first auxiliary signal line extends into a first connection via and is connected to the second signal line, and the orthographic projection of the first end of the first auxiliary signal line on the substrate does not overlap with the first signal line.

[0018] In some embodiments, a portion of the second end of the first auxiliary signal line extends into another first connection via and is connected to the second signal line, and the orthographic projection of the second end of the first auxiliary signal line on the substrate does not overlap with the first signal line.

[0019] In some embodiments, the array substrate has a second connection via, which extends through the first auxiliary signal line to the target signal line. The array substrate also includes a transition structure disposed within the second connection via, which is connected to both the first auxiliary signal line and the target signal line.

[0020] In some embodiments, the target signal line is a first signal line, and each first signal line is connected to a first auxiliary signal line through a plurality of first connection vias; the orthographic projection of the first auxiliary signal line on the substrate overlaps with the orthographic projection of the plurality of second signal lines on the substrate.

[0021] In some embodiments, the target signal line is a second signal line, and each second signal line is connected to a first auxiliary signal line through a plurality of first connection vias; the orthographic projection of the first auxiliary signal line on the substrate overlaps with the orthographic projection of the plurality of first signal lines on the substrate.

[0022] In some embodiments, the electrodes are spaced apart from the first auxiliary signal line.

[0023] In some embodiments, the array substrate further includes a plurality of transistors, wherein, in orthographic projection onto the substrate, a first signal line overlaps with the active layer of at least one transistor, and the portion of the first signal line overlapping with the active layer of the transistor forms the control electrode of the transistor. At least a portion of the first electrode of the transistor is located within a sub-pixel region and is connected to a second signal line; at least a portion of the second electrode of the transistor is located within a sub-pixel region and is connected to an electrode.

[0024] In some embodiments, the electrode layer further includes at least one second auxiliary signal line, the orthographic projection of the second auxiliary signal line on the substrate overlaps with the orthographic projection of the first electrode of the transistor on the substrate, and the second auxiliary signal line is connected to the first electrode of the transistor through at least one first connection via.

[0025] In some embodiments, the array substrate further includes a light-shielding layer disposed between the substrate and the plurality of first signal lines. The light-shielding layer includes a plurality of light-shielding portions arranged at intervals and at least one third auxiliary signal line. The orthographic projection of the third auxiliary signal line on the substrate overlaps with the orthographic projection of the target signal line on the substrate, and the third auxiliary signal line and the target signal line are connected through at least one third connection via.

[0026] In some embodiments, the third connection via penetrates the insulation layer between the third auxiliary signal line and the target signal line.

[0027] In some embodiments, the first signal line is a gate line, the second signal line is a data line, and the electrode is a pixel electrode.

[0028] On the other hand, a display panel is provided. The display panel includes: a color filter substrate, a liquid crystal layer, and an array substrate as described in any of the above embodiments. The color filter substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is disposed between the array substrate and the color filter substrate.

[0029] The above-described display panel has the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here.

[0030] In some embodiments, the display panel includes multiple gate lines, multiple data lines, and multiple light-emitting units disposed on a substrate, wherein the orthographic projections of the multiple gate lines and multiple data lines on the substrate intersect. Each light-emitting unit includes a first electrode, an organic light-emitting layer, and a second electrode stacked in a direction away from the substrate. The first electrode of the light-emitting unit is further away from the substrate than the gate lines and data lines.

[0031] The display panel also includes at least one first auxiliary signal line, which is disposed on the same layer as the first electrode and is connected to the target signal line through at least one first connection through hole; the target signal line is a gate line or a data line.

[0032] The above-described display panel has a similar structure and beneficial technical effects to the array substrate provided in some of the above embodiments, and will not be described in detail here. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0034] Figure 1This is a cross-sectional structural diagram of a display panel according to some embodiments;

[0035] Figure 2 This is a partially enlarged structural view of an array substrate according to some embodiments;

[0036] Figure 3 According to Figure 2 Cross-sectional structure diagram obtained from the mid-section line AA;

[0037] Figure 4 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0038] Figure 5 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0039] Figure 6 According to Figure 5 Cross-sectional structure diagram obtained from the mid-section line BB;

[0040] Figure 7 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0041] Figure 8 According to Figure 7 Cross-sectional structure diagram obtained from the mid-section line CC;

[0042] Figure 9 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0043] Figure 10 According to Figure 9 Cross-sectional structure diagram obtained from the mid-section line DD;

[0044] Figure 11 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0045] Figure 12 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0046] Figure 13 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0047] Figure 14 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0048] Figure 15 According to Figure 14 A cross-sectional structure diagram obtained from the mid-section line EE;

[0049] Figure 16 According to Figure 14Another cross-sectional structure diagram obtained from the mid-section line EE;

[0050] Figure 17 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0051] Figure 18 According to Figure 17 Cross-sectional structure diagram obtained from the mid-section line FF;

[0052] Figure 19 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0053] Figure 20 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0054] Figure 21 According to Figure 14 Another cross-sectional structure diagram obtained from the mid-section line EE;

[0055] Figure 22 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0056] Figure 23 According to Figure 22 Cross-sectional structure diagram obtained from the mid-section line GG;

[0057] Figure 24 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0058] Figure 25 This is a partially enlarged structural view of the array substrate according to some other embodiments;

[0059] Figure 26 According to Figure 25 Cross-sectional structure diagram obtained from the mid-section line HH;

[0060] Figure 27 According to Figure 25 Cross-sectional structure diagram obtained from mid-section line II. Detailed Implementation

[0061] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0062] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0063] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0064] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0065] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0066] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0067] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0068] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0069] Embodiments of this disclosure provide a display panel 100.

[0070] Taking display panel 100 as an LCD display panel as an example, Figure 1 This is a cross-sectional structural diagram of an LCD display panel according to some embodiments. Figure 2 This is a partially enlarged structural view of the array substrate 10 according to some embodiments.

[0071] like Figure 1 As shown, the display panel 100 includes: an array substrate 10, a color filter substrate 20 disposed on one side of the array substrate 10, and a liquid crystal layer 30 disposed between the array substrate 10 and the color filter substrate 20.

[0072] like Figure 2 As shown, the array substrate 10 includes: a substrate 1, a plurality of first signal lines 2 disposed on the substrate 1, a plurality of second signal lines 3 disposed on the plurality of first signal lines 2, and an electrode layer 4 disposed on the plurality of second signal lines 3.

[0073] Multiple first signal lines 2 extend along a first direction X and are spaced apart along a second direction Y. Multiple second signal lines 3 extend along the second direction Y and are spaced apart along the first direction X. The first direction X and the second direction Y intersect. The multiple first signal lines 2 and the multiple second signal lines 3 intersect to form multiple sub-pixel regions Q.

[0074] The electrode layer 4 includes multiple electrodes 41, each of which is located within a sub-pixel region Q.

[0075] For example, such as Figure 4 As shown, the array substrate 10 includes a gate conductive layer G, a first insulating layer J1, a source / drain conductive layer SD, and a second insulating layer J2 sequentially disposed on the substrate 1. The first insulating layer J1 is disposed between the gate conductive layer G and the source / drain conductive layer SD, and the second insulating layer J2 is disposed between the source / drain conductive layer SD and the electrode layer 4. The plurality of first signal lines 2 may be located within the gate conductive layer G, and the plurality of second signal lines 3 may be disposed within the source / drain conductive layer SD.

[0076] In this case, such as Figure 2 As shown, the first signal line 2 can be a gate line, and the second signal line 3 can be a data line. Multiple gate lines and multiple data lines intersect to define multiple sub-pixel regions Q.

[0077] For example, electrode layer 4 can be a pixel electrode layer, and correspondingly, electrode 41 is a pixel electrode.

[0078] Based on this, in some embodiments, such as Figure 2 As shown, the array substrate 10 also includes a plurality of transistors T, each transistor T being disposed at the intersection of a first signal line 2 and a second signal line 3, and at least a portion of each transistor T being located within a sub-pixel region Q. The positional relationship described here refers to the positional relationship of the transistors T, the first signal line 2, the second signal line 3, and the sub-pixel region Q projected onto the substrate 1.

[0079] like Figure 2 As shown, the control electrode T of each transistor T G Connected to a first signal line 2, the first terminal T of each transistor T S Connected to a second signal line 3, the second terminal T of each transistor T D Each electrode 41 is connected to a corresponding transistor T. Thus, each electrode 41 can be connected to the second signal line 3 via a corresponding transistor T.

[0080] For example, the control electrode T of transistor T G The connection to the first signal line 2 can be the control electrode T of transistor T. G It can be connected to the first signal line 2, or a part of the first signal line 2 can be used as the control electrode T of transistor T. G .

[0081] Based on the above embodiments, the first signal line 2 can be used to output a switch control signal to the transistor T to control the transistor T to be turned on or off; the second signal line 3 can be used to transmit data signals. When the transistor T is turned on, the data signal from the second signal line 3 is transmitted to the electrode 41 through the transistor T.

[0082] If the first signal line 2 is broken, at least some of the transistors T connected to the first signal line 2 may be unable to receive the switch control signal normally. As a result, the electrode 41 connected to the transistor T that cannot receive the switch control signal normally will not be able to receive the data signal normally, which will lead to the display panel 100 displaying abnormalities.

[0083] If the second signal line 3 breaks, at least some of the electrodes 41 connected to the second signal line 3 may be unable to receive data signals normally, which may cause the display panel 100 to malfunction.

[0084] Therefore, during the fabrication of the array substrate 10, after the signal lines (first signal line and second signal line) are formed, it is necessary to detect whether there are any problematic signal lines in the array substrate 10 (e.g., the signal lines are cracked or broken, causing abnormal signal transmission), and repair the problematic signal lines to ensure the yield of the array substrate 10.

[0085] The following example demonstrates how to repair a broken wire in the second signal line 3. Figure 2 and Figure 3 As shown, during the fabrication process of the array substrate 10, when forming the second signal line 3, since a part of the second signal line 3 needs to cross the first signal line 2 (the position where the orthographic projections of the second signal line 3 and the first signal line 2 on the substrate 1 overlap), there will be a certain step difference at the crossing position of the second signal line 3. The surface stress of the second signal line 3 in the step difference part is large, so this part is prone to defects such as cracks or breaks under the action of stress.

[0086] In some embodiments, the method for fabricating the array substrate 10 includes the following steps.

[0087] A1. Perform wire breakage detection on multiple second signal lines 3 to determine whether there is a wire breakage point R1 in the second signal line 3.

[0088] A2, such as Figure 4 As shown, the sub-pixel region Q (e.g., adjacent to the break point R1 of the second signal line 3) is... Figure 4 The portion of electrode 41 in the first sub-pixel region Q1 that is adjacent to the break point R1 is removed.

[0089] A3. Disconnect the connection between the transistor T connected to the electrode 41 in the first sub-pixel region Q1 and the first signal line 2 connected to the transistor T. Disconnect the connection between the transistor T connected to the electrode 41 in the second sub-pixel region Q and the first signal line 2 connected to the transistor T.

[0090] The second sub-pixel region Q2 is another sub-pixel region Q that is adjacent (or close to) the break point R1 and adjacent to the first sub-pixel region Q1 along the second direction Y.

[0091] A4. Using laser drilling technology, two connecting holes L are formed on both sides of the break point R1 of the second signal line 3.

[0092] A5, deposited metal bridging (e.g.) Figure 4The metal bridge (U-shaped bridge) has two ends connected to the second signal line 3 through two connection holes L. The two ends of the metal bridge are located on both sides of the break point R1, and are respectively connected to the two parts of the second signal line 3 that are separated by the break point R1.

[0093] The order of steps A2, A3, and A4 above is not limited.

[0094] During the deposition of the metal bridging, part of the material used to form the metal bridging will fill the connection hole L so that the metal bridging can be connected to the second signal line 3, and the portion of the second signal line 3 located on both sides of the break point R1 can be reconnected through the metal bridging.

[0095] However, when repairing the second signal line 3 using this broken line repair method, the metal bridging needs to be done from two adjacent sub-pixel regions Q (e.g. Figure 4 The first sub-pixel region Q1 and the second sub-pixel region Q2 shown in the diagram pass through the metal bridge. Therefore, in step A3, it is necessary to disconnect the electrode 41 and the transistor T corresponding to the electrode 41 within the sub-pixel region Q through which the metal bridge passes, in order to perform darkening processing on these two sub-pixel regions Q. While repairing the broken line of the second signal line 3, this part of the sub-pixel region Q that has undergone darkening processing can no longer be used for display on the display panel 100, which has a certain impact on the display effect of the display panel 100.

[0096] In step A4, two drilling operations are required to form connecting holes L on both sides of the break point R1. During the drilling process, the drilling depth may be too deep or too shallow, or the drilling position may deviate from the target position, causing the formed metal bridge to fail to connect with the second signal line 3 through the connecting hole L. The risk of connection failure of the connecting hole L is relatively high, resulting in the risk of repair failure.

[0097] In step A5, if there is a break in the metal bridge during deposition, the second signal line 3 cannot be restored through the metal bridge, resulting in repair failure.

[0098] In summary, the array substrate 10 prepared by the above method has an improved yield, but signal line breakage may still occur. Therefore, this disclosure proposes an array substrate 10 and its preparation method.

[0099] In some embodiments, the method for fabricating the array substrate 10 includes the following steps.

[0100] S1. Multiple first signal lines 2 are formed on substrate 1.

[0101] S2. Multiple second signal lines 3 are formed on the side of the multiple first signal lines 2 away from the substrate.

[0102] S3. An electrode layer 4 is formed on the side of the plurality of second signal lines 3 away from the substrate 1. The electrode layer 4 includes a plurality of electrodes 41 located in a plurality of sub-pixel regions Q, and at least one first auxiliary signal line 42; the first auxiliary signal line 42 is connected to the target signal line through a first connecting via K1.

[0103] For example, the first connection via K1 is located in the insulating layer below the electrode layer 4, and the target signal line is either the first signal line 2 or the second signal line 3. Figure 7 As shown, when the target signal line is the second signal line 3, the insulating layer can refer to the second insulating layer J2. For example... Figure 18 As shown, when the target signal line is the first signal line 2, the insulating layer can refer to the first insulating layer J1 and the second insulating layer J2.

[0104] In the array substrate 10 formed in this way, such as Figure 5 and Figure 6 As shown, the electrode layer 4 further includes at least one first auxiliary signal line 42. The orthographic projection of the first auxiliary signal line 42 on the substrate 1 overlaps with the orthographic projection of the target signal line on the substrate 1, and the first auxiliary signal line 42 and the target signal line are connected through at least one first connecting via K1. The target signal line is either the first signal line 2 or the second signal line 3. In the array substrate 10, the first connecting via K1 is not visible on the surface of the first auxiliary signal line 42 away from the target signal line.

[0105] Thus, on the array substrate 10, for each first auxiliary signal line 42, a portion of the first auxiliary signal line 42 directly contacts the target signal line to achieve a connection between the two. When forming the first auxiliary signal line 42, a portion of the first auxiliary signal line 42 extends into the first connection via K1 and connects to the target signal line, thereby ensuring that the potentials of the first auxiliary signal line 42 and the target signal line are kept consistent, and preventing parasitic capacitance from being generated in the overlapping portion of the target signal line and the first auxiliary signal line 42.

[0106] Meanwhile, in the array substrate 10, the first auxiliary signal line 42 and the target signal line are connected through one or more (two or more) first connection vias K1.

[0107] When the first auxiliary signal line 42 and the target signal line are connected through a first connecting through hole K1, if there is a break point in the target signal line, the portion of the target signal line located on the side of the break point has already been connected to the first auxiliary signal line 42 through the first connecting through hole K1.

[0108] like Figure 7 and Figure 8As shown, in this case, a second connecting via K2 can be obtained by drilling a hole on the part of the target signal line located on the other side of the break point, extending from the upper surface of the first auxiliary signal line 42 (the surface of the first auxiliary signal line 42 away from the substrate 1) to the upper surface of the target signal line (the surface of the target signal line away from the substrate 1) or inside the target signal line. Conductive material is filled into the second connecting via K2 to obtain a transition structure 5 that is connected to the target signal line and the first auxiliary signal line 42 respectively, so that the target signal line with the break point can be reconnected through the first auxiliary signal line 42 and the transition structure 5.

[0109] In this way, when repairing a broken target signal line, only one side of the broken point needs to be drilled. Compared with the broken line repair scheme described in steps A1 to A5 above, the number of holes required is reduced, which can avoid the problem of signal line broken line repair failure caused by drilling failure (drilling too deep or too shallow, or drilling position deviating from the preset position) to a certain extent, and improve the success rate of breaking the target signal line.

[0110] Furthermore, in the array substrate 10, only the setting position of the second connection via K2 needs to be reserved to realize the repair of the broken target signal line, reducing the space required for repairing the broken target signal line, thereby reducing the space required for repairing the broken target signal line and limiting the wiring design on the array substrate 10.

[0111] When the first auxiliary signal line 42 and the target signal line are connected by multiple (two or more) first connecting through holes K1, if there is a break in the target signal line, such as Figure 9 and Figure 10 As shown, the portions of the target signal line located on both sides of the break point are connected to the first auxiliary signal line 42 through at least one first connecting through-hole K1, thereby restoring the target signal line with the break point through the first auxiliary signal line 42. When the first auxiliary signal line is formed, a pre-repair of the target signal line is already achieved. Even if a break point occurs in the target signal line, the target signal line with the break point has already been restored through the first auxiliary signal line 42, eliminating the need for further break repair of the target signal line.

[0112] In this embodiment, regardless of whether the first auxiliary signal line 42 is connected to the target signal line through one or more first connecting vias K1 during its formation, the first auxiliary signal line 42 can repair the broken line of the target signal line without occupying the position of the sub-pixel area Q. Compared with the array substrate 10 formed by the preparation methods of steps A1 to A5, it is not necessary to perform darkening processing on the sub-pixel area Q adjacent to the broken point of the target signal line. While repairing the broken line of the target signal line, the number of sub-pixel areas Q used for display on the array substrate 10 is not reduced, thus ensuring the display effect of the display panel 100.

[0113] Based on this, if the first auxiliary signal line 42 is broken or damaged, and the target signal line connected to the first auxiliary signal line 42 has a break point, it is only necessary to perform deposition repair on the first auxiliary signal line 42 to restore the target signal line with the break point through the first auxiliary signal line 42, without the need for drilling or cross-line repair, thus simplifying the fabrication process of the array substrate 10.

[0114] Based on the above embodiments, in some embodiments, the array substrate 10 further includes an insulating layer disposed between the target signal line and the electrode layer 4, a first connection via K1 penetrating through the insulating layer to the target signal line, a first auxiliary signal line 42 covering the first connection via K1, and at least a portion of the first auxiliary signal line 42 being connected to the target signal line.

[0115] like Figure 6 , Figure 8 and Figure 10 As shown, when the target signal line is the second signal line 3, the insulating layer refers to the second insulating layer J2.

[0116] like Figure 18 As shown, when the target signal line is the first signal line 2, the insulating layer refers to the first insulating layer J1 and the second insulating layer J2.

[0117] During the fabrication of the array substrate 10, the first auxiliary signal line 42 is formed after the first connecting via K1. When the first auxiliary signal line 42 is formed, a portion of the material used to form the first auxiliary signal line 42 will fill the first connecting via K1 and come into contact with the target signal line.

[0118] The resulting first auxiliary signal line 42 includes a portion located on the side of the insulating layer away from the target signal line, and another portion located within the first connecting via K1. The portion of the first auxiliary signal line 42 located within the first connecting via K1 contacts the target signal line to achieve connection, while the portion of the first auxiliary signal line 42 located on the side of the insulating layer away from the target signal line is connected to the target signal line through the portion located within the first via K1. The phrase "at least a portion of the first auxiliary signal line 42" refers to the portion of the first auxiliary signal line 42 connected to the target signal line located within the first connecting via K1.

[0119] In some embodiments, such as Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 17 , Figure 19 and Figure 20 As shown, electrode 41 and the first auxiliary signal line 42 are spaced apart.

[0120] In this way, while forming the electrode 41 located within the sub-pixel region Q, a first auxiliary signal line 42 overlapping with the first signal line 2 or the second signal line 3 is formed, and the first auxiliary signal line 42 is connected to the first signal line 2 or the second signal line 3. In the orthographic projection onto the substrate 1, the first auxiliary signal line 42 does not overlap with the sub-pixel region Q, thus avoiding any impact of the first auxiliary signal line 42 on the display of the sub-pixel region Q.

[0121] Some embodiments of this disclosure will be described using the target signal line as the second signal line 3 as an example.

[0122] In some embodiments, such as Figure 5 , Figure 7 and Figure 9 As shown, the target signal line is the second signal line 3; the orthographic projection of the first auxiliary signal line 42 on the substrate 1 overlaps with the orthographic projections of the first signal line 2 and the second signal line 3 on the substrate.

[0123] As mentioned above, the second signal line 3 is prone to breakage at the intersection with the first signal line 2 due to the step difference. Therefore, when forming the first auxiliary signal line 42 for connecting with the second signal line 3, the first auxiliary signal line 42 is set at the intersection of the second signal line 3 and at least one first signal line 2.

[0124] In the orthographic projection onto the substrate 1, each first signal line 2 intersects with multiple second signal lines 3, and each second signal line 3 intersects with multiple first signal lines 2. When repairing the broken second signal line 3 using the first auxiliary signal line 42, as... Figure 7 , Figure 9 and Figure 11 As shown, the orthographic projection of the first auxiliary signal line 42 on the substrate 1 overlaps with the orthographic projection of a second signal line 3 on the substrate, and also overlaps with the orthographic projection of at least one (one, two, or more) first signal lines 2 on the substrate. That is, each first auxiliary signal line 42 may be located at the position where the second signal line 3 intersects with a first signal line 2, or at the position where the second signal line 3 intersects with multiple first signal lines 2.

[0125] like Figure 7 and Figure 9 As shown, each first auxiliary signal line 42 can be located at the intersection of a second signal line 3 and a first signal line 2. Compared with the array substrate 10 formed by the preparation methods of steps A1 to A5, the length of the first auxiliary signal line 42 is shorter than that of the U-shaped metal repair line, which can avoid the risk of breakage caused by the excessive length of the first auxiliary signal line 42, thereby improving the success rate of the breakage repair of the second signal line 3.

[0126] like Figure 11 As shown, each first auxiliary signal line 42 can also be located at the intersection of a second signal line 3 and multiple first signal lines 2. In this way, when both ends of the first auxiliary signal line 42 are connected to the second signal line 3, if a break occurs at any of the multiple crossing points of the second signal line 3 (the points where the orthographic projections of the second signal line 3 and the first signal line 2 on the substrate 1 intersect), the second signal line 3 can be reconnected through the first auxiliary signal line 42. Compared to setting a separate first auxiliary signal line 42 at each intersection point, this reduces the number of first auxiliary signal lines 42 and improves the efficiency of repairing breaks in the second signal line 3.

[0127] Based on this, in some embodiments, such as Figure 7 , Figure 9 and Figure 11 As shown, when the first auxiliary signal line 42 is used to repair the broken wire of the second signal line 3, the first end and the second end of the first auxiliary signal line 42 are located on both sides of at least one first signal line 2 along the second direction Y.

[0128] Thus, both ends of the first auxiliary signal line 42 are located on either side of at least one first signal line 2. For example, as Figure 7 , Figure 9 and Figure 11As shown, the first end and the second end of the first auxiliary signal line 42 are located on both sides of one or more (two or more) first signal lines 2 along the second direction Y, so that the position where the first auxiliary signal line 42 connects to the second signal line 3 (the setting position of the first connecting through hole K1) is located outside the position where the second signal line 3 is prone to breakage. When the second signal line 3 breaks, such as Figure 8 and Figure 10 As shown, the break point (break point R1) is located between two connection points of the first auxiliary signal line 42 and the second signal line 3 (two first connection through holes K1, or one first connection through hole K1 and one second connection through hole K2), ensuring that the second signal line 3 can be reconnected through the first auxiliary signal line 42.

[0129] For example, when the second signal line 3 has a break point R1 at the part opposite to the first auxiliary signal line 42, the first auxiliary signal line 42 and the second signal line 3 are connected by a plurality of (two or more) connecting vias, wherein at least two connecting vias (at least two first connecting vias K1, or one second connecting via K2 and at least one first connecting via K1) are located on both sides of the break point R1 of the second signal line 3.

[0130] In some embodiments, such as Figure 7 , Figure 9 and Figure 11 As shown, each second signal line 3 is connected to multiple first auxiliary signal lines 42, and the multiple first auxiliary signal lines 42 connected to the same second signal line 3 are spaced apart from each other.

[0131] In this way, each second signal line 3 can be provided with multiple first auxiliary signal lines 42. The length of each first auxiliary signal line 42 is shorter, which avoids the risk of wire breakage caused by the excessive length of the first auxiliary signal line 42 and improves the reliability of the first auxiliary signal line 42.

[0132] In this case, such as Figure 7 and Figure 9 As shown, the orthographic projection of each first auxiliary signal line 42 on the substrate 1 overlaps with the orthographic projection of a second signal line 3 on the substrate 1 and the orthographic projection of a first signal line 2 on the substrate 1.

[0133] Or, such as Figure 11 As shown, the orthographic projection of each first auxiliary signal line 42 on the substrate 1 overlaps with the orthographic projections of multiple (two or more) second signal lines 3 on the substrate 1, as well as the orthographic projections of multiple first signal lines 2 on the substrate 1.

[0134] In other embodiments, such as Figure 12As shown, each second signal line 3 is connected to a first auxiliary signal line 42, and the length of the first auxiliary signal line 42 is the same as or approximately the same as the length of the second signal line 3.

[0135] In the orthographic projection onto the substrate 1, the two ends of the first auxiliary signal line 42 are respectively located on both sides of all the first signal lines 2 that intersect with the second signal line 3 in the second direction Y. In this way, the area of ​​the first auxiliary signal line 42 is larger, which can better achieve the effect of reducing the line resistance of the second signal line 3.

[0136] In some embodiments, when the second signal line 3 is repaired by means of the first auxiliary signal line 42, such as Figure 7 , Figure 9 and Figure 11 As shown, the orthographic projection of the first end of the first auxiliary signal line 42 onto the substrate 1 does not overlap with the first signal line 2. Figure 8 and Figure 10 As shown, a portion of the first end of the first auxiliary signal line 42 extends into a first connection through hole K1 and is connected to the second signal line 3.

[0137] Since the first connecting through hole K1 needs to avoid the first signal line 2, by setting the first end of the first auxiliary signal line 42 on one side of the first signal line 2, it can be ensured that the first end of the first auxiliary signal line 42 can better cover the first connecting through hole K1, and connect to the second signal line 3 through the first connecting through hole K1, thereby ensuring that the broken wire of the second signal line 3 can be repaired through the first auxiliary signal line 42.

[0138] In some embodiments, when the second signal line 3 is repaired by means of the first auxiliary signal line 42, such as Figure 7 , Figure 9 and Figure 11 As shown, the orthographic projection of the second end of the first auxiliary signal line 42 onto the substrate 1 does not overlap with the first signal line 2. Figure 8 and Figure 10 As shown, a portion of the second end of the first auxiliary signal line 42 extends into another first connection through hole K1 and is connected to the second signal line 3.

[0139] Since the first connecting through hole K1 needs to avoid the first signal line 2, by setting the second end of the first auxiliary signal line 42 on one side of the first signal line 2, it can be ensured that the first end of the first auxiliary signal line 42 can better cover the first connecting through hole K1, and connect to the second signal line 3 through the first connecting through hole K1, thereby ensuring that the broken wire of the second signal line 3 can be repaired through the first auxiliary signal line 42.

[0140] In some embodiments, such as Figure 7 and Figure 8 As shown, after the auxiliary signal line 42 is formed, when the second signal line 3 and the first signal line 2 are broken at the intersection, a second connecting through hole K2 is formed. Conductive material is filled into the second connecting through hole K2 to form a transition structure 5. The transition structure 5 is connected to the second signal line 3 and the second end of the auxiliary signal line 42 so that the broken second signal line 3 can be connected through the transition structure 5 and the first auxiliary signal line 42.

[0141] Thus, during the fabrication of the array substrate 10, only a second connection via K2 needs to be formed at the break location, and conductive material needs to be filled into the second connection via K2 to repair the break in the second signal line 3. Compared to Figure 4 The broken line repair scheme shown can simplify the broken line repair process of the signal line, and while repairing the broken line, it does not require darkening the sub-pixel area Q adjacent to the broken line point R1. While repairing the broken line of the second signal line 3, it will not affect the normal display of the surrounding sub-pixel area Q.

[0142] In some embodiments of this disclosure, the second signal line 3 with the break point R1 can be restored to conduction via the first auxiliary signal line 42. Furthermore, all transistors T connected to the second signal line 3 are connected to their corresponding electrodes 41, and each electrode 41 can receive data signals from the second signal line 3 through its connected transistor T. While ensuring the effective conduction of the second signal line 3 in the array substrate 10, it is not necessary to sacrifice the sub-pixel region Q; each sub-pixel region Q can function normally, thus improving the yield of the array substrate 10 while ensuring the display quality of the display panel 100.

[0143] In some embodiments, such as Figure 13 , Figure 14 , Figure 15 and Figure 16 As shown, the electrode layer 4 also includes at least one second auxiliary signal line 43. The orthogonal projection of the second auxiliary signal line 43 onto the substrate 1 is perpendicular to the first electrode T of the transistor T. S The orthographic projections on substrate 1 overlap, and the second auxiliary signal line 43 intersects with the first electrode T of transistor T. S They are connected by at least one first connecting through hole K1.

[0144] For example, referring to the connection method of the first auxiliary signal line 42 and the second signal line 3 described above, the two ends of the second auxiliary signal line 43 can be respectively connected to the first electrode T of the transistor T through a first connection via K1. S Alternatively, the two ends of the second auxiliary signal line 43 can be connected to the first terminal T of the transistor T through a first connection via K1 and a second connection via K2, respectively. S connect.

[0145] Through the second auxiliary signal line 43, the first electrode T of transistor T can be reduced. S On the one hand, the resistor can also be used to control the first electrode T of transistor T via the second auxiliary signal line 43. S Repairing broken wires improves the fabrication yield of the array substrate 10.

[0146] like Figure 13 and Figure 14 As shown, when the target signal line is the second signal line 3, the adjacent first auxiliary signal line 42 and second auxiliary signal line 43 can be spaced apart from each other or connected to each other to form an integral structure.

[0147] Taking the target signal line as the first signal line 2 as an example, some embodiments of this disclosure will be described.

[0148] In some embodiments, such as Figure 17 , Figure 18 and Figure 19 As shown, the target signal line is the first signal line 2, and each first signal line 2 is connected to a first auxiliary signal line 42 through at least one first connecting via K1; the orthographic projection of the first auxiliary signal line 42 on the substrate 1 overlaps with the orthographic projection of multiple second signal lines 3 on the substrate 1.

[0149] For example, such as Figure 17 , Figure 18 and Figure 19 As shown, the target signal line is the first signal line 2. Each first signal line 2 is connected to a first auxiliary signal line 42 through multiple first connection vias K1. The orthographic projection of the first auxiliary signal line 42 on the substrate 1 overlaps with the orthographic projection of multiple second signal lines 3 on the substrate.

[0150] Each first auxiliary signal line 42 can be connected to the first signal line 2 through one or more (two or more) first connection vias K1. The first signal line 2 with a break point R2 can be restored to conduction via the first auxiliary signal line 42, allowing all transistors T connected to the first signal line 2 to function normally. While ensuring the effective conduction of the first signal line 2 in the array substrate 10, the first auxiliary signal line 42 does not occupy the sub-pixel area Q, and each sub-pixel area Q can function normally, thus improving the yield of the array substrate 10 while ensuring the display quality of the display panel 100.

[0151] The specific implementation method and technical effect of repairing the broken wire of the first signal line 2 by means of the first auxiliary signal line 42 and ensuring the conduction of the first signal line 2 are described in the previous section on the connection method between the first auxiliary signal line 42 and the second signal line 3, and will not be repeated here.

[0152] Based on the foregoing embodiments, such as Figure 20 As shown, when the first auxiliary signal line 42 is connected to the first signal line 2, the adjacent first auxiliary signal line 42 and the second auxiliary signal line 43 are spaced apart from each other to avoid signal crosstalk.

[0153] At the same time, such as Figure 17 and Figure 19 As shown, the two ends of the first auxiliary signal line 42, which is provided corresponding to the first signal line 2, are respectively located on both sides of at least one second signal line 3 in the first direction X, so as to ensure that the first end of the first auxiliary signal line 42 can be connected to the first signal line 2 through the first connecting through hole K1, and the second end of the first auxiliary signal line 42 can be connected to the first signal line 2 through the first connecting through hole K1 or the second connecting through hole K2.

[0154] Alternatively, the first auxiliary signal line 42, which is provided in correspondence with the first signal line 2, may also be located between two adjacent second signal lines 3. That is, in the orthographic projection onto the substrate 1, the first auxiliary signal line 42 is located between two adjacent second signal lines 3.

[0155] Based on the foregoing embodiments, in some embodiments of this disclosure, the first connection via K1 refers to a connection hole formed before the formation of the auxiliary signal line (first auxiliary signal line 42 or second auxiliary signal line 43) within the electrode layer 4, penetrating the insulating layer between the auxiliary signal line and the target signal line to the target signal line. The first connection via K1 in the array substrate 10 may be entirely through the first signal line 2, entirely through the second signal line 3, or partially through the first signal line 2 and partially through the second signal line 3. Simultaneously, the first connection via K1 in the array substrate 10 may also partially penetrate to the first electrode T of the transistor T. S .

[0156] The second connecting hole K2 refers to the connecting hole formed after the auxiliary signal line is formed in the electrode layer 4, which extends from the auxiliary signal line to the target signal line.

[0157] In some embodiments, such as Figure 15 , Figure 16 and Figure 21 As shown, in the orthographic projection onto the substrate 1, the first signal line 2 overlaps with the active layer 6 of at least one transistor T, and the overlapping portion of the first signal line 2 and the active layer 6 of the transistor T forms the control electrode T of the transistor T. G .

[0158] like Figure 15 and Figure 16As shown, in the array substrate 10, the first signal line 2 can be disposed between the active layer 6 and the substrate 1. In the orthographic projection onto the substrate 1, the active layer 6 of the transistor T falls within the range of the first signal line 2. In this way, the first signal line 2 can serve as a light-shielding part of the active layer 6 of the transistor T, preventing light from shining on the active layer 6 and causing damage to the active layer 6.

[0159] In this case, such as Figure 15 As shown, in the array substrate 10, a third insulating layer J3 may be provided between the active layer 6 and the source / drain metal layer SD. That is, after the active layer 6 is formed on the substrate 1, the third insulating layer J3 may be formed first on the side of the active layer 6 away from the substrate 1, and then the source / drain metal layer SD may be formed on the side of the third insulating layer J3 away from the substrate 1. The source / drain metal layer SD is connected to the active layer 6 through a through-hole penetrating the third insulating layer J3.

[0160] Or, such as Figure 16 As shown, in the array substrate 10, the source / drain metal layer SD can also be formed on the side of the active layer 6 away from the substrate 1, and the source / drain metal layer SD can be directly connected to the active layer 6.

[0161] The specific design can be adapted according to actual needs, and this disclosure does not limit it.

[0162] like Figure 21 As shown, in the array substrate 10, the first signal line 2 can also be located on the side of the active layer 6 away from the substrate 1. In this case, the array substrate 10 also includes a plurality of light-shielding portions 71. In the orthographic projection onto the substrate 1, the active layer 6 of the transistor T falls within the range of the light-shielding portions 71. By providing the light-shielding portions 71, it is possible to prevent light from shining on the active layer 6 and causing damage to the active layer 6.

[0163] In this configuration, the array substrate 10 further includes a fourth insulating layer J4 disposed between the light-shielding portion 71 and the active layer 6. During the fabrication of the array substrate 10, a plurality of light-shielding portions 71 may be formed on the substrate 1 first, then the fourth insulating layer J4 may be formed on the side of the plurality of light-shielding portions 71 away from the substrate 1, and subsequently, the active layer 6 of each transistor T may be formed on the side of the fourth insulating layer J4 away from the substrate 1. Thus,

[0164] In some embodiments, such as Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 and Figure 27As shown, the first signal line 2 is disposed on the side of the active layer 6 of the transistor T away from the substrate 1. The array substrate 10 also includes a light-shielding layer 7, which is disposed between the substrate 1 and the plurality of first signal lines 2. The light-shielding layer 7 includes a plurality of light-shielding portions 71 arranged at intervals and at least one third auxiliary signal line 72. The orthographic projection of the third auxiliary signal line 72 on the substrate 1 overlaps with the orthographic projection of the target signal line on the substrate 1, and the third auxiliary signal line 72 and the target signal line are connected through at least one third connection via K3.

[0165] The third connecting through-hole K3 penetrates the insulation layer between the third auxiliary signal line 72 and the target signal line. For example... Figure 23 As shown, the target signal line is the second signal line 3, and the third connecting through hole K3 penetrates the first insulating layer J1, the third insulating layer J3 and the fourth insulating layer J4.

[0166] During the fabrication of the array substrate 10, before forming the target signal line, a third connection via K3 can be formed on the insulating layer between the target signal line and the light-shielding layer 7. In this way, when forming the target signal line, a portion of the material used to form the target signal line will fill the third connection via K3, so that the formed target signal line can be connected to the third auxiliary signal line 72 through the third connection via K3.

[0167] Based on this, the arrangement of the third auxiliary signal line 72 in the light-shielding layer 7 can be referred to in the previous description of the arrangement of the first auxiliary signal line 42 in the electrode layer 4. The connection method between the third auxiliary signal line 72 and the target signal line can be referred to in the previous description of the connection method between the first auxiliary signal line 42 and the target signal line. It will not be elaborated here.

[0168] That is, in some embodiments of this disclosure, the auxiliary signal lines in the electrode layer 4 of the array substrate 10 can be used for the first signal line 2, the second signal line 3, and the first electrode T of the transistor T. S Repairing the broken wires of at least one of them; at the same time, when the array substrate 10 also includes a light-shielding layer 7, the auxiliary signal lines disposed within the light-shielding layer 7 can also be used for the first signal line 2, the second signal line 3, and the first electrode T of the transistor T. S Repair the broken wires of at least one of them.

[0169] Thus, the first signal line 2, the second signal line 3, and the first electrode T of transistor T S Any of them can be connected to the auxiliary signal line in the electrode layer 4 and / or the auxiliary signal line in the light-shielding layer 7, and the broken line can be repaired through the auxiliary signal line to improve the fabrication yield of the array substrate 10.

[0170] like Figure 22As shown, when the third auxiliary signal line 72 is connected to the second signal line 3, the third auxiliary signal line 72 and the light-shielding part 71 are arranged at intervals.

[0171] like Figure 24 , Figure 25 and Figure 26 As shown, when the third auxiliary signal line 72 is connected to the first signal line 2, the third auxiliary signal line 72 and the light-shielding part 71 can be arranged at intervals or connected to each other to form an integral structure.

[0172] Based on the foregoing embodiments, the technical solutions provided by some embodiments of this disclosure are not limited to LCD display panels, but can also be applied to OLED display panels.

[0173] Specifically, the OLED display panel includes multiple light-emitting units, multiple gate lines, and multiple data lines disposed on a substrate 1, wherein the orthographic projections of the multiple gate lines and multiple data lines on the substrate 1 intersect. Each light-emitting unit includes a first electrode, an organic light-emitting layer, and a second electrode stacked along a direction away from the substrate 1.

[0174] The first electrode of the light-emitting unit is further away from the substrate 1 than the gate line and the data line. Therefore, in an OLED display panel, when forming multiple first electrodes, the conductive material layer forming the first electrode can also be used to simultaneously form the first auxiliary signal line, and the first auxiliary signal line can be connected to the gate line or the data line.

[0175] For specific connection methods, please refer to the previous section on the connection methods of auxiliary signal lines and target signal lines in the LCD display panel; they will not be elaborated upon here.

[0176] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; Multiple first signal lines are disposed on the substrate; the multiple first signal lines extend along a first direction and are spaced apart along a second direction; The second direction intersects the first direction; Multiple second signal lines are disposed on the side of the multiple first signal lines away from the substrate; the multiple second signal lines extend along the second direction and are spaced apart along the first direction; the multiple first signal lines and the multiple second signal lines intersect to form multiple sub-pixel regions; An electrode layer is disposed on the side of the plurality of second signal lines away from the substrate; the electrode layer includes a plurality of electrodes respectively located in the plurality of sub-pixel regions, and at least one first auxiliary signal line; Wherein, the orthographic projection of the first auxiliary signal line on the substrate overlaps with the orthographic projection of the target signal line on the substrate, and the first auxiliary signal line and the target signal line are connected through at least one first connecting via; the target signal line is either the first signal line or the second signal line.

2. The array substrate according to claim 1, characterized in that, The array substrate further includes: An insulating layer is disposed between the target signal line and the electrode layer; the first connecting via penetrates the insulating layer to the target signal line, the first auxiliary signal line covers the first connecting via, and at least a portion of the first auxiliary signal line is connected to the target signal line.

3. The array substrate according to claim 2, characterized in that, The target signal line is the second signal line; The orthographic projection of the first auxiliary signal line on the substrate overlaps with the orthographic projections of the first signal line and the second signal line on the substrate at the points where they intersect.

4. The array substrate according to claim 3, characterized in that, The first end and the second end of the first auxiliary signal line are located on both sides of at least one of the first signal lines along the second direction.

5. The array substrate according to claim 3, characterized in that, Each of the second signal lines is connected to multiple of the first auxiliary signal lines; The multiple first auxiliary signal lines connected to the same second signal line are spaced apart from each other.

6. The array substrate according to claim 3, characterized in that, A portion of the first end of the first auxiliary signal line extends into a first connection via and connects to the second signal line, and the orthographic projection of the first end of the first auxiliary signal line on the substrate does not overlap with the first signal line.

7. The array substrate according to claim 6, characterized in that, A portion of the second end of the first auxiliary signal line extends into another of the first connection vias and connects to the second signal line, and the orthographic projection of the second end of the first auxiliary signal line on the substrate does not overlap with the first signal line.

8. The array substrate according to claim 6, characterized in that, The array substrate has a second connection via, which extends through the first auxiliary signal line to the target signal line. The array substrate further includes: a transition structure disposed in the second connection through hole and connected to the first auxiliary signal line and the target signal line respectively.

9. The array substrate according to claim 2, characterized in that, The target signal line is the first signal line, and each first signal line is connected to a first auxiliary signal line through multiple first connecting vias; the orthographic projection of the first auxiliary signal line on the substrate overlaps with the orthographic projection of the multiple second signal lines on the substrate; or... The target signal line is the second signal line, and each second signal line is connected to a first auxiliary signal line through multiple first connection vias; the orthographic projection of the first auxiliary signal line on the substrate overlaps with the orthographic projection of the multiple first signal lines on the substrate.

10. The array substrate according to any one of claims 1 to 9, characterized in that, The electrodes are spaced apart from the first auxiliary signal line.

11. The array substrate according to any one of claims 1 to 9, characterized in that, The array substrate also includes multiple transistors; In a projection onto the substrate, the first signal line overlaps with the active layer of at least one transistor, and the portion of the first signal line that overlaps with the active layer of the transistor forms the control electrode of the transistor. At least a portion of the first electrode of the transistor is located within one of the sub-pixel regions and connected to a second signal line, and the second electrode of the transistor is located within one of the sub-pixel regions and connected to one of the electrodes; The electrode layer further includes at least one second auxiliary signal line, the orthographic projection of the second auxiliary signal line on the substrate overlaps with the orthographic projection of the first electrode of the transistor on the substrate, and the second auxiliary signal line and the first electrode of the transistor are connected through at least one first connection via.

12. The array substrate according to any one of claims 1 to 9, characterized in that, The array substrate further includes: A light-shielding layer is disposed between the substrate and the plurality of first signal lines; the light-shielding layer includes a plurality of light-shielding portions arranged at intervals and at least one third auxiliary signal line; The orthographic projection of the third auxiliary signal line on the substrate overlaps with the orthographic projection of the target signal line on the substrate, and the third auxiliary signal line and the target signal line are connected by at least one third connecting via.

13. The array substrate according to any one of claims 1 to 9, characterized in that, The first signal line is a gate line, the second signal line is a data line, and the electrode is a pixel electrode.

14. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 13; A color filter substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the color filter substrate.

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