Asymmetric trench gate silicon carbide VDMOS

Abstract

The utility model provides an asymmetric trench gate silicon carbide VDMOS. The asymmetric trench gate silicon carbide VDMOS is characterized in that a first drift layer is connected to a silicon carbide substrate; the first low-resistance region is connected to the first drift layer, and the second low-resistance region is connected to the first drift layer; the first P-type source region is connected to the second low-resistance region, the P-type well region is connected to the lug boss, and the second P-type source region is connected to the first low-resistance region, the lug boss and the P-type well region; the second drift layer is connected with the second low-resistance region; the second drift layer is respectively connected with the lug boss, the P-type well region and the first P-type source region; the insulating dielectric layer is respectively connected with the first P-type source region, the second drift layer, the P-type well region, the N-type source region and the protruding part; a groove is formed in the insulating medium layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the first P-type source region, the P-type well region, the N-type source region and the second P-type source region; the drain metal layer is connected to the silicon carbide substrate; the follow current capability of the body diode is improved and the body diode loss is reduced.

Description

Technical Field

[0001] This utility model relates to an asymmetric trench gate silicon carbide VDMOS. Background Technology

[0002] Silicon carbide VDMOS is a typical example of silicon carbide power devices, widely used in electric vehicles, aerospace, power conversion, and other fields. For silicon carbide power VDMOS, the performance requirements vary across different applications, but existing VDMOS devices still require higher breakdown voltage, lower on-resistance, higher gate reliability, and lower body diode conduction loss. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide an asymmetric trench gate silicon carbide VDMOS, which improves the freewheeling capability of the body diode and reduces the body diode loss by designing the device structure asymmetrically.

[0004] This invention provides an asymmetric trench-gate silicon carbide VDMOS, comprising:

[0005] silicon carbide substrate;

[0006] A first drift layer, wherein the lower side of the first drift layer is connected to the upper side of the silicon carbide substrate;

[0007] A first low-resistivity region, the lower side of the first low-resistivity region is connected to the upper side of the first drift layer, and the first low-resistivity region is provided with a protrusion;

[0008] The second low-resistivity region has its lower side connected to the upper side of the first drift layer.

[0009] A first P-type source region, the lower side of which is connected to the second low-resistivity region, and a protrusion is provided on the first P-type source region;

[0010] A P-type well region, wherein the lower side of the P-type well region is connected to the upper side of the protrusion, and an N-type source region is provided within the P-type well region;

[0011] The second P-type source region has its lower side connected to the first low-resistivity region, and its inner side connected to the outer side of the protrusion and the outer side of the P-type well region, respectively.

[0012] The second drift layer has its lower side connected to the second low-resistivity region, and its outer side connected to the inner side of the protrusion, the inner side of the P-type well region, and the inner side of the first P-type source region, respectively.

[0013] An insulating dielectric layer is provided, the lower side of which is connected to the upper side of the first P-type source region and the upper side of the second drift layer, respectively, and the outer side of which is connected to the P-type well region, the N-type source region and the protrusion, respectively; the insulating dielectric layer is provided with trenches.

[0014] A gate metal layer is disposed within the trench;

[0015] A source metal layer, wherein the source metal layer is respectively connected to the first P-type source region, the P-type well region, the N-type source region and the second P-type source region;

[0016] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

[0017] The advantages of this utility model are:

[0018] I. This utility model designs an asymmetric trench gate structure, in which the first P-type source region and the second P-type source region are in direct contact with the source metal layer, which improves the freewheeling capability of the device's body diode and reduces the body diode loss.

[0019] Second, the asymmetric trench gate structure is redesigned so that the first P-type source region extends directly below the trench gate. This extension width does not affect the normal conduction characteristics on the other side of the device, and can also achieve trench gate protection for the device.

[0020] Third, the P-type well region on the gate control side of the device is redesigned. In traditional devices, the bottom of the P-type well region is flush with the bottom of the gate insulating medium to ensure low on-resistance. In this invention, the P-type well region is extended downward. Since a first low-resistance region is designed at the bottom of the P-type well region, it cancels out the P-type well region at the bottom of the gate insulating medium, so it will not affect the conduction characteristics of the device. At the same time, by extending the P-type well region downward, the insulating medium at the gate corner on this side is also protected, improving the reliability of the device.

[0021] Fourth, a second low-resistance region is designed below the redesigned region of the device. The functions of the second low-resistance region are: 1. to redistribute the current from the device when it is normally conducting, thereby reducing the on-resistance of the device; 2. to reduce the freewheeling loss of the body diode of the device. Attached Figure Description

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Figure 1 This is a schematic diagram of an asymmetric trench gate silicon carbide VDMOS according to the present invention.

[0024] Figure 2 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 1 .

[0025] Figure 3 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 2 .

[0026] Figure 4 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 3 .

[0027] Figure 5 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 4 .

[0028] Figure 6 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 5 .

[0029] Figure 7 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 6 .

[0030] Figure 8 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 7 .

[0031] Figure 9 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 8 .

[0032] Figure 10 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 9 .

[0033] Figure 11 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 10 .

[0034] Figure 12 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS according to the present invention. Figure 10 one. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0039] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0040] like Figure 1 As shown, this application embodiment provides an asymmetric trench-gate silicon carbide VDMOS, comprising:

[0041] Silicon carbide substrate 101;

[0042] A first drift layer 102, the lower side of the first drift layer 102 being connected to the upper side of the silicon carbide substrate 101;

[0043] A first low-resistivity region 103, the lower side of the first low-resistivity region 103 is connected to the upper side of the first drift layer 102, and the first low-resistivity region 103 is provided with a protrusion 1031.

[0044] The second low-resistivity region 104 is connected to the upper side of the first drift layer 102.

[0045] A first P-type source region 105 is connected to the second low-resistivity region 104 on its lower side, and a protrusion 1051 is provided on the first P-type source region 105.

[0046] P-type well region 106, the lower side of the P-type well region 106 is connected to the upper side of the protrusion 1031, and an N-type source region 1061 is provided in the P-type well region 106;

[0047] The second P-type source region 107 has its lower side connected to the first low-resistivity region 103, and its inner side is connected to the outer side of the protrusion 1031 and the outer side of the P-type well region 106, respectively.

[0048] The second drift layer 108 has its lower side connected to the second low-resistivity region 104, and its outer side connected to the inner side of the protrusion 1031, the inner side of the P-type well region 106, and the inner side of the first P-type source region 105, respectively.

[0049] An insulating dielectric layer 109 is provided, the lower side of which is connected to the upper side of the first P-type source region 105 and the upper side of the second drift layer 108, respectively, and the outer side of which is connected to the P-type well region 106, the N-type source region 1061 and the protrusion 1051, respectively; a groove 1091 is provided in the insulating dielectric layer 109.

[0050] A gate metal layer 110 is disposed within the trench 1091;

[0051] Source metal layer 111, which is connected to the first P-type source region 105, the P-type well region 106, the N-type source region 1061 and the second P-type source region 107 respectively.

[0052] And a drain metal layer 112, which is connected to the lower side of the silicon carbide substrate 101.

[0053] In this embodiment, preferably, one side of the second drift layer 102, one side of the insulating dielectric layer 109, and one side of the second low-resistivity region 104 are located on the same vertical plane.

[0054] In this embodiment, preferably, the thickness of the first low-resistivity region 103 is equal to the thickness of the second low-resistivity region 104.

[0055] In this embodiment, preferably, the thickness of the second drift layer 108 is equal to the thickness of the second P-type source region 107.

[0056] In this embodiment, preferably, the thickness of the second drift layer 108 is greater than the thickness of the protrusion 1031.

[0057] In this embodiment, preferably, the sum of the thicknesses of the first P-type source region 105 and the protrusion 1051 is equal to the thickness of the second P-type source region 107.

[0058] In this embodiment, preferably, the doping concentration of the first low-resistivity region 103 is less than the doping concentration of the second low-resistivity region 104.

[0059] In this embodiment, preferably, the doping concentration of the first P-type source region 105 is equal to the doping concentration of the second P-type source region 107, and the doping concentration of the first P-type source region 105 is greater than the doping concentration of the second low-resistivity region 104.

[0060] like Figures 1 to 12 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:

[0061] Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 112; epitaxially grow on the upper side of silicon carbide substrate 101 to form drift region 113;

[0062] Step 2: Form a barrier layer 114 on the drift region 113, etch the barrier layer 114 to form a via, and perform ion implantation into the drift region 113 to form a second low-resistivity region 104.

[0063] Step 3: Remove the barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via, and perform ion implantation into the drift region 113 to form the first low-resistivity region 103, the first drift layer 102, and the second drift layer 108.

[0064] Step 4: Remove the barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via, and perform ion implantation into the second drift layer 108 and the first low-resistivity region 103 to form the first P-type source region 105 and the second P-type source region 107, respectively.

[0065] Step 5: Remove the barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via, and implant ions into the second drift layer 108 to form a P-type well region 106.

[0066] Step 6: Remove the barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via, and implant ions into the P-type well region 106 to form the N-type source region 1061.

[0067] Step 7: Remove the original barrier layer 114, re-form the barrier layer 114, etch the barrier layer 114 to form a through hole, and etch the second drift layer 108 and the first P-type source region 105. A protrusion 1051 is formed on the first P-type source region 105, and then oxidize to form an insulating dielectric layer 109. The insulating dielectric layer 109 has a trench 1091 inside.

[0068] Step 8: Remove the original barrier layer 114, re-form the barrier layer 114, etch the barrier layer to form a via, deposit metal, and form the gate metal layer 110.

[0069] Step 9: Remove the original barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via, etch the second drift layer 108, deposit metal to form the source metal layer 111, remove the barrier layer 114, and complete the fabrication.

[0070] In another embodiment, the silicon carbide substrate 101, the first drift layer 102, the second drift layer 108, the first low-resistivity region 103, and the second low-resistivity region 104 are all N-type; the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of the N-type first drift layer 102 and the second drift layer 108 is 1-5e16cm. -3 The doping concentration of the first low-resistivity region 103 is 1-5e17cm. -3 The doping concentration of the second low-resistivity region 104 is 1-2e18cm. -3 The doping concentration of the first P-type source region 105 and the second P-type source region 107 is 1-2e19cm. -3 The doping concentration of the P-type well region 106 is 1-5e17cm. -3 The insulating dielectric layer 109 is silicon dioxide, and the doping concentration of the N-type source region 1061 is 2-8e18cm. -3The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 112, thereby reducing the overall on-resistance of the device. The doping concentration of the N-type first drift layer 102 and the second drift layer 108 represents a trade-off between the reverse breakdown voltage and on-resistance of the device. The doping concentration design of the first low-resistance region 103 and the second low-resistance region 104 has two considerations: to achieve current equalization within the device and to reduce the on-resistance of the device. This requires ensuring a high doping concentration. The first low-resistance region 103 must be adjacent to the bottom of the P-type well region 106. The space charge region is formed to ensure the reliability of the device gate corner and does not affect the normal on-resistance of the device when it is turned on. The doping concentration of the second low-resistance region 104 is higher than that of the first low-resistance region 103 because the distance on the right side of the device is larger, which better realizes the internal current sharing of the device. The second low-resistance region 104 also forms a low-resistance body diode region with the first P-type source region 105 to reduce the freewheeling loss of the device body diode. The relatively low doping of the P-type well region 106 can reduce the inversion voltage of the device gate, thereby reducing the driving loss of the device.

[0071] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm. The thickness of the first drift layer 102 is 30-100 μm, which is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the first low-resistivity region 103 and the second low-resistivity region 104 is 500-800 nm. The thickness of the protrusion 1031 is 300 nm. The thickness of the P-type well region 106 is 800 nm. The thickness of the N-type source region 1061 is 300 nm. The P-type well region 106 extends downward 300 nm from the bottom of the insulating dielectric layer 109. This is a design that combines with the doping concentration of the first low-resistivity region 103 to form a space charge region. The space charge region extends upward 300 nm from the P-type well region. The thickness of the first P-type source region 105 is 600 nm. The thickness of the protrusion 1051 is 500 nm. The thickness of the source metal layer 111 is 300 nm. The thickness of the insulating dielectric layer is 50 nm. The thickness of the gate metal layer 110 is 750 nm.

[0072] This invention designs an asymmetric trench gate structure, in which the first P-type source region 105 and the second P-type source region 107 are in direct contact with the source metal layer 111, which improves the body diode freewheeling capability and reduces the body diode loss. The asymmetric trench gate structure extends a portion of the redesigned first P-type source region 105 directly below the trench gate. This extension width does not affect the normal conduction characteristics on the other side of the device, and can also achieve trench gate protection for the device.

[0073] The P-type well region 106 on the gate control side of the device is redesigned. The P-type well region 106 is extended downward. Since a first low-resistance region 103 is designed at the bottom of the P-type well region 106, it cancels out the P-type well region 106 at the bottom of the insulating dielectric layer 109, so it will not affect the conduction characteristics of the device. At the same time, by extending the P-type well region 106 downward, the insulating dielectric layer 109 at the gate corner on this side is also protected, improving the reliability of the device.

[0074] A second low-resistance region 104 is designed below the redesigned region of the device. The functions of the second low-resistance region 104 are: first, to redistribute the current from the device when it is normally turned on, thereby reducing the on-resistance of the device; and second, to reduce the freewheeling loss of the body diode of the device.

[0075] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An asymmetric trench gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate; A first drift layer, wherein the lower side of the first drift layer is connected to the upper side of the silicon carbide substrate; A first low-resistivity region, the lower side of the first low-resistivity region is connected to the upper side of the first drift layer, and the first low-resistivity region is provided with a protrusion; The second low-resistivity region has its lower side connected to the upper side of the first drift layer. A first P-type source region, the lower side of which is connected to the second low-resistivity region, and a protrusion is provided on the first P-type source region; A P-type well region, wherein the lower side of the P-type well region is connected to the upper side of the protrusion, and an N-type source region is provided within the P-type well region; The second P-type source region has its lower side connected to the first low-resistivity region, and its inner side connected to the outer side of the protrusion and the outer side of the P-type well region, respectively. The second drift layer has its lower side connected to the second low-resistivity region, and its outer side connected to the inner side of the protrusion, the inner side of the P-type well region, and the inner side of the first P-type source region, respectively. An insulating dielectric layer is provided, the lower side of which is connected to the upper side of the first P-type source region and the upper side of the second drift layer, respectively, and the outer side of which is connected to the P-type well region, the N-type source region and the protrusion, respectively; the insulating dielectric layer is provided with trenches. A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is respectively connected to the first P-type source region, the P-type well region, the N-type source region and the second P-type source region; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

2. The asymmetric trench gate silicon carbide VDMOS of claim 1, wherein: One side of the second drift layer, one side of the insulating dielectric layer, and one side of the second low-resistivity region are located on the same vertical plane.

3. The asymmetric trench gate silicon carbide VDMOS of claim 1, wherein: The thickness of the first low-resistivity region is equal to the thickness of the second low-resistivity region.

4. An asymmetric trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the second drift layer is equal to the thickness of the second P-type source region.

5. An asymmetric trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the second drift layer is greater than the thickness of the protrusion.

6. An asymmetric trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The sum of the thicknesses of the first P-type source region and the protrusion is equal to the thickness of the second P-type source region.

7. An asymmetric trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the first low-resistivity region is less than that of the second low-resistivity region.

8. An asymmetric trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the first P-type source region is equal to the doping concentration of the second P-type source region, and the doping concentration of the first P-type source region is greater than the doping concentration of the second low-resistivity region.

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