Semiconductor chip and semiconductor packaging structure
By utilizing the material and thickness differences of existing film structures in semiconductor chips to enhance the contrast of alignment marks, the problems of inaccurate measurement and high cost in COG packaging are solved, achieving higher precision alignment and lower cost packaging.
Patent Information
- Application Number
- CN202423194764.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2034-12-24
AI Technical Summary
The inaccurate measurement and high manufacturing cost of alignment marks in existing COG packaging technology are mainly due to the increased cost of additional photomasks and the unclear display of alignment marks caused by material differences.
By introducing alignment marks with special structures into semiconductor chips, the material and thickness differences in existing film structures are utilized to enhance the contrast of alignment patterns through reflectivity differences, reduce the measurement error of alignment marks, and combine photomasks to reduce costs.
This improves the measurement and positioning accuracy of alignment marks while reducing chip manufacturing costs.
Smart Images
Figure CN223829829U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor lithography technology, and in particular to a semiconductor chip and semiconductor packaging structure. Background Technology
[0002] After the semiconductor silicon wafer process is completed, individual chips need to be assembled and packaged. In the traditional industrial display field, the mainstream packaging technology is still chip-on-glass (COG) packaging. COG packaging technology involves packaging chips, such as driver chips, onto liquid crystal glass, and interconnecting them with transparent conductive pads on the liquid crystal glass through conductive bumps on the driver chip, thus enabling the screen to light up.
[0003] Currently, when performing COG packaging on chips, alignment marks are usually required to avoid misalignment. However, for precise positioning, an additional alignment mark mask is needed during chip manufacturing. This inevitably increases packaging costs and causes problems such as inaccurate measurement of alignment marks due to the different materials at different positions of the existing alignment marks. Utility Model Content
[0004] The purpose of this invention is to provide a semiconductor chip and semiconductor packaging structure, which proposes a novel structure for alignment marks, thereby improving the measurement accuracy of alignment marks and reducing chip manufacturing costs.
[0005] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a semiconductor chip, which may include at least: a substrate.
[0006] Alignment markings, including a first marking pattern and a second marking pattern surrounding it.
[0007] The first marking pattern includes a barrier layer, a first insulating layer and a second insulating layer stacked from bottom to top, and the second marking pattern includes a third insulating layer and a fourth insulating layer stacked from bottom to top. The third insulating layer and the first insulating layer are made of the same material, and the fourth insulating layer and the second insulating layer are made of the same material.
[0008] In some optional examples, the semiconductor chip may further include:
[0009] The Nth top-level interconnect is located between the substrate and the alignment mark, and the material of the Nth top-level interconnect includes at least one of aluminum or copper.
[0010] In some of the alternative examples, the projection shape of the first marking pattern on the surface of the substrate may include at least one of a cross or a square.
[0011] In some of the alternative examples, the material of the barrier layer may include at least one of titanium nitride or metallic titanium.
[0012] In some alternative examples, the first insulating layer and the second insulating layer are made of different materials; the first insulating layer may be made of silicon dioxide, and the second insulating layer may be made of silicon oxynitride or silicon nitride.
[0013] In some alternative examples, the top surfaces of the first insulating layer and the third insulating layer may be at the same horizontal level, and the top surfaces of the second insulating layer and the fourth insulating layer may be at the same horizontal level.
[0014] In some alternative examples, the thickness of the first insulating layer may be greater than the thickness of the second insulating layer.
[0015] In some alternative examples, the second marking pattern may further include: a plurality of metal wire layers, arranged horizontally spaced apart within the third insulating layer.
[0016] Multiple anti-reflective layers are respectively disposed on the metal wire layer.
[0017] In some optional examples, the semiconductor chip may further include:
[0018] The circuit area is located on one side of the alignment mark.
[0019] Secondly, based on the same concept, the present invention also provides a semiconductor packaging structure, which may include at least: a transparent substrate.
[0020] A semiconductor chip, including a circuit region and at least one alignment mark located on its outer side, the alignment mark including a first mark pattern and a second mark pattern surrounding its outer side.
[0021] The first marking pattern includes a barrier layer, a first insulating layer and a second insulating layer stacked from bottom to top, and the second marking pattern includes a third insulating layer and a fourth insulating layer stacked from bottom to top. The third insulating layer and the first insulating layer are made of the same material, and the fourth insulating layer and the second insulating layer are made of the same material.
[0022] Compared with the prior art, the present invention has at least the following technical effects:
[0023] As described above, this utility model provides a semiconductor chip and specifically provides an alignment mark with a unique film layer structure design. Specifically, the alignment mark includes a first marking pattern and a second marking pattern surrounding it. The first marking pattern includes a barrier layer, a first insulating layer, and a second insulating layer stacked from bottom to top. The second marking pattern includes a third insulating layer and a fourth insulating layer stacked from bottom to top. The third insulating layer and the first insulating layer are made of the same material, and the fourth insulating layer and the second insulating layer are made of the same material. An unexpected effect is achieved: on the one hand, by utilizing existing film layer structures in the semiconductor chip, such as metal interconnects... The difference in reflectivity of the detection light by the multilayer material layers with different materials and / or thicknesses on the Nth top interconnect in the structure allows the first and second alignment patterns of the alignment mark to be placed in different film layer structures. By utilizing the difference in reflectivity of the detection light by the different film layer materials and / or thicknesses of the first and second alignment patterns, the contrast of the different alignment patterns of the alignment mark on the semiconductor chip is enhanced, thereby improving the measurement progress and positioning accuracy of the alignment mark. On the other hand, by placing the alignment mark on the mask corresponding to the existing film layer structure on the semiconductor chip, one mask is saved, thereby reducing the chip manufacturing cost. Attached Figure Description
[0024] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:
[0025] Figure 1 This is a plan view of one structure of the alignment mark in this utility model.
[0026] Figure 2 This is a plan view of an evolved structure of the alignment mark in this utility model.
[0027] Figure 3 This is a plan view of an evolved structure of the alignment mark in this utility model.
[0028] Figure 4 This is a plan view of another structure of the alignment mark in this utility model.
[0029] Figure 5 for Figure 1 The alignment mark shown is a partial cross-sectional view along the tangent line AA.
[0030] The attached figures are labeled as follows:
[0031] 10 - Nth top layer interconnect, 20 - Alignment mark, 21 - First alignment pattern, 22 - Second alignment pattern, 211 - Barrier layer, 212 - First insulating layer, 213 - Second insulating layer, 221 - Third insulating layer, 222 - Fourth insulating layer, 2211 - Metal wire layer, 2212 - Anti-reflective layer.
[0032] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0033] The following specific embodiments illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.
[0034] It should be noted that the illustrations provided in this embodiment are merely schematic representations of the basic structure of this utility model. That is, the illustrations only show components relevant to this utility model and are not drawn according to the actual number, state, and size of components in implementation. In actual implementation, the type, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. Therefore, the following description should be understood as being common knowledge to those skilled in the art and is not intended to limit this utility model.
[0035] In the description of this utility model, it should be noted that the terms "center", "middle", "outer periphery", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device, graphic, material layer or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0036] As described in the background section, liquid crystal displays (LCDs) are typically driven by driver chips. Some of these chips are precisely bonded to corresponding positions on a transparent substrate using a high-temperature, high-pressure lamination process to achieve COG (Chip-on-Glass) packaging. To avoid misalignment, an alignment process is usually performed before lamination. This alignment is achieved using corresponding components or parts on the driver chip and the transparent substrate, such as alignment marks. After alignment, lamination proceeds. However, mechanical or human errors are inevitable during the lamination process, resulting in misalignment or offset. Therefore, it is necessary to observe the offset and readjust the equipment.
[0037] Currently, the traditional method for detecting and evaluating the misalignment between the transparent substrate and the driver chip in COG packaging is to directly observe the position of the driver chip on the alignment marks relative to the transparent substrate after lamination using a microscope. Although the first alignment mark on the driver chip and the second alignment mark on the substrate have a fixed length and width, if the driver chip is misaligned after lamination, the two alignment marks are not completely sealed. Therefore, when misalignment occurs, the misalignment can be estimated based on the difference between the actual and expected sealing degree between the two alignment marks. However, existing technologies require an additional separate photomask (or mask) to form the alignment marks on the driver chip, which inevitably increases the cost of chip manufacturing. Furthermore, the material of the film layer formed by the alignment marks in existing technologies can cause the alignment marks to be unclear, leading to inaccurate measurements or even the inability to measure.
[0038] To address this, the present invention proposes a special alignment mark structure located on a driver chip. By leveraging the different reflectivity or brightness of reflected light in different materials and / or materials of different thicknesses, the alignment mark is placed in different film structures within the existing film structure of the driver chip (i.e., the semiconductor chip), such as the Nth top interconnect in a metal interconnect structure. Furthermore, by utilizing the differences in reflectivity of the detection light caused by the different film materials and / or thicknesses of the different alignment patterns in the alignment mark, the contrast of different alignment patterns on the semiconductor chip is enhanced, the measurement progress and positioning accuracy of the alignment mark are improved, and the chip manufacturing cost is reduced.
[0039] Please refer to Figures 1-4 , Figures 1-4 This is a plan view of various structures of the alignment mark in this utility model. For example... Figures 1-4 As shown, the structure of one or more alignment marks 20 located outside the circuit area of the driver chip (referred to as a semiconductor chip in this invention) provided in this invention may specifically include a first mark pattern 21 and a second mark pattern 22 located outside thereon.
[0040] In one embodiment, the first marking pattern 21 and the second marking pattern 22 of the alignment mark 20 can be arranged in direct contact, for example, the second marking pattern 22 surrounds the outside of the first marking pattern 21, such as... Figure 1 As shown; furthermore, the first marking pattern 21 and the second marking pattern 22 of the alignment mark 20 can also be set in a way that does not directly contact each other, for example, the second marking pattern 22 is independent of the first marking pattern 21 and is located on the outside of one corner or the outside of the whole, such as Figure 2 or Figure 3 As shown; of course, the first mark pattern 21 and the second mark pattern 22 of the alignment mark 20 can also be set in any other irregular manner, such as Figure 4 The examples shown are not intended to limit the scope of this invention. It should be understood that this invention only exemplarily demonstrates four structures for alignment marks, and any structure containing at least two patterns that can be used for measurement is within the scope of protection of the structural examples of alignment marks of this invention.
[0041] The following will be through Figure 1 The structure of the alignment mark shown is an example, and the structure of the special alignment mark proposed in this utility model will be described in detail.
[0042] It should be noted that the alignment mark 20 described in this utility model is specifically formed on the driver chip in the COG packaging process, and the number of alignment marks 10 can be 1, 2, 3, 4, etc., which can be set according to actual needs. The alignment mark 10 is usually located in the area outside the circuit area of the driver chip, such as the edge of the driver chip, but is not limited thereto.
[0043] Please refer to Figure 5 , Figure 5 for Figure 1 The partial cross-sectional view shown is along the tangent of alignment mark 20. (See figure) Figure 5 As shown, the first marking pattern 21 in the alignment mark 20 of this utility model may include a barrier layer 211, a first insulating layer 212 and a second insulating layer 213 stacked sequentially from bottom to top, while the second marking pattern 22 includes a third insulating layer 221 and a fourth insulating layer 222 stacked sequentially from bottom to top.
[0044] In one embodiment, the material of the barrier layer 211 may include at least one of titanium nitride or metallic titanium, but metallic titanium is preferred. The materials of the first insulating layer 212 and the third insulating layer 221 may be the same, and are preferably oxides, such as silicon dioxide. The materials of the second insulating layer 213 and the fourth insulating layer 222 may be the same, and are preferably silicon oxynitride, but are not limited thereto. The top surfaces of the first insulating layer 212 and the third insulating layer 221 are at the same horizontal height (flush), and the top surfaces of the second insulating layer 213 and the fourth insulating layer 222 are at the same horizontal height (flush), but are not limited thereto. The thickness of the first insulating layer 212 in the vertical direction may be greater than the thickness of the second insulating layer 213 in the vertical direction, but is not limited thereto.
[0045] In detail, since multiple driving circuit units are arranged in the circuit area of the driver chip, and each component and / or part of each driving unit, such as a transistor, needs to be electrically connected to complete the driving function, a metal interconnect structure for electrically connecting different components and / or parts must be fabricated on the driver chip. The metal interconnect structure may include multiple metal interconnects (hereinafter referred to as interconnects), such as a first layer interconnect, a second layer interconnect, ..., the (N-1)th top layer interconnect and the Nth top layer interconnect, where N≥1; wherein, the material of each layer interconnect can be at least one of copper, aluminum or other conductive materials; and, between adjacent interconnects and on the Nth top layer interconnect, a material layer of titanium or titanium nitride is formed to wrap the interconnect, so as to increase the adhesion between different layers of interconnects. An insulating material such as silicon nitride or silicon oxide is also formed on the titanium or titanium nitride film as an isolation layer between different interconnects.
[0046] It should be understood that, in order to facilitate understanding of the specific film layer position of the alignment mark 20 in the semiconductor chip, the present invention... Figure 5 The corresponding Nth top-level interconnect (e.g., aluminum) is also shown under alignment mark 20, and the Nth top-level interconnect is identified by reference numeral 10.
[0047] Based on this, in this embodiment of the present invention, the alignment mark 20 to be set on the driver chip (hereinafter referred to as the semiconductor chip) can be set in the stacked structure layer of the Nth top interconnect in the metal interconnect structure of the semiconductor chip, that is, in the material layer of titanium or titanium nitride and the insulating material layer of silicon nitride or silicon oxide. The alignment mark 20 is formed by merging the mask corresponding to the alignment mark 20 and the last mask in the formation of the metal interconnect structure of the semiconductor chip, that is, by drawing the mask pattern of the alignment mark 20 on the last mask in the metal interconnect structure. In one embodiment, corresponding components and / or parts can be formed on a substrate on which a semiconductor chip is formed, followed by the formation of corresponding interconnects. After forming the last interconnect layer (i.e., the top interconnect layer), a titanium metal layer and / or a titanium nitride layer are formed. This invention refers to this film layer as a barrier layer. In the area of the titanium metal layer and / or titanium nitride layer used to form the alignment mark 20, a portion is etched away, leaving a residual portion. The residual portion is used as part of the first alignment pattern 21 of the alignment mark 20, i.e., the barrier layer 211. Then, an insulating material is formed that buries the barrier layer 211 and serves as an isolation layer. For example, silicon dioxide. In this configuration, the silicon dioxide in the region where the alignment mark 20 is formed and located on both sides of the barrier layer 211 is called the third insulating layer 221 of the second alignment mark 22, and the silicon dioxide on the barrier layer 211 is called the first insulating layer 212. Then, an insulating material layer, such as silicon oxynitride or silicon nitride, is formed. The portion on the first insulating layer 212 is called the second insulating layer 213 of the first alignment pattern 21, and the portion on the third insulating layer 221 is called the fourth insulating layer 222 of the second alignment pattern 22.
[0048] In this configuration, the film structures of the first alignment pattern 21 and the alignment pattern 22 in the alignment mark 20 of this utility model embodiment are different. Since the film structure of the first alignment pattern 21 includes a film made of titanium metal or titanium nitride, while the film structure of the second alignment pattern 22 does not, when the first alignment pattern 21 is used for laser detection imaging, due to the high reflectivity of the blocking layer 211, the first alignment pattern 21 becomes the bright part of the alignment mark 20, while due to the low reflectivity of the insulating material, the second alignment pattern 22 becomes the dark part of the alignment mark 20. This enhances the contrast of different pattern areas of the alignment mark 20, thereby improving the measurement progress and positioning accuracy of the alignment mark.
[0049] In one embodiment, the thickness ranges of the second insulating layer 213 and the fourth insulating layer 222 are: And preferably The thickness range of the first insulating layer 212 is: Furthermore, when the thickness of the second insulating layer 213 and the fourth insulating layer 222 in the first alignment pattern 21 and the second alignment pattern 22 of the alignment mark 20 are the same, the later the thickness of the first insulating layer 212, the better the contrast between the first alignment pattern 21 and the second alignment pattern 22. Moreover, when the material of the barrier layer 211 is titanium, the contrast between the first alignment pattern 21 and the second alignment pattern 22 is better than when it is titanium nitride. Therefore, the material of the barrier layer 211 is preferably titanium.
[0050] Furthermore, the second marking pattern 22 in this embodiment of the present invention may further include: a plurality of metal wire layers 2211 and a plurality of anti-reflection layers 2212, so as to further reduce the reflectivity of the second marking pattern 22; specifically, the plurality of metal wire layers 2211 may be disposed in the third insulating layer 221 with mutual separation along the horizontal direction, and each of the metal wire layers 2211 has an anti-reflection layer 2212 disposed on its top surface.
[0051] Furthermore, based on the alignment marks described above, this invention also provides a semiconductor packaging structure, which may include at least:
[0052] Transparent substrates, such as glass, are used as support structures for driver chips during the COG packaging process.
[0053] A semiconductor chip, such as a driver chip in a liquid crystal display device, may include a circuit region and at least one alignment mark 20 located outside therefrom, the alignment mark 20 including a first marking pattern 21 and a second marking pattern 22 surrounding therefrom; wherein the first marking pattern 11 includes a barrier layer 211, a first insulating layer 212 and a second insulating layer 213 stacked from bottom to top, the second marking pattern 22 includes a third insulating layer 221 and a fourth insulating layer 224 stacked from bottom to top, the third insulating layer 221 being made of the same material as the first insulating layer 212, and the fourth insulating layer 224 being made of the same material as the second insulating layer 213.
[0054] It should be understood that the methods, steps, and processes involved in this utility model are all existing technologies.
[0055] In summary, the alignment mark in this invention includes a first marking pattern and a second marking pattern surrounding it. The first marking pattern includes a barrier layer, a first insulating layer, and a second insulating layer stacked from bottom to top. The second marking pattern includes a third insulating layer and a fourth insulating layer stacked from bottom to top. The third insulating layer and the first insulating layer are made of the same material, and the fourth insulating layer and the second insulating layer are made of the same material. Unexpectedly, this achieves the following effects: On the one hand, by utilizing the differences in reflectivity of detection light by multiple layers of different materials and / or thicknesses on the Nth top interconnect in a semiconductor chip's existing film structure, such as a metal interconnect structure, the first and second alignment patterns of the alignment mark are placed in different film structures. This enhances the contrast of different alignment patterns on the semiconductor chip by utilizing the differences in reflectivity of the film materials and / or thicknesses of the first and second alignment patterns, thus improving the measurement progress and positioning accuracy of the alignment mark. On the other hand, by placing the alignment mark on a mask corresponding to the existing film structure on the semiconductor chip, a mask is saved, thereby reducing chip manufacturing costs.
[0056] It should be noted that the above description is only a preferred embodiment of this application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the utility model involved in this application does not limit the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the concept of the utility model. For example, technical solutions formed by replacing the above features with (but not limited to) technologies with similar functions disclosed in this application.
[0057] Apart from the technical features described in the specification, the other technical features are known to those skilled in the art. To highlight the innovative features of this utility model, the other technical features will not be repeated here.
Claims
1. A semiconductor chip, characterized in that, include: Base; Alignment markings, including a first marking pattern and a second marking pattern surrounding it; The first marking pattern includes a barrier layer, a first insulating layer and a second insulating layer stacked from bottom to top, and the second marking pattern includes a third insulating layer and a fourth insulating layer stacked from bottom to top. The third insulating layer and the first insulating layer are made of the same material, and the fourth insulating layer and the second insulating layer are made of the same material.
2. The semiconductor chip as described in claim 1, characterized in that, Also includes: The Nth top-level interconnect is located between the substrate and the alignment mark, and the material of the Nth top-level interconnect includes either aluminum or copper.
3. The semiconductor chip as described in claim 1, characterized in that, The projection shape of the first marking pattern on the surface of the substrate includes at least one of a cross shape or a square shape.
4. The semiconductor chip as described in claim 1, characterized in that, The material of the barrier layer includes either titanium nitride or metallic titanium.
5. The semiconductor chip as described in claim 1, characterized in that, The first insulating layer and the second insulating layer are made of different materials. The first insulating layer is made of silicon dioxide, and the second insulating layer is made of either silicon oxynitride or silicon nitride.
6. The semiconductor chip as described in claim 1, characterized in that, The top surfaces of the first insulating layer and the third insulating layer are at the same horizontal height, and the top surfaces of the second insulating layer and the fourth insulating layer are at the same horizontal height.
7. The semiconductor chip as described in claim 6, characterized in that, The thickness of the first insulating layer is greater than the thickness of the second insulating layer.
8. The semiconductor chip as described in claim 1, characterized in that, The second marking pattern further includes: multiple metal wire layers, which are arranged in a horizontally spaced manner within the third insulating layer; Multiple anti-reflective layers are respectively disposed on the metal wire layer.
9. The semiconductor chip as described in claim 1, characterized in that, Also includes: The circuit area is located on one side of the alignment mark.
10. A semiconductor packaging structure, characterized in that, include: Transparent substrate; A semiconductor chip, including a circuit region and at least one alignment mark located on its outer side, the alignment mark including a first mark pattern and a second mark pattern surrounding its outer side; The first marking pattern includes a barrier layer, a first insulating layer and a second insulating layer stacked from bottom to top, and the second marking pattern includes a third insulating layer and a fourth insulating layer stacked from bottom to top. The third insulating layer and the first insulating layer are made of the same material, and the fourth insulating layer and the second insulating layer are made of the same material.