Marking graphic structure
By designing marking pattern structures in integrated circuit manufacturing, including setting marking trenches on the substrate and setting protrusion structures on the epitaxial layer, the problem of difficult measurement of marking patterns when the epitaxial layer is thick has been solved, achieving higher measurement accuracy and ensuring product quality.
Patent Information
- Application Number
- CN202520064581.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-13
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2035-01-13
AI Technical Summary
In integrated circuit manufacturing, when the epitaxial layer is thick, the marking pattern is difficult to display clearly, leading to measurement difficulties and affecting product quality and manufacturing costs.
Design a marking pattern structure, including setting marking trenches on a substrate and setting protrusions on an epitaxial layer to surround the marking pattern, reducing the deformation of the epitaxial layer and ensuring that the marking pattern is clear and measurable.
It improves the measurement accuracy of marking patterns, reduces measurement errors, ensures product quality and the accuracy of overlay measurement, reduces the number of rework operations, and lowers manufacturing costs.
Smart Images
Figure CN223829830U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a marker pattern structure. Background Technology
[0002] In integrated circuit manufacturing, to obtain high-frequency, high-power transistors, a high-resistivity epitaxial layer needs to be grown on a substrate with extremely low resistivity. Transistors and other devices are fabricated on this epitaxial layer, which ensures high breakdown voltage. This also requires the epitaxial layer to have a certain thickness. However, in actual processes, when the epitaxial layer is thick, it is difficult to display clear markings, making the markings on the epitaxial layer difficult to measure. Utility Model Content
[0003] Therefore, it is necessary to provide a marker pattern structure to address the problem that marker patterns on epitaxial layers are difficult to measure in existing technologies.
[0004] To achieve the above objectives, on the one hand, a marker graphic structure is provided, including:
[0005] A substrate having a marking pattern including marking grooves, the marking pattern having a first marking portion and a second marking portion, the first marking portion extending along a first direction, the second marking portion being connected to opposite sides of the first marking portion along a second direction, the first direction intersecting the second direction;
[0006] An epitaxial layer is located on one side of the substrate, the epitaxial layer fills the marking pattern and covers the upper surface of the substrate.
[0007] In one embodiment, the second marking portion is symmetrically distributed based on the first marking portion.
[0008] In one embodiment, the marker graphic is a centrally symmetric graphic.
[0009] In one embodiment, the first marking portion is square-ring shaped, and the second marking portion is rectangular.
[0010] In one embodiment, the substrate has a plurality of marking patterns arranged along the second direction.
[0011] The aforementioned marking pattern structure, wherein the second marking portion is connected to the two opposite sides of the first marking portion along the second direction, reduces the deformation of the epitaxial layer covering the second marking portion, thereby improving the measurement accuracy of the marking pattern. Furthermore, the width of the first marking portion can be relatively wide, further reducing the deformation of the epitaxial layer covering the first marking portion, resulting in a more uniform pattern on the surface of the epitaxial layer away from the substrate, and reducing the measurement error of the marking pattern.
[0012] On the other hand, a marker graph structure is also provided, including:
[0013] A substrate having a marking pattern;
[0014] A raised structure is located on one side of the substrate and surrounds the marking pattern, the raised structure protruding along the thickness direction of the substrate;
[0015] An epitaxial layer is located on the side of the protrusion structure away from the substrate. The epitaxial layer covers the protrusion structure and the substrate, and the surface of the epitaxial layer away from the substrate has a protrusion, which is disposed opposite to the protrusion structure.
[0016] In one embodiment, the marking pattern includes a filling structure, and the orthographic projection of the raised structure on the substrate overlaps with the orthographic projection of the marking pattern on the substrate.
[0017] In one embodiment, the marker graphic structure includes:
[0018] A dielectric layer, comprising the raised structure and the filling structure, the dielectric layer further covering the substrate upper surface between adjacent filling structures, and the dielectric layer located on the substrate upper surface between adjacent filling structures being lower than the raised structure.
[0019] In one embodiment, the marking pattern includes marking grooves, and the orthographic projection of the protrusion structure on the substrate does not overlap with the orthographic projection of the opening of the marking groove on the substrate.
[0020] In one embodiment, the material of the protrusion structure includes silicon dioxide.
[0021] In the aforementioned marking pattern structure, a raised structure is provided around the marking pattern, thereby creating a raised portion opposite to the raised structure on the surface of the epitaxial layer away from the substrate. This raised portion can have a clear morphology and a small deformation. Therefore, by measuring this raised portion, the possibility of measurement failure is reduced, the measurement accuracy of overlay measurement is improved, and the quality of the final product is ensured. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of a substrate used in related technologies;
[0024] Figure 2 This is a schematic diagram of the epitaxial layer cross-section in the related technology;
[0025] Figure 3 This refers to an epitaxial layer image in related technologies;
[0026] Figure 4 This is a side view of the epitaxial layer signal in the related technology;
[0027] Figure 5 This is another epitaxial layer image in the related technology;
[0028] Figure 6 This is another epitaxial layer image in related technologies;
[0029] Figure 7 This is a schematic diagram of a marker image provided in one embodiment;
[0030] Figure 8 This is a schematic diagram of a labeled image in related technologies;
[0031] Figure 9 An epitaxial layer image provided in one embodiment;
[0032] Figure 10 This is a schematic diagram of a protrusion structure provided in one embodiment;
[0033] Figure 11 This is a schematic diagram of a protrusion provided in one embodiment;
[0034] Figure 12 An image of a protrusion provided in one embodiment;
[0035] Figure 13 This is a flowchart of an epitaxial layer growth method provided in one embodiment;
[0036] Figure 14 This is a schematic diagram of a protrusion provided in another embodiment.
[0037] Explanation of reference numerals in the attached drawings: First marking portion - 110; Second marking portion - 111; Substrate - 20; Dielectric layer - 21; Protrusion structure - 211; Filling structure - 212; Epitaxial layer - 22; Protrusion portion - 221.
[0038] To better describe and illustrate embodiments and / or examples of the utility models disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed utility models, the currently described embodiments and / or examples, or the best mode of these utility models as currently understood. Detailed Implementation
[0039] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0041] In each embodiment, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in each embodiment according to the specific circumstances.
[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this embodiment, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion.
[0043] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0044] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0045] Embodiments of this specification are described herein with reference to cross-sectional views that serve as schematic representations of ideal embodiments (and intermediate structures). Variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of this specification should not be limited to the specific shapes of the regions shown herein, but should include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of embodiments of this specification.
[0046] As mentioned in the background section, in actual processes, when the epitaxial layer is thick, it is difficult to display clear marking patterns on the epitaxial layer, making the marking patterns on the epitaxial layer difficult to measure. Please refer to... Figure 1 and Figure 2 A marking pattern 11 is provided on a substrate 10. Then, an epitaxial layer 12 is formed to cover the substrate 10 and fill the marking pattern 11. At this time, the epitaxial layer 12 is relatively thick, making it difficult for the upper surface of the epitaxial layer 12, away from the substrate 10, to display a pattern corresponding to the marking pattern 11. Furthermore, the inventors discovered that when the epitaxial layer is thick, the marking outline on the epitaxial layer deforms. Please refer to... Figure 3 and Figure 4 , Figure 3 The marked contour of the epitaxial layer obtained in related technologies. Figure 4 This is a signal test diagram of the marked contour. Figure 4 The signal was cluttered and contained two consecutive peaks and troughs, making it difficult for the inventors to obtain the signal. Figure 3 Information about the marked outline is shown. Additionally, please refer to... Figure 5 , Figure 5 The image shows the marker outline of another epitaxial layer obtained in the related technology. The widths of points A, B, and C in this structure are not the same, with point B being narrower and points A and C being wider. This indicates... Figure 5 The outline of the epitaxial layer shown is deformed. Also, please refer to... Figure 6 , Figure 6 for Figure 5 The cross-sectional view of the marked outline shown is in Figure 6 In this case, the marking outline is difficult to display the required shape (as shown by the green line). It is understandable that when the marking outline on the epitaxial layer is difficult to measure or is not accurately overlaid, the epitaxial layer fabrication process requires multiple reworks, which not only increases the fabrication cost of the semiconductor structure but also affects product quality.
[0047] Based on this, in one embodiment, please refer to Figure 7 A marking pattern structure is provided. The marking pattern structure includes a substrate, a marking pattern located in the substrate, and an epitaxial layer.
[0048] In one possible example, the substrate can be made of a semiconductor material, an insulating material, or any combination thereof. For example, the substrate can be such as a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Furthermore, in another possible example, the substrate can have a low resistivity. In this case, ions can be doped into the substrate. This embodiment does not limit the type, material, or resistivity of the substrate.
[0049] The substrate may have marking patterns, including marking trenches. As an example, the marking trenches may extend into the interior of the substrate. Furthermore, the marking patterns may be located at the edges or corners of the substrate for measuring overlay errors, etc.
[0050] For details, please refer to Figure 7 The marking graphic may have a first marking portion 110 and a second marking portion 111. The first marking portion 110 may extend along a first direction (such as the Y direction), and the second marking portion 111 may be connected to opposite sides of the first marking portion 110 along a second direction (such as the X direction). The first direction and the second direction may intersect. As an example, the first direction and the second direction may be perpendicular.
[0051] In one possible example, the first marking portion 110 may be in the shape of a square ring, and the second marking portion 111 may be in the shape of a rectangle. Furthermore, the first marking portion 110 and the second marking portion 111 may also have other shapes. For example, the first marking portion 110 may be in the shape of a ring, and the second marking portion 111 may be in the shape of an arc, etc. This embodiment does not limit the width of the first marking portion 110, nor does it limit the length or width of the second marking portion 111.
[0052] In another possible example, the second marking portion 111 may be symmetrically distributed based on the first marking portion 110. For example, the second marking portion 111 may be located in the middle of the first marking portion 110, or the second marking portion 111 may be located at the top or bottom of the first marking portion 110. When the second marking portion 111 is located in the middle of the first marking portion 110, the marking pattern may be a centrally symmetrical pattern.
[0053] In yet another possible example, the substrate may have multiple marker patterns arranged along a second direction. As an example, each row may have 6 or 10 marker patterns. Furthermore, the multiple marker patterns may be arranged in other ways. This embodiment does not limit the number of marker patterns or their arrangement.
[0054] The marking pattern may include marking trenches, in which case the marking pattern within the substrate can be formed by dry etching. For example, dry etching may include at least one of reactive ion etching, inductively coupled plasma etching, or high-concentration plasma etching. Correspondingly, a pattern corresponding to the marking pattern may also be provided on the mask.
[0055] The epitaxial layer can be located on one side of the substrate. The epitaxial layer can fill the marking pattern (marking trench) and cover the upper surface of the substrate. In this case, the surface of the epitaxial layer facing away from the substrate can display a pattern corresponding to the marking pattern provided in this embodiment. This embodiment does not limit the thickness of the epitaxial layer.
[0056] In related technologies, marked graphics, such as Figure 8 As shown. Formed on the substrate as shown. Figure 8 After the trenches of the marked pattern shown, an epitaxial layer needs to be used to fill the trenches. At this time, the upper surface of the epitaxial layer away from the substrate is as follows: Figure 5 and Figure 6 As shown, the deformation of this structure is relatively large.
[0057] In this embodiment, by setting the marking pattern including a second marking portion 111 connected to the opposite sides of the first marking portion 110 along a second direction, the deformation of the epitaxial layer covering the second marking portion 111 is reduced, thereby improving the measurement accuracy of the marking pattern. Furthermore, in this embodiment, the width of the first marking portion 110 can be relatively wide, further reducing the deformation of the epitaxial layer covering the first marking portion 110, resulting in a more uniform pattern on the surface of the epitaxial layer away from the substrate, thereby obtaining a clear marking outline and reducing the measurement error of the marking pattern.
[0058] For details, please refer to Figure 9 , Figure 9 The structure shown is the upper surface of the epitaxial layer away from the substrate after using the marking pattern provided in this embodiment. Figure 9 The structure corresponding to the marked graphic can be clearly observed in the image.
[0059] Based on the same concept, in one embodiment, please refer to Figure 10 and Figure 11 Alternatively, a marking pattern structure is provided. The marking pattern structure includes a substrate 20, a protrusion structure 211, and an epitaxial layer 22.
[0060] In one possible example, substrate 20 may be constructed of semiconductor materials, insulating materials, or any combination thereof. For example, substrate 20 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Further, in another possible example, substrate 20 may have a low resistivity. In this case, ions may be doped within substrate 20. This embodiment does not limit the type, material, or resistivity of substrate 20.
[0061] The substrate 20 may have a marking pattern. In this case, the marking pattern may be the marking pattern structure provided in the previous embodiment, or it may only have the first marking portion 110 or the second marking portion 111, or it may be other patterns. This embodiment does not limit the specific form of the marking pattern.
[0062] The protrusion structure 211 may be located on one side of the substrate 20 and surround the marking pattern. As an example, the protrusion structure 211 may be located on opposite sides of the marking pattern or may surround the marking pattern. The protrusion structure 211 protrudes along the thickness direction of the substrate 20. This embodiment does not limit the specific height of the protrusion structure 211. The material of the protrusion structure 211 may include an insulating material, thereby ensuring that devices such as transistors have a high breakdown voltage. For example, the material of the protrusion structure 211 may include silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.
[0063] The epitaxial layer 22 may be located on the side of the protrusion structure 211 away from the substrate 20. The epitaxial layer 22 covers the protrusion structure 211 and the substrate 20, and the surface of the epitaxial layer 22 away from the substrate 20 has a protrusion 221, which is disposed opposite to the protrusion structure 211. As an example, when the protrusion structure 211 surrounds the marking pattern, the protrusion 221 may also be annular.
[0064] In this embodiment, by setting a protrusion structure 211 around the marking pattern, the surface of the epitaxial layer 22 away from the substrate 20 can have a clear protrusion 221, reducing the probability of measurement failure. Subsequently, the overlay deviation information of the epitaxial layer 22 can be obtained by measuring this protrusion 221.
[0065] For details, please refer to Figure 12 , Figure 12 The structure shown is a cross-sectional view of the epitaxial layer 22 after using the protrusion structure 211 provided in this embodiment. In this figure, it can be clearly seen that the upper surface of the epitaxial layer 22 has a clear protrusion 221.
[0066] Accordingly, please refer to Figure 13 A method for growing an epitaxial layer is provided, the method for growing an epitaxial layer may include:
[0067] Step S100: Provide a substrate 20 having a marking pattern, the marking pattern including marking trenches.
[0068] Step S200: Form a raised structure 211 around the marking groove.
[0069] Step S300: An epitaxial layer 22 is formed covering the protrusion structure 211 and the upper surface of the substrate 20. The surface of the epitaxial layer 22 away from the substrate 20 has a protrusion 221, which is disposed opposite to the protrusion structure 211.
[0070] In one possible example, please see Figure 10 Step S200 may include:
[0071] Step S210: Form a dielectric material layer covering the marking trench and the upper surface of the substrate 20.
[0072] Step S221: The dielectric material layer is patterned to form a raised structure 211, the dielectric material layer that fills the marked grooves forms a filled structure 212, and the remaining dielectric material layer forms a dielectric layer 21.
[0073] In step S210, the dielectric material layer can be formed using a deposition process. The deposition process can include, but is not limited to, one or more of the following: chemical vapor deposition, atomic layer deposition, high-density plasma deposition, plasma-enhanced deposition, and spin-coating of the dielectric layer. At this time, the dielectric material layer can be formed over the entire surface; that is, the dielectric material layer can fill the marking trenches and also cover the upper surface of the substrate 20.
[0074] In step S221, the dielectric material layer can be etched to form a protrusion structure 211. Simultaneously, the dielectric material layer located within the marking trench can be retained to form a filling structure 212. The etched dielectric material layer can be formed by dry etching. For example, dry etching can include at least one of reactive ion etching, inductively coupled plasma etching, or high-concentration plasma etching.
[0075] At this time, the orthographic projection of the protrusion 211 on the substrate 20 may overlap with the orthographic projection of the marking pattern on the substrate 20. Specifically, the sidewall of the protrusion 211 away from the marking pattern may be flush with the sidewall of the marking pattern. Correspondingly, the sidewall of the protrusion 221 away from the sidewall of the marking pattern may be visible.
[0076] In another possible example, see Figure 14 Step S200 may include:
[0077] Step S220: Form a dielectric material layer covering the marking trench and the upper surface of the substrate 20.
[0078] Step S221: Pattern the dielectric material layer to form a raised structure 211, and remove the dielectric material layer located in the marked trench and the dielectric material layer on the upper surface of the substrate 20.
[0079] In steps S220 to S221, only the protrusion structure 211 may be retained. Subsequently, when forming the epitaxial layer 22, a recessed area may appear between the protrusions 221 of the epitaxial layer 22, which may correspond to the marking groove.
[0080] As an example, the orthographic projection of the protrusion 211 onto the substrate 20 does not overlap with the orthographic projection of the opening of the marking trench onto the substrate 20. In this case, the protrusion 211 facing the sidewall of the marking trench can be flush with the sidewall of the marking trench, thereby ensuring the integrity of the morphology of the protrusion 211.
[0081] In this embodiment, by setting a raised structure 211 around the marking pattern, a protrusion 221 opposite to the raised structure 211 can be obtained on the surface of the epitaxial layer 22 away from the substrate 20. At this time, the protrusion 221 can have a clear morphology and a small deformation, thus obtaining a clear marking outline. Therefore, this embodiment can reduce the possibility of measurement failure by measuring the protrusion 221, improve the measurement accuracy of overlay measurement, and ensure the quality of the final product.
[0082] It should be understood that, although Figure 13 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 13 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0083] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the phrase "this embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment.
[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0085] The embodiments described above merely illustrate several implementations of the marker graphic structure, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the marker graphic structure, and these all fall within the scope of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims. The above descriptions are merely preferred embodiments of this disclosure and do not limit the patent scope of this disclosure. Any equivalent structural transformations made based on the inventive concept of this disclosure, utilizing the description and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.
Claims
1. A marker graphic structure, characterized in that, include: A substrate having a marking pattern including marking grooves, the marking pattern having a first marking portion and a second marking portion, the first marking portion extending along a first direction, the second marking portion being connected to opposite sides of the first marking portion along a second direction, the first direction intersecting the second direction; An epitaxial layer is located on one side of the substrate, the epitaxial layer fills the marking pattern and covers the upper surface of the substrate.
2. The marking graphic structure according to claim 1, characterized in that, The second marking portion is symmetrically distributed based on the first marking portion.
3. The marking graphic structure according to claim 2, characterized in that, The marked graphic is a centrally symmetrical graphic.
4. The marking graphic structure according to claim 1, characterized in that, The first marking part is in the shape of a square ring, and the second marking part is in the shape of a rectangle.
5. The marking graphic structure according to claim 1, characterized in that, The substrate has a plurality of marking patterns, which are arranged along the second direction.
6. A marker graphic structure, characterized in that, include: A substrate having a marking pattern; A raised structure is located on one side of the substrate and surrounds the marking pattern, the raised structure protruding along the thickness direction of the substrate; An epitaxial layer is located on the side of the protrusion structure away from the substrate. The epitaxial layer covers the protrusion structure and the substrate, and the surface of the epitaxial layer away from the substrate has a protrusion, which is disposed opposite to the protrusion structure.
7. The marking graphic structure according to claim 6, characterized in that, The marking pattern includes a filling structure, and the orthographic projection of the raised structure on the substrate overlaps with the orthographic projection of the marking pattern on the substrate.
8. The marking graphic structure according to claim 7, characterized in that, The marker graphic structure includes: A dielectric layer, comprising the raised structure and the filling structure, the dielectric layer further covering the substrate upper surface between adjacent filling structures, and the dielectric layer located on the substrate upper surface between adjacent filling structures being lower than the raised structure.
9. The marking graphic structure according to claim 6, characterized in that, The marking pattern includes marking grooves, and the orthographic projection of the protrusion structure on the substrate does not overlap with the orthographic projection of the opening of the marking groove on the substrate.
10. The marking graphic structure according to claim 6, characterized in that, The material of the protruding structure includes silicon dioxide.