LED epitaxial structure and LED chip
By employing an N-type temporary substrate and a composite buffer layer in the LED epitaxial structure, combined with N-type and P-type inverted epitaxial structures, the problem of improving the performance of existing LED devices has been solved, achieving higher current expansion capability and photoelectric performance, while reducing manufacturing costs.
Patent Information
- Application Number
- CN202520298614.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-02-24
AI Technical Summary
Existing LED devices have not yet met the higher performance requirements in display technology, especially in terms of resolution and photoelectric performance of micro LED devices, where there is room for improvement.
The structure design employs an N-type temporary substrate and a composite buffer layer, which includes sequentially stacked N-type buffer layer, undoped buffer layer and P-type buffer layer to achieve the transition from N-type material to P-type material. Combining the inverted epitaxial structures of N-type and P-type, a mesa structure with exposed N-type layer is formed, and N-type material with high carrier mobility is used to improve current spread capability.
It reduces the fabrication cost of LED epitaxial structures and chips, reduces lattice defects, improves fabrication quality, enhances current spreading capability and photoelectric performance, strengthens antistatic capability, and improves the overall performance of LED chips.
Smart Images
Figure CN223844171U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor light-emitting diode (ELD) technology, and more specifically, to an LED epitaxial structure and an LED chip. Background Technology
[0002] As a new generation of green lighting energy, LEDs have been widely used in various fields. LED lighting has now completely replaced traditional lighting sources, and LEDs occupy an important position in the display industry, with their market share and application areas continuously expanding. In particular, as the resolution of LED display devices increases, micro-LED devices (such as Mini / MicroLED) have become the new favorite in the display field. Compared with traditional display devices, displays composed of micro-LED devices have advantages such as fast response, high color gamut, high PPI, and low energy consumption. Although LED devices have many advantages, with the gradual development of LED display technology and higher demands, the performance of LED devices still needs further improvement. Utility Model Content
[0003] In view of this, this application provides an LED epitaxial structure and an LED chip, which effectively solves the technical problems existing in the prior art, improves the fabrication quality of the LED epitaxial structure, and improves the performance of the LED chip.
[0004] To achieve the above objectives, the technical solution provided in this application is as follows:
[0005] An LED epitaxial structure, the LED epitaxial structure comprising:
[0006] The N-type temporary substrate, composite buffer layer, P-type etch stop layer, P-type ohmic contact layer, P-type layer, active layer and N-type layer are grown sequentially.
[0007] The composite buffer layer comprises an N-type buffer layer, an undoped buffer layer, and a P-type buffer layer grown sequentially, wherein the N-type buffer layer is located between the N-type temporary substrate and the undoped buffer layer.
[0008] Optionally, the P-type layer includes a P-type current spreading layer and a P-type confinement layer that are grown sequentially, wherein the P-type current spreading layer is located between the P-type ohmic contact layer and the P-type confinement layer.
[0009] Optionally, the N-type layer includes an N-type confinement layer, an N-type ohmic contact layer, and an N-type current spreading layer that are grown sequentially, wherein the N-type confinement layer is located between the active layer and the N-type ohmic contact layer.
[0010] Optionally, the N-type ohmic contact layer is an N-type GaInP ohmic contact layer;
[0011] And / or, the N-type current spreading layer is an N-type AlGaInP current spreading layer.
[0012] Based on the same inventive concept, this application also provides an LED chip, the LED chip comprising:
[0013] Fixed substrate;
[0014] An N-type layer is located on one side of the fixed substrate, and the fixed substrate and the N-type layer are bonded and fixed together. The surface of the N-type layer facing away from the fixed substrate includes a device region and a first electrode region.
[0015] An active layer is located on the side of the N-type layer away from the fixed substrate, and the active layer is located in the device region;
[0016] A P-type layer is located on the side of the active layer away from the N-type layer, and the surface of the P-type layer away from the fixed substrate includes a second electrode region.
[0017] A P-type ohmic contact layer is located on the side of the P-type layer away from the fixed substrate, and the P-type ohmic contact layer is located in the second electrode region;
[0018] An N-type electrode and a P-type electrode, wherein the N-type electrode is located on the side of the N-type layer away from the fixed substrate, and the N-type layer is located in the first electrode region; the P-type electrode is located on the side of the P-type ohmic contact layer away from the fixed substrate, and the P-type electrode is located in the second electrode region.
[0019] Optionally, the P-type layer includes a P-type current spreading layer and a P-type confinement layer that are grown sequentially, wherein the P-type current spreading layer is located between the P-type ohmic contact layer and the P-type confinement layer;
[0020] And / or, the N-type layer includes an N-type confinement layer, an N-type ohmic contact layer and an N-type current spreading layer that are grown sequentially, wherein the N-type confinement layer is located between the active layer and the N-type ohmic contact layer; in the device region, the N-type layer exposes the N-type ohmic contact layer, and the N-type electrode is electrically connected to the N-type ohmic contact layer.
[0021] Optionally, the P-type current spreading layer is a P-type AlGaInP current spreading layer;
[0022] And / or, the N-type ohmic contact layer is an N-type GaInP ohmic contact layer;
[0023] And / or, the N-type current spreading layer is an N-type AlGaInP current spreading layer.
[0024] Optionally, the surface of the N-type layer facing the fixed substrate is roughened.
[0025] Optionally, the LED chip further includes:
[0026] A protective film layer covers the exposed surfaces of the N-type layer, the active layer, the P-type layer, and the P-type ohmic contact layer, and the protective film layer includes a first cutout exposing at least a portion of the N-type electrode and a second cutout exposing at least a portion of the P-type electrode.
[0027] A first pad and a second pad, wherein the first pad is electrically connected to the N-type electrode through the first cutout, and the second pad is electrically connected to the P-type electrode through the second cutout.
[0028] Optionally, the protective film layer is an insulating layer or a DBR layer.
[0029] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:
[0030] This application provides an LED epitaxial structure and an LED chip. The LED epitaxial structure includes: an N-type temporary substrate, a composite buffer layer, a P-type etch stop layer, a P-type ohmic contact layer, a P-type layer, an active layer, and an N-type layer, which are grown sequentially. The composite buffer layer includes an N-type buffer layer, an undoped buffer layer, and a P-type buffer layer, which are grown sequentially. The N-type buffer layer is located between the N-type temporary substrate and the undoped buffer layer. The LED chip includes: a fixed substrate; an N-type layer located on one side of the fixed substrate and bonded to the fixed substrate, wherein the surface of the N-type layer facing away from the fixed substrate includes a device region and a first electrode region; an active layer located on the side of the N-type layer facing away from the fixed substrate and located in the device region; a P-type layer located on the side of the active layer facing away from the N-type layer and located in the second electrode region; an N-type electrode and a P-type electrode, wherein the N-type electrode is located on the side of the N-type layer facing away from the fixed substrate and located in the first electrode region; and the P-type electrode is located on the side of the P-type ohmic contact layer facing away from the fixed substrate and located in the second electrode region.
[0031] As described above, the LED epitaxial structure provided in this application adopts an N-type temporary substrate design, reducing the fabrication cost of the LED epitaxial structure and chip. Furthermore, the LED epitaxial structure employs a composite buffer layer design, comprising sequentially stacked N-type buffer layers, undoped buffer layers, and P-type buffer layers, thereby achieving a transition from N-type to P-type materials, reducing lattice defects, and improving the fabrication quality of the LED epitaxial structure. In addition, the LED chip provided in this application implements an inverted N-type and P-type epitaxial structure, forming a mesa structure with an exposed N-type layer in the device region. Since the carrier mobility of the N-type layer is greater than that of the P-type layer, the current spread effect of the LED chip at the mesa structure is higher, improving the current spread capability of the LED chip, enhancing its photoelectric performance and antistatic properties, and ultimately improving its overall performance. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0033] Figure 1 This is a schematic diagram of an LED epitaxial structure provided in an embodiment of this application;
[0034] Figure 2 This is a schematic diagram of another LED epitaxial structure provided in an embodiment of this application;
[0035] Figure 3 A flowchart illustrating a method for fabricating an LED epitaxial structure, as provided in this application embodiment;
[0036] Figure 4 This is a schematic diagram of the structure of an LED chip provided in an embodiment of this application;
[0037] Figure 5 This is a schematic diagram of another LED chip structure provided in an embodiment of this application;
[0038] Figure 6 This is a schematic diagram of the structure of another LED chip provided in an embodiment of this application. Detailed Implementation
[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0040] As described in the background section, LEDs, as a new generation of green lighting energy, have been widely used in various fields. LED lighting has now completely replaced traditional lighting sources, and LEDs occupy an important position in the display industry, with their market share and application areas continuously expanding. In particular, as the resolution of LED display devices increases, micro-LED devices (such as Mini / Micro LEDs) have become the new favorite in the display field. Compared with traditional display devices, displays composed of micro-LED devices have advantages such as fast response, high color gamut, high PPI, and low energy consumption. Although LED devices have many advantages, with the gradual development of LED display technology and higher demands, the performance of LED devices still needs further improvement.
[0041] Based on this, the embodiments of this application provide an LED epitaxial structure and an LED chip, which effectively solves the technical problems existing in the prior art, improves the fabrication quality of the LED epitaxial structure, and improves the performance of the LED chip.
[0042] To achieve the above objectives, the technical solutions provided in this application are as follows, in specific combination with... Figures 1 to 6 The technical solutions provided in the embodiments of this application will be described in detail.
[0043] refer to Figure 1 The diagram shown is a schematic representation of an LED epitaxial structure according to an embodiment of this application. The LED epitaxial structure includes, in this embodiment, a sequentially stacked N-type temporary substrate 11, a composite buffer layer 12, a P-type etch stop layer 13, a P-type ohmic contact layer 14, a P-type layer 15, an active layer 16, and an N-type layer 17. The composite buffer layer 12 includes, in this embodiment, a sequentially stacked N-type buffer layer 121, an undoped buffer layer 122, and a P-type buffer layer 123, wherein the N-type buffer layer 121 is located between the N-type temporary substrate 11 and the undoped buffer layer 122.
[0044] As can be seen from the above, the LED epitaxial structure provided in this application adopts an N-type temporary substrate 11, which reduces the fabrication cost of the LED epitaxial structure and chip. Furthermore, the LED epitaxial structure adopts a composite buffer layer 12, which includes sequentially stacked N-type buffer layer 121, undoped buffer layer 122, and P-type buffer layer 123, thereby achieving a transition from N-type to P-type materials, reducing lattice defects, and improving the fabrication quality of the LED epitaxial structure. Additionally, the LED epitaxial structure provided in this application achieves an inversion of N-type and P-type structures. During subsequent LED chip fabrication, a mesa structure with exposed N-type layer 17 will be formed. Since the carrier mobility of N-type layer 17 is greater than that of P-type layer 15, the fabricated LED chip exhibits higher current spread at the mesa structure, improving the current spread capability of the LED chip, enhancing its photoelectric performance and antistatic properties, and ultimately improving its overall performance.
[0045] refer to Figure 2 The diagram shows another LED epitaxial structure provided in this application embodiment. The P-type layer 15 provided in this application embodiment includes a P-type current spreading layer 151 and a P-type confinement layer 152 grown sequentially. The P-type current spreading layer 151 is located between the P-type ohmic contact layer 14 and the P-type confinement layer 152. Therefore, the design of the P-type current spreading layer 151 further improves the current spreading capability of the subsequently fabricated LED chip, thereby improving the performance of the LED chip. Continuing... Figure 2 As shown in the embodiment of this application, the N-type layer 17 includes an N-type confinement layer 171, an N-type ohmic contact layer 172, and an N-type current spreading layer 173, which are sequentially stacked. The N-type confinement layer 171 is located between the active layer 16 and the N-type ohmic contact layer 172. The design of the N-type ohmic contact layer 172 improves the ohmic contact performance of the epitaxial structure. Furthermore, the design of the N-type current spreading layer 173 further improves the current spreading capability of the subsequently fabricated LED chip, thus enhancing the LED chip's performance. In addition, the LED epitaxial structure provided in this embodiment achieves an inversion of N-type and P-type structures. During subsequent LED chip fabrication, a mesa structure exposing the N-type ohmic contact layer 172 is formed. Since the carrier mobility of the N-type current spreading layer 173 is greater than that of the P-type current spreading layer 151, the current spreading effect of the fabricated LED chip at the mesa structure is higher, improving the current spreading capability of the LED chip, enhancing its photoelectric performance and antistatic properties, and ultimately improving its overall performance.
[0046] In some embodiments, the N-type ohmic contact layer 172 provided in this application is an N-type GaInP ohmic contact layer, whose band gap is larger than that of existing ohmic contact layers made of GaAs material, thereby avoiding light absorption and improving light extraction efficiency; and since GaInP material does not contain Al component compared to AlGaInP material, it is easier to form ohmic contacts, thereby reducing voltage. And / or, the N-type current spreading layer 173 provided in this application is an N-type AlGaInP current spreading layer, and the P-type current spreading layer 151 is a P-type AlGaInP current spreading layer. Compared with existing current spreading layers made of GaP material, the AlGaInP current spreading layer provided in this application does not have a lattice mismatch problem with the substrate, improving the crystal quality of the LED epitaxial structure.
[0047] refer to Figure 3 The diagram shown is a flowchart of a method for fabricating an LED epitaxial structure according to an embodiment of this application. Figure 2 Taking the illustrated LED epitaxial structure as an example, the method for fabricating the LED epitaxial structure provided in this application includes:
[0048] S1. Provide an N-type temporary substrate 11. The N-type temporary substrate 11 provided in this embodiment can be an N-type GaAs substrate, specifically an N-type GaAs 15° substrate. After the N-type temporary substrate 11 is placed in the reaction chamber, the temperature is raised to grow the subsequent epitaxial structure.
[0049] S2. A composite buffer layer 12 is grown on one side surface of the N-type temporary substrate 11, wherein the composite buffer layer 12 includes an N-type buffer layer 121, an undoped buffer layer 122, and a P-type buffer layer 123 grown sequentially. The composite buffer layer 12 provided in this embodiment can be a composite GaAs buffer layer. Specifically, the N-type buffer layer 121 can be an N-type GaAs buffer layer, and the doping element of the N-type GaAs buffer layer can be Si / Te, with a doping concentration of 1–5E18 / cm³. 3 The thickness of the buffer layer can be 1000–4000 angstroms. The undoped buffer layer 122 can be an undoped GaAs buffer layer, with a thickness of 500–2000 angstroms. Furthermore, the p-type buffer layer 123 can be a p-type GaAs buffer layer, with Mg / Zn as the doping element and a doping concentration of 1–5E18 / cm³. 3 And its thickness can be 1000 to 4000 angstroms.
[0050] S3. A P-type corrosion stop layer 13 is grown on the composite buffer layer 12. The P-type corrosion stop layer 13 provided in this embodiment can be a P-type GaInP corrosion stop layer, and its doping element can be Mg / Zn, with a doping concentration of 0.5–5E18 / cm³. 3 .
[0051] S4. Grow a P-type ohmic contact layer 14 on the P-type corrosion stop layer 13. The P-type ohmic contact layer 14 provided in this embodiment can be a P-type GaAs ohmic contact layer, and its doping element can be Mg / Zn, with a doping concentration of 1 to 5E18 / cm³. 3 .
[0052] S5. A P-type layer 15 is grown on the P-type ohmic contact layer 14, wherein the P-type layer 15 includes a P-type current spreading layer 151 and a P-type confinement layer 152 grown sequentially. The P-type current spreading layer 151 provided in this embodiment can be a P-type AlGaInP current spreading layer, and its doping element can be Mg / Zn, with a doping concentration of 0.5–5E18 / cm³. 3 Furthermore, the p-type confinement layer 152 provided in this application embodiment can be a p-type AlInP confinement layer, the doping element of which can be Mg / Zn, and the doping concentration of which can be 0.5~3E18 / cm³. 3 .
[0053] S6. An active layer 16 is grown on the P-type layer 15. The active layer 16 provided in this embodiment can be a multiple quantum well (MQW) active layer.
[0054] S7. An N-type layer 17 is grown on the active layer 16, wherein the N-type layer 17 includes an N-type confinement layer 171, an N-type ohmic contact layer 172, and an N-type current spreading layer 173, which are sequentially stacked. The N-type confinement layer 171 provided in this embodiment can be an N-type AlInP confinement layer, and the doping element of the N-type AlInP confinement layer can be Si / Te, with a doping concentration of 0.5–3E18 / cm³. 3 The N-type ohmic contact layer 172 can be an N-type GaInP ohmic contact layer. The doping element of the N-type GaInP ohmic contact layer can be Si / Te, and its doping concentration can be 1 to 5E18 / cm³. 3 Furthermore, the N-type current spreading layer 173 can be an N-type AlGaInP current spreading layer, and the doping element of the N-type AlGaInP current spreading layer can be Si / Te, with a doping concentration of 1–5E¹⁸ / cm². 3 .
[0055] Based on the same inventive concept, this application also provides an LED chip, which is fabricated using the LED epitaxial structure provided in any of the above embodiments. See details. Figure 4 The diagram shows a schematic of an LED chip according to an embodiment of this application. The LED chip includes: a fixed substrate 21; an N-type layer 22 located on one side of the fixed substrate 21, bonded to the fixed substrate 21; a bonding layer 28 (optionally, the bonding layer 28 can be a SiO2 bonding layer) between the fixed substrate 21 and the N-type layer 22; an active layer 23 located on the side of the N-type layer 22 away from the fixed substrate 21, situated in the device region; and a P-type layer 24 located on the side of the active layer 23 away from the N-type layer 22, situated on the side of the P-type layer 24 away from the fixed substrate 21, situated in the device region. A P-type ohmic contact layer 25 is located on the side of the P-type layer 24 away from the fixed substrate 21, and is situated in the second electrode region. An N-type electrode 26 and a P-type electrode 27 are also present. The N-type electrode 26 is located on the side of the N-type layer 22 away from the fixed substrate 21, and is situated in the first electrode region. The P-type electrode 27 is located on the side of the P-type ohmic contact layer 25 away from the fixed substrate 21, and is situated in the second electrode region.
[0056] Understandably, in the LED chip provided in this application embodiment, the N-type layer 22 is fabricated from the N-type layer 17 of the LED epitaxial structure, the active layer 23 is fabricated from the active layer 16 of the LED epitaxial structure, and the P-type layer 24 is fabricated from the P-type layer 15 of the LED epitaxial structure. The LED chip provided in this application embodiment is fabricated using any of the LED epitaxial structures provided in the above embodiments. The crystal quality of the epitaxial structure in the LED chip is high, improving the performance of the LED chip. Furthermore, the LED epitaxial structure provided in this application embodiment achieves the inversion of N-type and P-type layers. Based on this, the LED chip fabricated forms a mesa structure with exposed N-type layer 22 in the device region. Since the carrier mobility of the N-type layer 22 is greater than that of the P-type layer 24, the current spreading effect of the fabricated LED chip at the mesa structure is higher, improving the current spreading capability of the LED chip, enhancing the photoelectric performance and antistatic capability of the LED chip, and improving the overall performance of the LED chip.
[0057] refer to Figure 5The diagram shown is a schematic diagram of another LED chip structure provided in this application embodiment. The P-type layer 24 provided in this application embodiment includes a P-type current spreading layer 241 and a P-type confinement layer 242 that are grown sequentially. The P-type current spreading layer 241 is located between the P-type ohmic contact layer 25 and the P-type confinement layer 242. The design of the P-type current spreading layer 241 further improves the current spreading capability of the LED chip and improves the performance of the LED chip. And / or, the N-type layer 22 provided in this application embodiment includes an N-type confinement layer 221, an N-type ohmic contact layer 222, and an N-type current spreading layer 223 grown sequentially, wherein the N-type confinement layer 221 is located between the active layer 23 and the N-type ohmic contact layer 222; in the device region, the N-type layer 22 exposes the N-type ohmic contact layer 222, and the N-type electrode 26 is electrically connected to the N-type ohmic contact layer 222, thereby improving the ohmic contact performance of the epitaxial structure through the design of the N-type ohmic contact layer 222; and further improving the current spreading capability of the LED chip and improving the performance of the LED chip through the design of the N-type ohmic contact layer 223. Furthermore, the LED epitaxial structure provided in this application embodiment realizes the inversion of N-type and P-type, so that the prepared LED chip forms a mesa structure with exposed N-type ohmic contact layer 222. Since the carrier mobility of the N-type current spreading layer 223 is greater than that of the P-type current spreading layer 241, the current spreading effect of the prepared LED chip at the mesa structure is higher, which improves the current spreading capability of the LED chip, enhances the photoelectric performance and antistatic capability of the LED chip, and improves the performance of the LED chip.
[0058] In some embodiments, the N-type ohmic contact layer 222 provided in this application is an N-type GaInP ohmic contact layer, whose band gap is larger than that of existing ohmic contact layers made of GaAs material, thereby avoiding light absorption and improving light extraction efficiency; and since GaInP material does not contain Al component compared to AlGaInP material, it is easier to form ohmic contacts, thereby reducing voltage. And / or, the N-type current spreading layer 223 provided in this application is an N-type AlGaInP current spreading layer, and / or, the P-type current spreading layer 241 is a P-type AlGaInP current spreading layer. Compared with existing current spreading layers made of GaP material, the AlGaInP current spreading layer provided in this application does not have a lattice mismatch problem with the substrate, improving the crystal quality of the LED epitaxial structure.
[0059] refer to Figure 6The diagram shows a structural schematic of another LED chip provided in this application embodiment, wherein the surface of the N-type layer 22 facing the fixed substrate 21 is roughened. When the N-type layer 22 includes an N-type confinement layer 221, an N-type ohmic contact layer 222, and an N-type current spreading layer 223 grown sequentially, the roughened surface is the surface of the N-type current spreading layer 223 facing the fixed substrate 21, thereby further improving the performance of the LED chip. Continuing as... Figure 6 As shown, the LED chip provided in this embodiment further includes: a protective film layer 29, which covers the exposed surfaces of the N-type layer 22, the active layer 23, the P-type layer 24, and the P-type ohmic contact layer 25, and extends to cover at least a portion of the surfaces of the N-type electrode 26 and the P-type electrode 27. Specifically, the protective film layer 29 includes a first cutout exposing at least a portion of the N-type electrode 26 and a second cutout exposing at least a portion of the P-type electrode 27. A first pad 211 and a second pad 212 are also included. The first pad 211 is electrically connected to the N-type electrode 26 through the first cutout, and the second pad 212 is electrically connected to the P-type electrode 27 through the second cutout. In some embodiments, the protective film layer 29 provided in this embodiment can be an insulating layer (such as an ISO insulating layer) or a DBR (Distributed Bragg Reflector) layer.
[0060] The technical solution provided in the embodiments of this application will be described in more detail below through the method of LED chip fabrication. Specifically, using... Figure 6 Taking the LED chip shown as an example, the method for preparing the LED chip provided in this application embodiment includes:
[0061] S11. Provide an LED epitaxial structure as illustrated in any of the above embodiments. Optionally, using... Figure 3 The schematic diagram of an LED epitaxial structure is used as an example.
[0062] S12. Roughen the N-type current extension layer 173 in the LED epitaxial structure to form a roughened surface.
[0063] S13. The N-type current spreading layer 173 and the fixed substrate 21 are bonded together to form a bonding layer 28. The fixed substrate 21 provided in this embodiment can be a sapphire substrate, and this application does not impose specific limitations on it.
[0064] S14. Remove the N-type temporary substrate 11, composite buffer layer 12 and P-type etch stop layer 13 from the LED epitaxial structure, and expose the P-type ohmic contact layer 14 in the LED epitaxial structure.
[0065] S15. The P-type ohmic contact layer 14, P-type current spreading layer 151, P-type confinement layer 152, active layer 16, and N-type confinement layer 171 in the LED epitaxial structure are etched using an etching process until the exposed N-type ohmic contact layer 172 in the LED epitaxial structure forms a mesa structure, thereby obtaining the P-type current spreading layer 241, P-type confinement layer 242, active layer 23, N-type confinement layer 221, N-type ohmic contact layer 222, and N-type current spreading layer 223 of the LED chip. Optionally, the etching process provided in this embodiment can be an ICP dry etching process.
[0066] S16. An N-type electrode 26 is deposited on the N-type ohmic contact layer 222 at the mesa structure (device area), and the P-type ohmic contact layer 25 of the LED chip is further etched by etching the P-type ohmic contact layer 222 in step S15, and a P-type electrode 27 is deposited on the P-type ohmic contact layer 25.
[0067] S17. The cutting pattern is obtained by etching using an etching process, wherein the etching process can also be the ICP dry etching process.
[0068] S18. A protective film is deposited by vapor deposition, and a first and second perforation are formed by etching, thereby obtaining a protective film layer 29. The etching process can be an ICP dry etching process.
[0069] S19, first pad 211 and second pad 212 are vapor deposited, and then the LED chip is cut and split to obtain the LED chip.
[0070] In summary, this application provides an LED epitaxial structure and an LED chip. The LED epitaxial structure includes: an N-type temporary substrate, a composite buffer layer, a P-type etch stop layer, a P-type ohmic contact layer, a P-type layer, an active layer, and an N-type layer, which are grown sequentially. The composite buffer layer includes an N-type buffer layer, an undoped buffer layer, and a P-type buffer layer, which are grown sequentially, wherein the N-type buffer layer is located between the N-type temporary substrate and the undoped buffer layer. The LED chip includes: a fixed substrate; an N-type layer located on one side of the fixed substrate and bonded to the fixed substrate, wherein the surface of the N-type layer facing away from the fixed substrate includes a device region and a first electrode region; an active layer located on the side of the N-type layer facing away from the fixed substrate and located in the device region; a P-type layer located on the side of the active layer facing away from the N-type layer and located in the second electrode region; an N-type electrode and a P-type electrode, wherein the N-type electrode is located on the side of the N-type layer facing away from the fixed substrate and located in the first electrode region; and the P-type electrode is located on the side of the P-type ohmic contact layer facing away from the fixed substrate and located in the second electrode region.
[0071] As described above, the LED epitaxial structure provided in this application adopts an N-type temporary substrate design, reducing the fabrication cost of the LED epitaxial structure and chip. Furthermore, the LED epitaxial structure employs a composite buffer layer design, comprising sequentially stacked N-type buffer layers, undoped buffer layers, and P-type buffer layers, thereby achieving a transition from N-type to P-type materials, reducing lattice defects, and improving the fabrication quality of the LED epitaxial structure. In addition, the LED chip provided in this application implements an inverted N-type and P-type epitaxial structure, forming a mesa structure with an exposed N-type layer in the device region. Since the carrier mobility of the N-type layer is greater than that of the P-type layer, the current spread effect of the LED chip at the mesa structure is higher, improving the current spread capability of the LED chip, enhancing its photoelectric performance and antistatic properties, and ultimately improving its overall performance.
[0072] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0073] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0074] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0075] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0076] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0077] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. An LED epitaxial structure, characterized in that, The LED epitaxial structure includes: The N-type temporary substrate, composite buffer layer, P-type etch stop layer, P-type ohmic contact layer, P-type layer, active layer and N-type layer are grown sequentially. The composite buffer layer comprises an N-type buffer layer, an undoped buffer layer, and a P-type buffer layer grown sequentially, wherein the N-type buffer layer is located between the N-type temporary substrate and the undoped buffer layer.
2. The LED epitaxial structure according to claim 1, characterized in that, The P-type layer includes a P-type current spreading layer and a P-type confinement layer that are grown sequentially, wherein the P-type current spreading layer is located between the P-type ohmic contact layer and the P-type confinement layer.
3. The LED epitaxial structure according to claim 1, characterized in that, The N-type layer includes an N-type confinement layer, an N-type ohmic contact layer, and an N-type current spreading layer that are grown sequentially, wherein the N-type confinement layer is located between the active layer and the N-type ohmic contact layer.
4. The LED epitaxial structure according to claim 3, characterized in that, The N-type ohmic contact layer is an N-type GaInP ohmic contact layer; And / or, the N-type current spreading layer is an N-type AlGaInP current spreading layer.
5. An LED chip, characterized in that, The LED chip includes: Fixed substrate; An N-type layer is located on one side of the fixed substrate, and the fixed substrate and the N-type layer are bonded and fixed together. The surface of the N-type layer facing away from the fixed substrate includes a device region and a first electrode region. An active layer is located on the side of the N-type layer away from the fixed substrate, and the active layer is located in the device region; A P-type layer is located on the side of the active layer away from the N-type layer, and the surface of the P-type layer away from the fixed substrate includes a second electrode region. A P-type ohmic contact layer is located on the side of the P-type layer away from the fixed substrate, and the P-type ohmic contact layer is located in the second electrode region; An N-type electrode and a P-type electrode, wherein the N-type electrode is located on the side of the N-type layer away from the fixed substrate, and the N-type layer is located in the first electrode region; the P-type electrode is located on the side of the P-type ohmic contact layer away from the fixed substrate, and the P-type electrode is located in the second electrode region.
6. The LED chip according to claim 5, characterized in that, The P-type layer includes a P-type current spreading layer and a P-type confinement layer that are grown sequentially, wherein the P-type current spreading layer is located between the P-type ohmic contact layer and the P-type confinement layer; And / or, the N-type layer includes an N-type confinement layer, an N-type ohmic contact layer and an N-type current spreading layer that are grown sequentially, wherein the N-type confinement layer is located between the active layer and the N-type ohmic contact layer; in the device region, the N-type layer exposes the N-type ohmic contact layer, and the N-type electrode is electrically connected to the N-type ohmic contact layer.
7. The LED chip according to claim 6, characterized in that, The P-type current spreading layer is a P-type AlGaInP current spreading layer; And / or, the N-type ohmic contact layer is an N-type GaInP ohmic contact layer; And / or, the N-type current spreading layer is an N-type AlGaInP current spreading layer.
8. The LED chip according to claim 5, characterized in that, The surface of the N-type layer facing the fixed substrate is roughened.
9. The LED chip according to claim 5, characterized in that, The LED chip also includes: A protective film layer covers the exposed surfaces of the N-type layer, the active layer, the P-type layer, and the P-type ohmic contact layer, and the protective film layer includes a first cutout exposing at least a portion of the N-type electrode and a second cutout exposing at least a portion of the P-type electrode. A first pad and a second pad, wherein the first pad is electrically connected to the N-type electrode through the first cutout, and the second pad is electrically connected to the P-type electrode through the second cutout.
10. The LED chip according to claim 9, characterized in that, The protective film layer is an insulating isolation layer or a DBR layer.