Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a substrate body, a plurality of bonding pads and a circuit structure layer. The substrate body comprises a display area and a first binding area located on one side of the display area. The plurality of bonding pads are located in the first binding area, and the plurality of bonding pads are configured to be bound with a driving chip; the circuit structure layer is arranged on the substrate, a groove is formed in the end face, away from the substrate, of the circuit structure layer, and the orthographic projection, on the substrate, of the groove is located in the first binding area and does not overlap with the orthographic projection, on the substrate, of the bonding pad; the circuit structure layer comprises a plurality of inorganic insulating layers which are arranged in a stacked mode in the direction perpendicular to the substrate, and the groove is arranged to penetrate through at least one inorganic insulating layer in the direction perpendicular to the substrate.

Description

Technical Field

[0001] This utility model relates to display technology, and more specifically, to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Utility Model Content

[0003] This utility model embodiment provides a display substrate, including:

[0004] The substrate includes a display area and a first border area located on one side of the display area, the first border area including a first bonding area;

[0005] Multiple sub-pixels are located on one side of the substrate and within the display area;

[0006] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, and the multiple data lines are configured to transmit data signals to the multiple sub-pixels;

[0007] Multiple pads are located in the first bonding area, and the multiple pads are configured to be bonded to the driver chip;

[0008] Multiple data transmission lines are located in the first border area, and the multiple data transmission lines connect the multiple data lines and at least a portion of the multiple pads;

[0009] A circuit structure layer is disposed on the substrate. The circuit structure layer has a groove on the end face away from the substrate. The orthographic projection of the groove on the substrate is located in the first bonding area and does not overlap with the orthographic projection of the plurality of pads on the substrate.

[0010] The circuit structure layer includes a plurality of inorganic insulating layers stacked in a direction perpendicular to the substrate, and the groove is configured to penetrate at least one of the inorganic insulating layers in a direction perpendicular to the substrate.

[0011] In some exemplary embodiments, the plurality of pads include at least one row of input pads and at least one row of output pads, the at least one row of input pads and the at least one row of output pads being arranged at a distance from each other in a first direction, the groove being located between the at least one row of input pads and the at least one row of output pads, the first direction being parallel to the substrate.

[0012] In some exemplary embodiments, the groove is provided with at least two, and the at least two grooves include a first groove and a second groove, the first groove and the second groove being arranged at a distance from each other in the first direction.

[0013] In some exemplary embodiments, the circuit structure layer further includes an array test unit located between the at least one row of input pads and the at least one row of output pads in the first direction;

[0014] The first groove is located between the array test unit and the at least one row of output pads in the first direction, and the second groove is located between the array test unit and the at least one row of input pads in the first direction.

[0015] In some exemplary embodiments, the first groove is provided in multiple ways, including a third groove and a fourth groove spaced apart in the first direction, the third groove and the fourth groove being staggered in a second direction, the second direction being parallel to the substrate and perpendicular to the first direction; and / or

[0016] The second groove is provided in multiple ways, including a fifth groove and a sixth groove arranged at intervals in the first direction, and the fifth groove and the sixth groove are staggered in the second direction.

[0017] In some exemplary embodiments, the groove is in the form of a closed ring or an intermittently arranged ring on a plane parallel to the substrate.

[0018] In some exemplary embodiments, the circuit structure layer further includes an array test unit located in the first direction between the at least one row of input pads and the at least one row of output pads, the groove being configured to surround the array test unit.

[0019] In some exemplary embodiments, the groove is provided with at least two, the at least two grooves including a first groove and a second groove, the first groove and the second groove being arranged at intervals in a second direction, the second direction being parallel to the substrate and perpendicular to the first direction.

[0020] In some exemplary embodiments, the circuit structure layer further includes an array test unit located between the at least one row of input pads and the at least one row of output pads in the first direction, and the first groove and the second groove are respectively disposed on both sides of the array test unit in the second direction.

[0021] In some exemplary embodiments, the groove is provided with at least two, the at least two grooves including a first groove and a second groove, wherein the size of the first groove in the direction perpendicular to the base is not equal to the size of the second groove in the direction perpendicular to the base.

[0022] In some exemplary embodiments, the first groove has a dimension H1 in the direction perpendicular to the base, and the second groove has a dimension H2 in the direction perpendicular to the base, where H1 < H2;

[0023] The number of the first grooves penetrating the inorganic insulating layer is n, and the number of the second grooves penetrating the inorganic insulating layer is m, where n < m.

[0024] In some exemplary embodiments, the groove is configured to extend along a second direction, and at least one row of the input pads and at least one row of the output pads are arranged along the second direction, which is perpendicular to the first direction and parallel to the substrate.

[0025] In some exemplary embodiments, the groove is configured to protrude from both ends of the at least one row of input pads in the second direction; and / or

[0026] The groove at both ends in the second direction is configured to protrude from both ends of the at least one row of output pads in the second direction.

[0027] In some exemplary embodiments, the plurality of inorganic insulating layers include a touch insulating layer and a touch buffer layer, the touch insulating layer being located on the side of the touch buffer layer away from the substrate, and the groove being configured to penetrate the touch insulating layer and the touch buffer layer in a direction perpendicular to the substrate.

[0028] In some exemplary embodiments, the plurality of inorganic insulating layers further include a first interlayer dielectric layer located on the side of the touch buffer layer near the substrate, and the groove is configured to penetrate the first interlayer dielectric layer in a direction perpendicular to the substrate.

[0029] In some exemplary embodiments, the circuit structure layer further includes a plurality of organic insulating layers, the plurality of organic insulating layers including a first organic layer located between the first interlayer dielectric layer and the touch buffer layer, wherein the orthographic projection of the first organic layer on the substrate and the orthographic projection of the groove on the substrate do not overlap.

[0030] In some exemplary embodiments, the plurality of inorganic insulating layers further includes a first gate insulating layer located on the side of the first interlayer dielectric layer near the substrate, and the groove is configured to penetrate the first gate insulating layer in a direction perpendicular to the substrate.

[0031] In some exemplary embodiments, the plurality of inorganic insulating layers further include a second gate insulating layer and a third gate insulating layer, the third gate insulating layer, the second gate insulating layer and the first gate insulating layer being arranged sequentially in a direction away from the substrate, and the groove being configured to penetrate the second gate insulating layer and the third gate insulating layer in a direction perpendicular to the substrate.

[0032] In some exemplary embodiments, the circuit structure layer further includes at least one conductive layer, wherein the orthographic projection of the groove on the substrate overlaps with the orthographic projection of the at least one conductive layer on the substrate.

[0033] This utility model embodiment also provides a display device, including the display panel described above.

[0034] In this embodiment of the present invention, a groove is formed on the circuit structure layer of the display substrate. The groove causes a local break in the inorganic layer. When the film layer peels off and grows to the break, it naturally stops at the position because there is no film layer under force. This prevents the film layer from peeling off to the vicinity of the driver chip bonding position, and the water vapor path formed by the film layer peeling off is stopped at the groove position.

[0035] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0036] The accompanying drawings are provided to further illustrate the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solution of this utility model and do not constitute a limitation on the technical solution of this utility model.

[0037] Figure 1 This is a schematic diagram of the structure of a display device;

[0038] Figure 2 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present invention;

[0039] Figure 3 for Figure 2 Side view of the display substrate;

[0040] Figure 4 This is a schematic diagram of a planar structure of a display substrate;

[0041] Figure 5 for Figure 2 A magnified view of part A in the diagram;

[0042] Figure 6 for Figure 5 Schematic diagram of section aa in the diagram;

[0043] Figure 7 This is a partial schematic diagram of another display substrate according to this exemplary embodiment;

[0044] Figure 8 This is a partial schematic diagram of yet another display substrate according to this exemplary embodiment;

[0045] Figure 9 This is a partial schematic diagram of another display substrate according to this exemplary embodiment;

[0046] Figure 10 This is a partial schematic diagram of yet another display substrate according to this exemplary embodiment;

[0047] Figure 11 This is a partial schematic diagram of another display substrate according to this exemplary embodiment;

[0048] Figure 12 This is a partial schematic diagram of yet another display substrate according to this exemplary embodiment;

[0049] Figure 13 for Figure 6 A magnified view of section B in the diagram;

[0050] Figure 14 for Figure 6 A magnified view of part C in the diagram;

[0051] Figure 15 This is a cross-sectional schematic diagram of another display substrate according to this exemplary embodiment;

[0052] Figure 16 for Figure 15 A magnified view of part D in the diagram;

[0053] Figure 17 This is a cross-sectional schematic diagram of another display substrate according to this exemplary embodiment;

[0054] Figure 18 for Figure 17 A magnified view of part E in the diagram;

[0055] Figure 19 This is a cross-sectional schematic diagram of another display substrate according to this exemplary embodiment;

[0056] Figure 20 for Figure 19 A magnified view of part F in the diagram;

[0057] Figure 21 This is a cross-sectional schematic diagram of another display substrate according to this exemplary embodiment;

[0058] Figure 22for Figure 21 A magnified view of point G in the diagram. Detailed Implementation

[0059] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0060] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique solutions. Any feature or element of any embodiment can also be combined with features or elements from other solutions to form another unique solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0061] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0062] This exemplary embodiment provides a display substrate, including:

[0063] The substrate includes a display area and a first border area located on one side of the display area, the first border area including a first bonding area;

[0064] Multiple sub-pixels are located on one side of the substrate and within the display area;

[0065] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, and the multiple data lines are configured to transmit data signals to the multiple sub-pixels;

[0066] Multiple pads are located in the first bonding area, and the multiple pads are configured to be bonded to the driver chip;

[0067] Multiple data transmission lines are located in the first border area, and the multiple data transmission lines connect the multiple data lines and at least a portion of the multiple pads;

[0068] A circuit structure layer is disposed on the substrate. The circuit structure layer has a groove on the end face away from the substrate. The orthographic projection of the groove on the substrate is located in the first bonding area and does not overlap with the orthographic projection of the plurality of pads on the substrate.

[0069] The circuit structure layer includes a plurality of inorganic insulating layers stacked in a direction perpendicular to the substrate, and the groove is configured to penetrate at least one of the inorganic insulating layers in a direction perpendicular to the substrate.

[0070] In some exemplary embodiments, the plurality of pads include at least one row of input pads and at least one row of output pads, the at least one row of input pads and the at least one row of output pads being arranged at a distance from each other in a first direction, the groove being located between the at least one row of input pads and the at least one row of output pads, the first direction being parallel to the substrate.

[0071] In some exemplary embodiments, the groove is provided with at least two, and the at least two grooves include a first groove and a second groove, the first groove and the second groove being arranged at a distance from each other in the first direction.

[0072] In some exemplary embodiments, the circuit structure layer further includes an array test unit located between the at least one row of input pads and the at least one row of output pads in the first direction;

[0073] The first groove is located between the array test unit and the at least one row of output pads in the first direction, and the second groove is located between the array test unit and the at least one row of input pads in the first direction.

[0074] In some exemplary embodiments, the plurality of inorganic insulating layers include a touch insulating layer and a touch buffer layer, the touch insulating layer being located on the side of the touch buffer layer away from the substrate, and the groove being configured to penetrate the touch insulating layer and the touch buffer layer in a direction perpendicular to the substrate.

[0075] In some exemplary embodiments, the plurality of inorganic insulating layers further include a first interlayer dielectric layer located on the side of the touch buffer layer near the substrate, and the groove is configured to penetrate the first interlayer dielectric layer in a direction perpendicular to the substrate.

[0076] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels ij, where i and j can be natural numbers. At least one sub-pixel ij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn in unit rows, where n can be a natural number. The scan driver can receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The LED driver can receive clock signals, transmit stop signals, etc., from the timing controller to generate transmit signals to LED signal lines E1, E2, E3, ..., Eo. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0077] Figure 2 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment, a planar view before the bending process. Figure 3 for Figure 2The image shows a side view of the substrate, illustrating the bent state of the bonding area. In some exemplary embodiments, such as... Figure 2 and Figure 3 As shown, on a plane parallel to the display substrate, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. For example, the peripheral area BB may include a first border area B1 located on one side of the display area AA, and peripheral areas BB located on other sides of the display area AA (e.g., may include a second border area B2, a third border area B3, and a fourth border area B4). The first border area B1 may be, for example, the lower border of the display substrate, the second border area B2 may be the upper border of the display substrate, the third border area B3 may be the left border of the display substrate, and the fourth border area B4 may be the right border of the display substrate. The display area AA may be a flat area, and may include multiple sub-pixels forming a pixel array. These sub-pixels may be configured to display moving or still images. The display area AA may be referred to as the active area. In some examples, the display area AA may be rectangular. However, this embodiment is not limited to this; for example, the display area AA may be circular or elliptical, or other shapes. In some examples, the display substrate may be a flexible panel, and therefore the display substrate may be deformable, such as rolled, bent, folded, or rolled up.

[0078] In some exemplary embodiments, such as Figure 2 As shown, the display area AA may include at least: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a first direction X, and the multiple data lines DL may extend along a second direction Y. The orthogonal projections of the multiple gate lines GL and the multiple data lines DL onto the substrate may intersect to form multiple sub-pixel regions, each of which may contain one sub-pixel PX. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide gate control signals to the multiple sub-pixels PX. In some examples, the gate control signals may include scan signals and light emission control signals, or may include scan signals, or may include scan signals, reset control signals, and light emission control signals.

[0079] In some exemplary embodiments, such as Figure 2 As shown, the second direction can be the extension direction of the grid line GL in the display area AA (e.g., the row direction), and the first direction can be the extension direction of the data line DL in the display area AA (e.g., the column direction). The first and second directions can intersect each other, for example, they can be perpendicular to each other.

[0080] Figure 4This is a schematic diagram of a planar structure of a display substrate. Figure 4 As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel circuit. The pixel circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting device in each sub-pixel is connected to the pixel circuit of the sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.

[0081] In some exemplary embodiments, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In exemplary embodiments, the shape of the sub-pixels may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement, etc., without limitation herein. In some exemplary embodiments, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may be arranged along a straight line, but are not limited thereto; for example, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may be arranged in a non-linear arrangement such as a triangular arrangement. In some exemplary embodiments, a pixel unit P may include four sub-pixels, and the four sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement, without limitation herein.

[0082] In some exemplary embodiments, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. However, this embodiment is not limited to this.

[0083] In some exemplary embodiments, the multiple transistors in the pixel circuit can employ low-temperature polysilicon (LTPS) thin-film transistors (TFTs) and oxide (OTP) thin-film transistors (OTPs). The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OTP TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OTPs offer advantages such as low leakage current. Integrating LTPS and OTPs onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0084] In some exemplary embodiments, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some exemplary embodiments, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0085] In some exemplary embodiments, the display substrate can integrate a touch structure. The display substrate may include an organic light-emitting diode (OLED) display structure, a plasma display structure, or an electrophoretic display structure. For example, the display substrate may include an OLED display structure and a touch structure. The touch structure can be disposed on the encapsulation layer of the display structure, forming a Touch on Thin Film Encapsulation (TFE) structure. The integration of the display structure and the touch structure offers advantages such as thinness, lightness, and foldability, meeting the product requirements for flexible folding and narrow bezels.

[0086] In some exemplary embodiments, the touch structure on the thin-film encapsulation mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure operates based on mutual capacitance detection, typically using two metal layers to form the driving (Tx) electrode and the sensing (Rx) electrode. The integrated circuit (IC) realizes touch action by detecting the mutual capacitance between the driving and sensing electrodes. The FSLOC structure operates based on self-capacitance (or voltage) detection, typically using a single metal layer to form the touch electrode. The integrated circuit realizes touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0087] In some exemplary embodiments, such as Figure 2 and Figure 3 As shown, the first border area B1 may include a fan-out area B11, a bending area B12, and a bonding area B13 arranged sequentially along a direction away from the display area AA. The fan-out area B11 may be connected to the display area AA and may include at least multiple data transmission lines DL1, configured as data signal lines connecting the display area. The bending area B12 may be connected to the fan-out area B11 and may include a composite insulating layer, configured to bend the bonding area to the back of the display area AA, such that the bonding area B13 may overlap with the display area AA in a direction perpendicular to the plane of the display area. The bonding area B13 may include at least a first bonding area B14 and a second bonding area B15. A driver chip (Integrated Circuit, IC) (not shown) may be bonded to the first bonding area B14, and a flexible circuit board (not shown) may be bonded to the second bonding area B15. The driver chip may be bonded to the first bonding area B14 via an anisotropic conductive film or other means. The driver chip can generate driving signals required to drive sub-pixels and can provide these driving signals to the sub-pixels in the display area AA. For example, the driving signal can be a data signal that drives the brightness of a sub-pixel. In an exemplary embodiment, the second bonding area B15 may include multiple pins, and the flexible circuit board 250 may be bonded to the multiple pins.

[0088] The applicant discovered that during the bonding process between the display substrate and the driver chip, a relatively high bonding pressure is unavoidable to ensure a stable bonding resistance and prevent weak bonding. When the bonding pressure is too high, cracks may occur in the display substrate at the location corresponding to the driver chip. While internal cracks generally do not affect the screen itself, the warping of the display substrate can cause crack propagation leading to film peeling, which poses a reliability risk. Specifically, film peeling may create moisture pathways. Internal moisture, during crack propagation, causes rapid film peeling, eventually reaching the vicinity of the driver chip bonding location. Moisture corrosion will ultimately lead to driver chip bonding failure.

[0089] The technical solutions of the present invention will be described in detail below through specific embodiments.

[0090] Figure 5 This is a schematic diagram of a display substrate according to an exemplary embodiment of the present invention. Figure 6 for Figure 5 The schematic diagram of section aa in this exemplary embodiment shows a display substrate, such as... Figures 1 to 6 As shown, the display substrate may include a substrate 100, sub-pixels PX, multiple data lines DL, a circuit structure layer 200, multiple pads 300, and multiple data transmission lines DL1. The substrate 100 may include a display area AA and a first border area B1 located on one side of the display area AA. The first border area B1 may include a first bonding area B14. Multiple sub-pixels PX may be located on one side of the substrate 100 and within the display area AA. Multiple data lines DL may be located in the display area AA and electrically connected to the multiple sub-pixels PX, and the multiple data lines DL are configured to transmit data signals to the multiple sub-pixels PX. Multiple pads 300 are located in the first bonding area B14, and the multiple pads 300 are configured to bond to a driver chip (not shown). Multiple data transmission lines DL1 may be located in the first border area B1, and the multiple data transmission lines DL1 connect the multiple data lines DL and at least a portion of the multiple pads 300. A circuit structure layer 200 is disposed on a substrate 100. The circuit structure layer 200 has a groove 400 on its end face away from the substrate 100. The orthographic projection of the groove 400 onto the substrate 100 is located in the first bonding area B14 and does not overlap with the orthographic projections of the plurality of pads 300 onto the substrate 100. The circuit structure layer 200 includes a plurality of inorganic insulating layers 201 stacked in a direction perpendicular to the substrate 100 (i.e., a third direction). The groove 400 is configured to penetrate at least one inorganic insulating layer 201 in the direction perpendicular to the substrate 100 (i.e., a third direction). Thus, in this example, the display substrate has a groove 400 formed on the circuit structure layer 200. The groove 400 causes an inorganic layer fracture at its location. When the film layer peels off and grows to this fracture surface, it naturally stops at this location because there is no stress on the film layer, thereby preventing the film layer peeling from reaching the vicinity of the driver chip bonding location. This also prevents the moisture path formed by the film layer peeling from ending at the groove 400.

[0091] In some exemplary embodiments, such as Figure 2 , Figure 5 and Figure 6 As shown, portions of the multiple pads 300 may be located on the side of the circuit structure layer 200 away from the substrate 100, and the driver chip can be connected to the display substrate through the pads 300. The multiple pads 300 may include at least one row of input pads 302 and at least one row of output pads 301, and the multiple output pads 301 in one row of output pads 301 may be spaced apart along a second direction. The output pads 301 may have multiple rows, and the multiple rows of output pads 301 may be spaced apart in a first direction parallel to the substrate 100. In this example, the multiple output pads 301 may be divided into three rows, namely the first row (i1), the second row (i2), and the third row (i3), and adjacent rows of the three rows of output pads 301 may be spaced apart in the first direction. However, this is not a limitation; for example, the multiple output pads 301 may be divided into four rows, one row, two rows, or five rows, etc., and the number of rows of output pads 301 may be determined according to the number of bonding contacts. Multiple input pads 302 in each row of input pads 302 can be arranged at intervals along a second direction, which is parallel to the substrate 100. In this example, the input pads 302 have one row, that is, multiple input pads 302 are arranged at intervals along the second direction in a row, but it is not limited to this. For example, the input pads 302 can be arranged in multiple rows.

[0092] In some exemplary embodiments, such as Figure 2 , Figure 5 and Figure 6 As shown, at least one row of input pads 302 and at least one row of output pads 301 can be arranged at intervals in the first direction, that is, there is space between the three rows of output pads 301 and the one row of input pads 302 where no pads 300 are arranged. The first bonding area B14 includes an input area B17 and an output area B16. The input area B17 can be located on the side of the output area B16 away from the display area AA in the first direction. The orthographic projection of all input pads 302 on the substrate 100 is located in the input area B17, and the orthographic projection of all output pads 301 on the substrate 100 is located in the output area B16.

[0093] In some exemplary embodiments, such as Figure 2 , Figure 5 and Figure 6 As shown, the groove 400 is located between at least one row of input pads 302 and at least one row of output pads 301. That is, the groove 400 can be located in the blank area between one row of input pads 302 and three rows of output pads 301. It can also be understood that the groove 400 can be located between the input area B17 and the output area B16. Thus, the groove 400 can be staggered from the pads 300 in the third direction.

[0094] In some exemplary embodiments, such as Figure 2 , Figure 5 and Figure 6 As shown, the groove 400 can extend along the second direction, and the groove 400 protrudes from both ends of the second direction, respectively, three rows of output pads 301 at both ends of the second direction. For example, the output pads 301 at both ends of the second direction of a row of output pads 301 can be a first output pad 303 and a second output pad 304. The first output pad 303 is located at one end of the row of output pads 301 in the second direction (i.e., the first output pad 303 can be the leftmost output pad 301 of the row of output pads 301), and the second output pad 304 is located at the other end of the row of output pads 301 in the second direction (i.e., the second output pad 304 can be the rightmost output pad 301 of the row of output pads 301). The groove 400 extends from one end in the second direction (i.e., the leftmost end of the groove 400) at the first output pad 303 towards the side of the first output pad 303 away from the other output pads 301 in this row (continuing to extend to the left), forming that end of the groove 400 protrudes from the second end of the row of output pads 301 in the second direction. The groove 400 also extends from the other end in the second direction (i.e., the rightmost end of the groove 400) at the second output pad 304 towards the side of the second output pad 304 away from the other output pads 301 in this row (continuing to extend to the right), forming that the other end of the groove 400 protrudes from the second end of the row of output pads 301 in the second direction.

[0095] In some exemplary embodiments, such as Figure 2 , Figure 5 and Figure 6As shown, the groove 400 can extend along the second direction, and the groove 400 protrudes from both ends of a row of input pads 302 in the second direction. For example, the input pads 302 at both ends of the row of input pads 302 in the second direction can be a first input pad 305 and a second input pad 306. The first input pad 305 is located at one end of the row of input pads 302 in the second direction (i.e., the first input pad 305 can be the leftmost input pad 302 of the row of input pads 302), and the second input pad 306 is located at the other end of the row of input pads 302 in the second direction (i.e., the second input pad 306 can be the rightmost input pad 302 of the row of input pads 302). At one end of the groove 400 in the second direction (i.e., the leftmost end of the groove 400), the groove 400 continues to extend from the first input pad 305 toward the side of the first input pad 305 away from the other input pads 302 in this row (continuing to extend to the left), forming that this end of the groove 400 protrudes from the second end of the row of input pads 302 in the second direction. At the other end of the groove 400 in the second direction (i.e., the rightmost end of the groove 400), the groove 400 continues to extend from the second input pad 306 toward the side of the second input pad 306 away from the other input pads 302 in this row (continuing to extend to the right), forming that the other end of the groove 400 protrudes from the second end of the row of input pads 302 in the second direction.

[0096] In some exemplary embodiments, such as Figure 2 , Figure 5 and Figure 6 As shown, at least two grooves 400 are provided, including a first groove 401 and a second groove 402. Both the first groove 401 and the second groove 402 extend along a second direction. The first groove 401 and the second groove 402 are arranged at intervals in a first direction. The first groove 401 is located on the side of the second groove 402 closest to the output pad 301 in the first direction. Therefore, the first groove 401, positioned close to the output pad 301, can cause an inorganic layer fracture near the output pad 301. When the peeling growth reaches this fracture surface, it naturally stops at this position due to the lack of a supporting film layer, thus preventing the film layer from peeling away to the vicinity of the output pad 301. The second groove 402, positioned close to the input pad 302, can also cause an inorganic layer fracture near the input pad 302. When the peeling growth reaches this fracture surface, it naturally stops at this position due to the lack of a supporting film layer, thus preventing the film layer from peeling away to the vicinity of the input pad 302. However, it is not limited to this. For example, at least one of the first groove 401 and the second groove 402 may not extend along the second direction.

[0097] In some exemplary embodiments, such as Figure 2 , Figure 5 and Figure 6As shown, the circuit structure layer 200 also includes an array test unit 500, which is located between the input pad 302 and the output pad 301 in a first direction. The array test unit 500 plays a crucial role in the manufacturing of the display substrate, and its main functions include detecting electrical performance, identifying defects, improving yield, supporting high-resolution displays, data recording and analysis, and supporting repair processes. A first groove 401 is located between the array test unit 500 and the row output pad 301 in the first direction, and a second groove 402 is located between the array test unit 500 and at least one row of input pads 302 in the first direction.

[0098] Figure 7 This is a partial schematic diagram of another display substrate according to this exemplary embodiment. In some exemplary embodiments, such as Figure 7 As shown, the groove 400 is provided, namely a first groove 401, which extends along the second direction. The first groove 401 is located near the output pad 301, and no groove 400 is provided on the side near the input pad 302. However, it is not limited to this. For example, the first groove 401 is located on the side near the input pad 302.

[0099] Figure 8 This is a partial schematic diagram of another display substrate according to this exemplary embodiment. In some exemplary embodiments, such as Figure 8 As shown, at least two grooves 400 are provided, each including a first groove 401 and a second groove 402. Both the first groove 401 and the second groove 402 extend along a second direction and are spaced apart in the second direction. Both the first groove 401 and the second groove 402 are located close to the output pad 301. However, this is not a limitation. For example, the number of grooves 400 may be three, four, or five, and multiple grooves 400 may be spaced apart in the first or second direction.

[0100] Figure 9 This is a partial schematic diagram of another display substrate according to this exemplary embodiment. In some exemplary embodiments, such as Figure 9 As shown, a groove 400 is provided. The groove 400 can be annular. In this example, the groove 400 can be a rectangular annular shape. The groove 400 can surround the array test unit 500.

[0101] Figure 10 This is a partial schematic diagram of another display substrate according to this exemplary embodiment. In some exemplary embodiments, such as Figure 10As shown, multiple grooves 400 are provided, and these grooves 400 can be located on the outer periphery of the array test unit 500. The multiple grooves 400 include a first groove 401, a second groove 402, a third groove 411, and a fourth groove 412. The third groove 411 and the fourth groove 412 can be located on opposite sides of the array test unit 500 in a second direction. The third groove 411 and the fourth groove 412 both extend along the first direction, but are not limited thereto. For example, the third groove 411 and the fourth groove 412 can extend along other directions. The third groove 411 can be spaced apart from the first groove 401 and the second groove 402, and the fourth groove 412 can be spaced apart from the first groove 401 and the second groove 402. The first groove 401, the second groove 402, and the third groove 411 and the fourth groove 412 are arranged on the outer periphery of the array test unit 500, forming multiple grooves 400 intermittently arranged in a ring shape.

[0102] Figure 11 This is a partial schematic diagram of another display substrate according to this exemplary embodiment. In some exemplary embodiments, such as Figure 11 As shown, multiple recesses 400 are provided, and the multiple recesses 400 may include a first recess 401 and a second recess 402. Both the first recess 401 and the second recess 402 are located between the input pad 302 and the output pad 301. The first recess 401 and the second recess 402 may be located on opposite sides of the array test unit 500 in the second direction. Both the first recess 401 and the second recess 402 extend along the first direction, but are not limited thereto; for example, one of the first recess 401 and the second recess 402 may extend along another direction intersecting the first direction.

[0103] Figure 12 This is a partial schematic diagram of another display substrate according to this exemplary embodiment. In some exemplary embodiments, such as Figure 12As shown, multiple recesses 400 are provided, which may include multiple first recesses 401 and multiple second recesses 402. The multiple first recesses 401 and second recesses 402 are all located between the input pad 302 and the output pad 301, and the first recesses 401 and second recesses 402 may be located on opposite sides of the array test unit 500 in a first direction. The multiple first recesses 401 may include multiple third recesses 411 and fourth recesses 412, both of which extend along a second direction. The third recesses 411 and fourth recesses 412 are spaced apart in the first direction, and are also staggered in the second direction. The third groove 411 and the fourth groove 412 are staggered in the second direction, meaning that at least one end of the third groove 411 and the fourth groove 412 is not located between the two ends of the second direction. For example, at least one end of the third groove 411 is not located between the two ends of the fourth groove 412, and at least one end of the fourth groove 412 is not located between the two ends of the third groove 411. A plurality of first grooves 401 can block the array test unit 500 and at least one row of output pads 301. The aggregate of the plurality of first grooves 401 protrudes from at least one row of output pads 301 at both ends of the second direction. A plurality of second grooves 402 may include a plurality of fifth grooves 413 and sixth grooves 414, both extending along the second direction. The fifth grooves 413 and sixth grooves 414 are spaced apart in the first direction and staggered in the second direction. The fifth groove 413 and the sixth groove 414 are staggered in the second direction, meaning that at least one end of the fifth groove 413 and the sixth groove 414 is not located between the two ends in the second direction. For example, at least one end of the fifth groove 413 is not located between the two ends in the second direction, and at least one end of the sixth groove 414 is not located between the two ends in the second direction. A plurality of second grooves 402 can block the array test unit 500 and at least one row of input pads 302, and the aggregate of the plurality of second grooves 402 protrudes from at least one row of input pads 302 at both ends in the second direction. In some exemplary embodiments, such as... Figure 2 , Figure 5 and Figure 6As shown, the circuit structure layer 200 comprises multiple inorganic insulating layers 201, at least one organic insulating layer, multiple conductor layers, and a first semiconductor layer 210. The multiple inorganic insulating layers 201 may include a touch insulating layer 202, a touch buffer layer 203, a first interlayer dielectric layer 204, a first gate insulating layer 205, a second gate insulating layer 206, a third gate insulating layer 207, and a first buffer layer 208, sequentially stacked in a third-side-up orientation close to the substrate 100. The material of the inorganic insulating layers 201 may be an inorganic material, such as silicon nitride, silicon oxide, or other materials that support metal layer isolation; in this example, the inorganic insulating layer 201 may be silicon oxide.

[0104] In some exemplary embodiments, such as Figure 2 , Figure 5 and Figure 6 As shown, the multiple conductor layers may include a first conductive layer 211, a second conductive layer 212, and a third conductive layer 213 arranged sequentially away from the substrate. The conductor layers are made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti. The first conductive layer 211 is located between the third gate insulating layer 207 and the second gate insulating layer 206, and the second conductive layer 212 and the third conductive layer 213 are located between the touch buffer layer 203 and the first interlayer dielectric layer 204. A fourth conductive layer 209 is provided on the side of the circuit structure layer 200 away from the substrate 100. The material of the fourth conductive layer 209 may be a metallic material. The fourth conductive layer 209 may include an input pad 302 and an output pad 301. The input pad 302 and the output pad 301 may be electrically connected to the third conductive layer 213 through vias. The orthographic projection of the groove 400 on the substrate 100 overlaps with the orthographic projection of at least one conductive layer on the substrate 100. For example, the orthographic projection of the first groove 401 on the substrate 100 overlaps with the orthographic projection of the first conductive layer 211 on the substrate 100, while the orthographic projection of the second groove 402 on the substrate 100 does not overlap with the orthographic projection of the conductive layer on the substrate 100.

[0105] In some exemplary embodiments, such as Figure 2 , Figure 5 and Figure 6As shown, the first semiconductor layer 210 may be located between the third gate insulating layer 207 and the first buffer layer 208. The first semiconductor layer 210 can be connected through vias and the second conductive layer 212. The material of the first semiconductor layer 210 may include semiconductor materials such as polycrystalline silicon and monocrystalline silicon. At least one organic insulating layer may include a first organic layer 214 and a second organic layer 215. The first organic layer 214 is located on the side of the second organic layer 215 away from the substrate 100. The materials of the first organic layer 214 and the second organic layer 215 may include polyimide, acrylic resin, etc. In some exemplary embodiments, the first organic layer 214 and the second organic layer 215 are located between the first interlayer dielectric layer 204 and the touch buffer layer 203. The orthographic projections of the first organic layer 214 and the second organic layer 215 on the substrate 100 and the orthographic projections of the groove 400 on the substrate 100 do not overlap.

[0106] Figure 13 for Figure 6 A magnified view of part B in the diagram. Figure 14 for Figure 6 A partially enlarged schematic diagram at point C in the diagram, as shown in some exemplary embodiments, such as Figure 5 , Figure 6 , Figure 13 and Figure 14As shown, the groove 400 is configured to penetrate the touch insulating layer 202 and the touch buffer layer 203 in a direction perpendicular to the substrate 100 (i.e., a third direction). Specifically, the first groove 401 extends from the end face of the touch insulating layer 202 away from the touch buffer layer 203 to the end face of the touch buffer layer 203 near the first interlayer dielectric layer 204, thus penetrating both the touch insulating layer 202 and the touch buffer layer 203 and exposing the first interlayer dielectric layer 204. In the third direction, the first groove 401 may include a first through-hole 403 penetrating the touch insulating layer 202 and a second through-hole 404 penetrating the touch buffer layer 203. The first through-hole 403 and the second through-hole 404 are connected, and the orthographic projection of the first through-hole 403 on the substrate 100 overlaps with the orthographic projection of the second through-hole 404 on the substrate 100. However, this is not a limitation; the orthographic projections of the first through-hole 403 and the second through-hole 404 on the substrate 100 overlap but do not completely overlap. The second groove 402 extends from the end face of the touch insulating layer 202 away from the touch buffer layer 203 to the end face of the touch buffer layer 203 near the first interlayer dielectric layer 204, such that the first groove 401 penetrates the touch insulating layer 202 and the touch buffer layer 203 to expose the first interlayer dielectric layer 204. In a third direction, the second groove 402 may include a third through-hole 405 penetrating the touch insulating layer 202 and a fourth through-hole 406 penetrating the touch buffer layer 203. The third through-hole 405 and the fourth through-hole 406 are connected, and the orthographic projections of the third through-hole 405 and the fourth through-hole 406 on the substrate 100 overlap. However, it is not limited to this; the orthographic projections of the third through-hole 405 and the fourth through-hole 406 on the substrate 100 overlap but do not overlap completely.

[0107] In some exemplary embodiments, such as Figure 5 , Figure 6 , Figure 13 and Figure 14As shown, the width (L1) of the first groove 401 can be equal to the width (L2) of the second groove 402, i.e., L1 = L2. The width of the first groove 401 can be the dimension of the first groove 401 in the first direction, and the width of the second groove 402 can be the dimension of the second groove 402 in the first direction. The depth (H1) of the first groove 401 can be equal to the depth (H2) of the second groove 402, i.e., H1 = H2. The depth of the first groove 401 can be the dimension of the first groove 401 in the third direction, and the depth of the second groove 402 can be the dimension of the second groove 402 in the third direction. The number of first grooves 401 penetrating the inorganic insulating layer 201 is n, where n = 2, and the number of second grooves 402 penetrating the inorganic insulating layer 201 is m, where m = 2, i.e., m = n. However, this is not the only possibility. For example, the number of times the first groove 401 penetrates the inorganic insulating layer 201 is not equal to the number of times the second groove 402 penetrates the inorganic insulating layer 201, i.e., m ≠ n; or for example, n = 2, m = 3, m > n, H1 < H2.

[0108] Figure 15 This is a cross-sectional schematic diagram of another display substrate according to this exemplary embodiment. Figure 16 for Figure 15 A partially enlarged schematic diagram at point D in the diagram, as shown in some exemplary embodiments, such as Figure 15 and Figure 16 As shown, at least one groove 400 is configured to penetrate the first interlayer dielectric layer 204 in a direction perpendicular to the substrate 100 (i.e., a third direction). A second groove 402 extends from the end face of the touch insulating layer 202 away from the touch buffer layer 203 to the end face of the first interlayer dielectric layer 204 near the first gate insulating layer 205, such that the second groove 402 penetrates the touch insulating layer 202, the touch buffer layer 203, and the first interlayer dielectric layer 204 to expose the first gate insulating layer 205. The second groove 402 may, in a third direction, include a third through-hole 405 penetrating the touch insulating layer 202, a fourth through-hole 406 penetrating the touch buffer layer 203, and a fifth through-hole 407 penetrating the first interlayer dielectric layer 204. The third through-hole 405, the fourth through-hole 406, and the fifth through-hole 407 are sequentially connected, and the orthographic projections of the third through-hole 405, the fourth through-hole 406, and the fifth through-hole 407 on the substrate 100 overlap. Thus, the number of inorganic insulating layers 201 penetrated by the second groove 402 is m, where m = 3, causing the second groove 402 to disconnect three layers of inorganic insulating layers 201.

[0109] Figure 17 This is a cross-sectional schematic diagram of another display substrate according to this exemplary embodiment. Figure 18 for Figure 17 A partially enlarged schematic diagram at point D in the diagram, as shown in some exemplary embodiments, such as Figure 17 and Figure 18As shown, at least one groove 400 is configured to penetrate the first gate insulating layer 205 in a direction perpendicular to the substrate 100 (i.e., a third direction). A second groove 402 extends from the end face of the touch insulating layer 202 away from the touch buffer layer 203 to the end face of the first gate insulating layer 205 near the second gate insulating layer 206, such that the second groove 402 penetrates the touch insulating layer 202, the touch buffer layer 203, the first interlayer dielectric layer 204 and the first gate insulating layer 205, to expose the second gate insulating layer 206. The second groove 402 may, in a third direction, include a third through-hole 405 penetrating the touch insulating layer 202, a fourth through-hole 406 penetrating the touch buffer layer 203, a fifth through-hole 407 penetrating the first interlayer dielectric layer 204, and a sixth through-hole 408 penetrating the first gate insulating layer 205. The third through-hole 405, the fourth through-hole 406, the fifth through-hole 407, and the sixth through-hole 408 are sequentially connected. The orthographic projections of the third through-hole 405, the fourth through-hole 406, the fifth through-hole 407, and the sixth through-hole 408 on the substrate 100 overlap. Thus, the number of inorganic insulating layers 201 penetrated by the second groove 402 is m, where m = 4, causing the second groove 402 to disconnect four layers of inorganic insulating layers 201.

[0110] Figure 19 This is a cross-sectional schematic diagram of another display substrate according to this exemplary embodiment. Figure 20 for Figure 19 A partially enlarged schematic diagram at point E in the diagram, as shown in some exemplary embodiments, such as Figure 19 and Figure 20As shown, at least one groove 400 is configured to penetrate the second gate insulating layer 206 in a direction perpendicular to the substrate 100 (i.e., the third direction). The second groove 402 extends from the end face of the touch insulating layer 202 away from the touch buffer layer 203 to the end face of the second gate insulating layer 206 near the third gate insulating layer 207, such that the second groove 402 penetrates the touch insulating layer 202, the touch buffer layer 203, the first interlayer dielectric layer 204, the first gate insulating layer 205 and the second gate insulating layer 206, to expose the third gate insulating layer 207. The second groove 402 may, in a third direction, include a third through-hole 405 penetrating the touch insulating layer 202, a fourth through-hole 406 penetrating the touch buffer layer 203, a fifth through-hole 407 penetrating the first interlayer dielectric layer 204, a sixth through-hole 408 penetrating the first gate insulating layer 205, and a seventh through-hole 409 penetrating the second gate insulating layer 206. The third through-hole 405, fourth through-hole 406, fifth through-hole 407, sixth through-hole 408, and seventh through-hole 409 are sequentially connected. The orthographic projections of the third through-hole 405, fourth through-hole 406, fifth through-hole 407, sixth through-hole 408, and seventh through-hole 409 onto the substrate 100 overlap. Thus, the second groove 402 penetrates m inorganic insulating layers 201, where m = 5, causing the second groove 402 to disconnect five inorganic insulating layers 201.

[0111] Figure 21 This is a cross-sectional schematic diagram of another display substrate according to this exemplary embodiment. Figure 22 for Figure 21 A partially enlarged schematic diagram at point F in the diagram, as shown in some exemplary embodiments, such as Figure 21 and Figure 22As shown, at least one groove 400 is configured to penetrate the third gate insulating layer 207 in a direction perpendicular to the substrate 100 (i.e., the third direction). A second groove 402 extends from the end face of the touch insulating layer 202 away from the touch buffer layer 203 to the end face of the third gate insulating layer 207 near the substrate 100, such that the second groove 402 penetrates the touch insulating layer 202, the touch buffer layer 203, the first interlayer dielectric layer 204, the first gate insulating layer 205, the second gate insulating layer 206, and the third gate insulating layer 207 to expose the first buffer layer 208. The second groove 402 may include, in a third direction, a third through hole 405 penetrating the touch insulating layer 202, a fourth through hole 406 penetrating the touch buffer layer 203, a fifth through hole 407 penetrating the first interlayer dielectric layer 204, a sixth through hole 408 penetrating the first gate insulating layer 205, a seventh through hole 409 penetrating the second gate insulating layer 206, and an eighth through hole 410 penetrating the third gate insulating layer 207. The third through hole 405, the fourth through hole 406, the fifth through hole 407, the sixth through hole 408, the seventh through hole 409, and the eighth through hole 410 are sequentially connected. The orthographic projections of the third through hole 405, the fourth through hole 406, the fifth through hole 407, the sixth through hole 408, the seventh through hole 409, and the eighth through hole 410 on the substrate 100 overlap. Therefore, the number of inorganic insulating layers 201 penetrated by the second groove 402 is m, where m = 6, so that the second groove 402 breaks through six layers of inorganic insulating layers 201.

[0112] In some exemplary embodiments, such as Figure 2 , Figure 5 and Figure 6 As shown, during the fabrication of the display substrate, each inorganic insulating layer 201 can be deposited on the substrate 100 first, and then part of the material of the inorganic insulating layer can be removed by dry etching to form the groove 400 mentioned above.

[0113] In some exemplary embodiments, a display device includes the aforementioned display substrate. The display device provided in this disclosure can be applied to electronic devices, which can be mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, in-vehicle displays, or any product or component with display functionality, such as wearable devices, smartwatches, smart bracelets, smart glasses, smart headphones, smart clothing, head-mounted displays, etc.

[0114] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0115] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0116] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0117] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0118] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0119] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0120] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, characterized in that, include: The substrate includes a display area and a first border area located on one side of the display area, the first border area including a first bonding area; Multiple sub-pixels are located on one side of the substrate and within the display area; Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, and the multiple data lines are configured to transmit data signals to the multiple sub-pixels; Multiple pads are located in the first bonding area, and the multiple pads are configured to be bonded to the driver chip; Multiple data transmission lines are located in the first border area, and the multiple data transmission lines connect the multiple data lines and at least a portion of the multiple pads; A circuit structure layer is disposed on the substrate. The circuit structure layer has a groove on the end face away from the substrate. The orthographic projection of the groove on the substrate is located in the first bonding area and does not overlap with the orthographic projection of the plurality of pads on the substrate. The circuit structure layer includes a plurality of inorganic insulating layers stacked in a direction perpendicular to the substrate, and the groove is configured to penetrate at least one of the inorganic insulating layers in a direction perpendicular to the substrate.

2. The display substrate according to claim 1, characterized in that, The plurality of pads include at least one row of input pads and at least one row of output pads, the at least one row of input pads and the at least one row of output pads being arranged at a distance in a first direction, the groove being located between the at least one row of input pads and the at least one row of output pads, the first direction being parallel to the substrate.

3. The display substrate according to claim 2, characterized in that, The groove is provided with at least two, and the at least two grooves include a first groove and a second groove, the first groove and the second groove being arranged at intervals in the first direction.

4. The display substrate according to claim 3, characterized in that, The circuit structure layer further includes an array test unit, which is located in the first direction between the at least one row of input pads and the at least one row of output pads; The first groove is located between the array test unit and the at least one row of output pads in the first direction, and the second groove is located between the array test unit and the at least one row of input pads in the first direction.

5. The display substrate according to claim 3, characterized in that, The first groove has multiple recesses, including a third groove and a fourth groove spaced apart in the first direction. The third groove and the fourth groove are staggered in a second direction, which is parallel to the base and perpendicular to the first direction; and / or The second groove is provided in multiple ways, including a fifth groove and a sixth groove arranged at intervals in the first direction, and the fifth groove and the sixth groove are staggered in the second direction.

6. The display substrate according to claim 2, characterized in that, The groove is a closed ring or an intermittently arranged ring on a plane parallel to the base.

7. The display substrate according to claim 6, characterized in that, The circuit structure layer further includes an array test unit located between the at least one row of input pads and the at least one row of output pads in the first direction, and the groove is configured to surround the array test unit.

8. The display substrate according to claim 2, characterized in that, The groove is provided with at least two, and the at least two grooves include a first groove and a second groove. The first groove and the second groove are arranged at intervals in a second direction, which is parallel to the base and perpendicular to the first direction.

9. The display substrate according to claim 8, characterized in that, The circuit structure layer further includes an array test unit, which is located between the at least one row of input pads and the at least one row of output pads in the first direction, and the first groove and the second groove are respectively disposed on both sides of the array test unit in the second direction.

10. The display substrate according to claim 2, characterized in that, The groove is provided in at least two parts, including a first groove and a second groove, wherein the size of the first groove in the direction perpendicular to the base is not equal to the size of the second groove in the direction perpendicular to the base.

11. The display substrate according to claim 10, characterized in that, The first groove has a dimension H1 in the direction perpendicular to the base, and the second groove has a dimension H2 in the direction perpendicular to the base, where H1 < H2; The number of the first grooves penetrating the inorganic insulating layer is n, and the number of the second grooves penetrating the inorganic insulating layer is m, where n < m.

12. The display substrate according to claim 2, characterized in that, The groove is configured to extend along a second direction, and at least one row of input pads and at least one row of output pads are configured to be arranged along the second direction, which is perpendicular to the first direction and parallel to the substrate.

13. The display substrate according to claim 12, characterized in that, The groove is configured to protrude from both ends of the at least one row of input pads in the second direction; and / or The groove at both ends in the second direction is configured to protrude from both ends of the at least one row of output pads in the second direction.

14. The display substrate according to claim 2, characterized in that, The plurality of inorganic insulating layers include a touch insulating layer and a touch buffer layer, wherein the touch insulating layer is located on the side of the touch buffer layer away from the substrate, and the groove is configured to penetrate the touch insulating layer and the touch buffer layer in a direction perpendicular to the substrate.

15. The display substrate according to claim 14, characterized in that, The plurality of inorganic insulating layers further include a first interlayer dielectric layer, which is located on the side of the touch buffer layer near the substrate, and the groove is configured to penetrate the first interlayer dielectric layer in a direction perpendicular to the substrate.

16. The display substrate according to claim 15, characterized in that, The circuit structure layer further includes multiple organic insulating layers, including a first organic layer located between the first interlayer dielectric layer and the touch buffer layer, wherein the orthographic projection of the first organic layer on the substrate and the orthographic projection of the groove on the substrate do not overlap.

17. The display substrate according to claim 15, characterized in that, The plurality of inorganic insulating layers further include a first gate insulating layer, the first gate insulating layer being located on the side of the first interlayer dielectric layer near the substrate, and the groove being configured to penetrate the first gate insulating layer in a direction perpendicular to the substrate.

18. The display substrate according to claim 17, characterized in that, The plurality of inorganic insulating layers further include a second gate insulating layer and a third gate insulating layer, wherein the third gate insulating layer, the second gate insulating layer and the first gate insulating layer are arranged sequentially in a direction away from the substrate, and the groove is configured to penetrate the second gate insulating layer and the third gate insulating layer in a direction perpendicular to the substrate.

19. The display substrate according to any one of claims 1 to 18, characterized in that, The circuit structure layer further includes at least one conductive layer, and the orthographic projection of the groove on the substrate overlaps with the orthographic projection of the at least one conductive layer on the substrate.

20. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 19.

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